Xilinx v1.00a - Manual

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PDF Text Table of Contents

Table of Contents:

• Page 2 – ChipScope PLB46 IBA I/O Signals; IBA_PLBv46 Pin Descriptions
• Page 5 – ChipScope PLB46 IBA Parameters; Table 2; IBA_PLBv46 Design Parameters
• Page 10 – ChipScope PLB46 IBA Block Diagram; clk; Date; Initial release

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DS619 (v1.0) September 17, 2007

www.xilinx.com

Product Specification

1

© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at

http://www.xilinx.com/legal.htm

.

PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.

I

Introduction

The ChipScope™ PLB IBA core is a specialized Bus
Analyzer core designed to debug embedded systems that
contain the IBM CoreConnect™ Processor Local Bus (PLB)
version 4.6. The ChipScope PLB46 IBA core in EDK is
based on a Tcl script that generates an HDL wrapper to the
PLB IBA and calls the ChipScope Core Generator to
generate the netlist based on user parameters.

Features

The ChipScope PLBv46 IBA is a soft IP core designed for
Xilinx® FPGAs and contains the following features:

•

Probes the master, slave, arbiter, and error status
signals of the PLBv46 bus

•

Probes the PLBv46 OR'ed slave signals

•

Automatically adjusts ports to the PLBv46 bus width

•

Separates master, slave, and error status signals into
independent match units which can be enabled or
disabled by a design parameter

•

Allows independent enabling or disabling of probed
master, slave, and error status signals for data capture

•

Suppor ts trigger port customization by a design
parameter

•

Suppor ts match unit type customization for each trigger
port by a design parameter

•

Suppor ts sample depths from 1024-131,072 on
Virtex™-5 Devices selectable by a design parameter

•

Can probe as few as 1 signals and as many as 1115
signals on a Virtex-5 device

•

Provides a separate input bus to allow a user-defined
input debug port

•

Suppor ts a trigger output indicator pin that can be sent
off chip or to other cores

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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)

DS619 (v1.0) September 17, 2007

Product Specification

R

LogiCORE™ Facts

Core Specifics

Supported Device
Family

Virtex-E, Virtex, Spartan™-3A DSP,
Spartan-3AN, Spartan-3A, Spartan-3E,
Spartan-3, Spartan-IIE, Spartan-II, Virtex-5
LX, Virtex-5 LXT Virtex-5 SXT, Virtex-4 FX,
Virtex-4 LX, Virtex-4 SX, Virtex-II Pro,
Virtex-II, Virtex-II Pro, Virtex-4

Version of Core

chipscope_plb46_iba

V1.00a

Resources Used

Min

Max

Slices

LUTs

FFs

Block RAMs

Provided with Core

Documentation

Product Specification

Design File
Formats

VHDL/EDIF

Constraints File

N/A

Verification

N/A

Instantiation
Template

N/A

Reference Designs None

Design Tool Requirements

Xilinx
Implementation
Tools

ISE™ 9.2i or later

Verification

ChipScope Pro 9.2i or later

Simulation

Not supported in simulation

Synthesis

XST

Support

Provided by Xilinx, Inc.

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