Xilinx UG129 - Manual

Xilinx UG129

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Table of Contents:

  • Page 2 – Revision History
  • Page 3 – Preface; Limitations; Limited Warranty and Disclaimer
  • Page 4 – Acknowledgments
  • Page 5 – About This Guide; Guide Contents
  • Page 7 – Preface: Limitations; Table of Contents
  • Page 8 – Chapter 4: Interrupts
  • Page 9 – Chapter 8: Performance
  • Page 10 – Appendix A: Related Materials and References
  • Page 11 – Chapter 1; Introduction; PicoBlaze Microcontroller Features
  • Page 12 – PicoBlaze Microcontroller Functional Blocks; General-Purpose Registers
  • Page 14 – Program Flow Control
  • Page 15 – Why the PicoBlaze Microcontroller?
  • Page 17 – Chapter 2; PicoBlaze Interface Signals; PicoBlaze Microcontroller
  • Page 19 – Chapter 3; PicoBlaze Instruction Set
  • Page 22 – Address Spaces
  • Page 24 – Processing Data; Logic Instructions
  • Page 25 – Complement/Invert Register
  • Page 26 – Clear Bit; Arithmetic Instructions; ADD and ADDCY Add Instructions
  • Page 27 – SUB and SUBCY Subtract Instructions
  • Page 28 – Negate; Multiplication
  • Page 30 – Division
  • Page 32 – Setting and Clearing CARRY Flag; Clear CARRY Flag; Test and Compare
  • Page 34 – Compare; Shift and Rotate Instructions; Shift
  • Page 35 – Rotate
  • Page 36 – Moving Data
  • Page 41 – Chapter 4; Interrupts
  • Page 43 – CLK
  • Page 45 – Chapter 5; Scratchpad RAM; Address Modes; Direct Addressing; Indirect Addressing
  • Page 46 – Implementing a Look-Up Table
  • Page 47 – Stack Operations
  • Page 49 – Chapter 6; Input and Output Ports
  • Page 50 – INPUT Operations; FPGA Logic
  • Page 52 – Applications with Few Input Sources
  • Page 53 – OUTPUT Operations
  • Page 54 – Simple Output Structure for Few Output Destinations
  • Page 56 – Pipelining for Maximum Performance
  • Page 58 – Repartitioning the Design for Maximum Performance
  • Page 59 – Chapter 7; Instruction Storage Configurations; Standard Configuration – Single 1Kx18 Block RAM; Instruction ROM
  • Page 60 – Standard Configuration with UART or JTAG Programming Interface; Block RAM
  • Page 61 – Distributed ROM Instead of Block RAM; Distributed ROM
  • Page 63 – Chapter 8; Performance; Input Clock Frequency; Predicting Executing Performance
  • Page 65 – Chapter 9; PicoBlaze Development Tools; Assembler
  • Page 66 – Assembly Errors
  • Page 67 – Mediatronix pBlazIDE; Configuring pBlazIDE for the PicoBlaze Microcontroller
  • Page 68 – Importing KCPSM3 Code into pBlazIDE
  • Page 69 – Differences Between the KCPSM3 Assembler and pBlazIDE
  • Page 71 – VHDL Design Flow; KCPSM3 Module
  • Page 72 – Connecting the Program ROM
  • Page 73 – Black Box Instantiation of KCPSM3 using KCPSM3.ngc; Generating the Program ROM using prog_rom.coe; Verilog Design Flow
  • Page 75 – Assembler Directives; Locating Code at a Specific Address
  • Page 76 – Defining Constants; Naming the Program ROM Output File; pBlazIDE
  • Page 77 – Input Por ts; Output Por ts
  • Page 79 – Custom Instruction Op-Codes
  • Page 81 – Simulating PicoBlaze Code
  • Page 82 – Instruction Set Simulation with pBlazIDE
  • Page 83 – Simulator Control Buttons
  • Page 85 – Turbocharging Simulation using FPGAs!
  • Page 87 – Appendix A; Related Materials and References
  • Page 89 – Appendix B; Example Program Templates; KCPSM3 Syntax
  • Page 90 – pBlazIDE Syntax
  • Page 91 – Appendix C; ADD sX, Operand —Add Operand to Register sX
  • Page 92 – ADDCY sX, Operand —Add Operand to Register sX with Carry
  • Page 96 – COMPARE sX, Operand — Compare Operand with Register sX
  • Page 97 – DISABLE INTERRUPT — Disable External Interrupt Input; ENABLE INTERRUPT — Enable External Interrupt Input
  • Page 98 – 4-Byte Scratchpad RAM
  • Page 100 – INTERRUPT Event, When Enabled
  • Page 102 – LOAD sX, Operand — Load Register sX with Operand
  • Page 103 – OR sX, Operand — Logical Bitwise OR Register sX with Operand
  • Page 105 – RESET Event
  • Page 108 – RL sX — Rotate Left Register sX; RR sX — Rotate Right Register sX
  • Page 113 – SUB sX, Operand —Subtract Operand from Register sX
  • Page 119 – Appendix D; Instruction Codes
  • Page 123 – Appendix E
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PicoBlaze 8-bit
Embedded Microcontroller
User Guide

for Spartan-3, Virtex-II, and
Virtex-II Pro FPGAs

UG129 (v1.1.2) June 24, 2008

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Summary

Page 2 - Revision History

PicoBlaze 8-bit Embedded Microcontroller www.xilinx.com UG129 (v1.1.2) June 24, 2008 Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of th...

Page 3 - Preface; Limitations; Limited Warranty and Disclaimer

PicoBlaze 8-bit Embedded Microcontroller www.xilinx.com 3 UG129 (v1.1.2) June 24, 2008 R Preface Limitations Limited Warranty and Disclaimer These designs are provided to you “as-is”. Xilinx and its licensors make and you receive no warranties or conditions, express, implied, statutory or otherwise,...

Page 4 - Acknowledgments

4 www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.2) June 24, 2008 Preface: Acknowledgments R Acknowledgments Xilinx thanks the following individuals for their contribution to the PicoBlaze microcontroller cause: • Henk van Kampen, Mediatronix Developer of the pBlazIDE graphical,...

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