Xilinx UG018 - Manual

Xilinx UG018

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Table of Contents:

  • Page 3 – Version
  • Page 5 – Preface: About This Guide; Table of Contents
  • Page 6 – Chapter 3: PowerPC 405 OCM Controller
  • Page 7 – Chapter 4: PowerPC 405 APU Controller
  • Page 8 – Appendix A: RISCWatch and RISCTrace Interfaces; RISCWatch Interface; Appendix B: Signal Summary; Interface Signals; Appendix C: Processor Block Timing Model; Timing Parameter Tables and Diagram; Index
  • Page 9 – Preface; About This Guide; Guide Contents
  • Page 10 – Additional Resources; Typographical; Resource; Courier bold
  • Page 11 – Online Document
  • Page 12 – General Conventions; Registers
  • Page 13 – Terms; Register
  • Page 17 – Chapter 1; PowerPC Architecture
  • Page 18 – PowerPC Embedded-Environment Architecture; Three Levels of PowerPC Architecture
  • Page 19 – Virtual Environment; Operating Environment
  • Page 20 – OEA Features of the PowerPC Embedded-Environment Architecture
  • Page 21 – PowerPC 405 Software Features
  • Page 22 – Privilege Modes; Privileged Mode; Address Translation Modes
  • Page 23 – Real Mode; Virtual Mode; Addressing Modes; Data Types
  • Page 24 – General-Purpose Registers; PowerPC 405 Registers; Privileged Registers
  • Page 25 – Special-Purpose Registers; PowerPC 405 Hardware Organization
  • Page 26 – Central-Processing Unit; PowerPC 405 Organization
  • Page 27 – Exception Handling Logic
  • Page 28 – Instruction and Data Caches
  • Page 29 – Timer Resources; Programmable Interval Timer; Debug; PowerPC 405 Interfaces
  • Page 30 – PowerPC 405 Performance
  • Page 31 – PowerPC 405 Cycles per Instruction
  • Page 33 – Chapter 2; Input/Output Interfaces
  • Page 34 – Signal Naming Conventions; Signal Name Prefix Definitions
  • Page 35 – Clock and Power Management Interface; Prefix1 or Prefix2
  • Page 36 – CPM Interface I/O Signal Summary
  • Page 37 – CPM Interface I/O Signal Descriptions; Signal
  • Page 39 – System Design Considerations for Clock Domains
  • Page 40 – PLB; Virtex-II Pro and ProX Specific; OCM
  • Page 41 – CPU Control Interface; CPU Control Interface I/O Signal Summary
  • Page 42 – CPU Control Interface I/O Signal Descriptions
  • Page 43 – Reset Interface; Reset Requirements
  • Page 44 – Reset Interface I/O Signal Summary
  • Page 45 – Reset Interface I/O Signal Descriptions
  • Page 47 – Instruction-Side Processor Local Bus Interface; Instruction-Side PLB Operation
  • Page 48 – Interaction with the ICU Fill Buffer
  • Page 49 – Prefetch and Address Pipelining
  • Page 50 – Guarded Storage; Instruction-Side PLB Interface Block Symbol
  • Page 51 – Instruction-Side PLB Interface I/O Signal Descriptions; Instruction-Side PLB Interface Signal Summary
  • Page 54 – PLB-Request Priority Encoding
  • Page 57 – Attachment of ISPLB Between 32-Bit Slave and 64-Bit Master
  • Page 59 – Instruction-Side PLB Interface Timing Diagrams; ISPLB Timing Diagram Assumptions
  • Page 60 – ISPLB Timing Diagram Abbreviations
  • Page 61 – Abbreviation
  • Page 62 – ISPLB Pipelined Cacheable Sequential Fetch (Case 1)
  • Page 63 – ISPLB Pipelined Cacheable Sequential Fetch (Case 2)
  • Page 64 – ISPLB Non-Pipelined Non-Cacheable Sequential Fetch
  • Page 65 – ISPLB Pipelined Non-Cacheable Sequential Fetch
  • Page 67 – ISPLB Aborted Fetch Request
  • Page 68 – Data-Side Processor Local Bus Interface; Data-Side PLB Operation
  • Page 70 – Interaction with the DCU Fill Buffer
  • Page 71 – Address Pipelining
  • Page 73 – Data-Side PLB Interface I/O Signal Descriptions
  • Page 80 – Contents of DCU Write-Data Bus During Eight-Word Line Transfer
  • Page 83 – Contents of DCU Read-Data Bus During Eight-Word Line Transfer
  • Page 85 – Data-Side PLB Interface Timing Diagrams; DSPLB Timing Diagram Assumptions
  • Page 86 – DSPLB Three Consecutive Line Reads; DSPLB Timing Diagram Abbreviations
  • Page 88 – DSPLB Three Consecutive Word Reads
  • Page 89 – DSPLB Three Consecutive Line Writes
  • Page 91 – DSPLB Three Consecutive Word Writes
  • Page 97 – DSPLB Aborted Data-Access Request
  • Page 98 – Device-Control Register Interfaces
  • Page 99 – Internal Device Control Register (DCR) Interface
  • Page 100 – Block
  • Page 101 – External DCR Bus Interface; Dedicated EMAC DCR Bus Interface Block Symbol
  • Page 102 – DCR Chain Block Diagram
  • Page 103 – External DCR Bus Interface I/O Signal Summary; DCR Bus Implementation
  • Page 104 – Virtex-II Pro and Virtex-II ProX DCR Interface Block Symbol
  • Page 105 – External DCR Bus Interface I/O Signal Descriptions
  • Page 106 – External DCR Bus Interface Timing Diagrams
  • Page 107 – DCR Interface 1:1 Clocking, Latched Acknowledge
  • Page 108 – DCR Interface 2:1 Clocking, Latched Acknowledge
  • Page 109 – External Interrupt Controller Interface; DCR Interface 1:2 Clocking, Latched Acknowledge
  • Page 110 – EIC Interface I/O Signal Summary
  • Page 111 – EIC Interface I/O Signal Descriptions; PPC405 JTAG Debug Port; JTAG Interface I/O Signals; JTAG Interface Block Symbol
  • Page 112 – JTAG Interface I/O Signal Descriptions
  • Page 113 – JTAG Instruction Register; Device
  • Page 114 – PPC405 Instruction Opcodes
  • Page 115 – Connecting PPC405 JTAG Logic Directly to Programmable I/O
  • Page 118 – Correct Wiring of JTAG Chain with Multiplexed PPC405 Connection
  • Page 120 – Primitive
  • Page 121 – VHDL and Verilog Instantiation Templates
  • Page 128 – Debug Interface; Debug Interface I/O Signal Summary; Debug Interface Block Symbol
  • Page 129 – Debug Interface I/O Signal Descriptions; Debug Interface I/O Signals
  • Page 131 – Trace Interface; Trace Interface Signal Summary; Trace Interface Block Symbol
  • Page 132 – Trace Interface I/O Signal Descriptions; Trace Interface Signals
  • Page 133 – Bit
  • Page 134 – PVR Interface I/O Signal Summary; PVR Interface Block Symbol
  • Page 135 – PVR Interface I/O Signal Descriptions; PVR Interface I/O Signals
  • Page 136 – Additional FPGA Specific Signals; Additional FPGA I/O Signal Descriptions
  • Page 139 – Chapter 3; PowerPC 405 OCM Controller; Introduction
  • Page 140 – Comparison of Virtex-II Pro and Virtex-4 OCM Controllers; Functional Features; Common Features for DSOCM and ISOCM; Features Introduced in Virtex-4 OCM
  • Page 141 – DSOCM and ISOCM Features
  • Page 142 – OCM Controller Operation; Feature
  • Page 143 – OCM DCR-Based Control Registers (Accessed Via DCR Instructions); DSOCM Controller Load/Store Operation
  • Page 144 – Non-Memory Peripherals for DSOCM; Execution Re-ordering; ISOCM Controller Instruction Fetch Operation
  • Page 145 – DSOCM Ports; DSOCM Interface for Virtex-4; DSOCM Interface for Virtex-II Pro
  • Page 146 – DSOCM Input Ports
  • Page 147 – DSOCM Input Ports: Attributes; DSOCM Attributes
  • Page 148 – DSOCM Output Ports
  • Page 149 – Port
  • Page 152 – ISOCM Ports; ISOCM Interface for Virtex-II Pro
  • Page 153 – ISOCM Interface for Virtex-4; ISOCM Input Ports
  • Page 154 – ISOCM Input Ports, Attributes; ISOCM Attributes
  • Page 155 – ISOCM Output Ports
  • Page 157 – ISOCM to BRAM Interface: 8 KByte Example in Virtex-II Pro
  • Page 158 – Programmer’s Model; DCR Registers; DSARC/ ISARC Registers; ISOCM to BRAM Interface: 8 KByte Example in Virtex-4
  • Page 159 – DSCNTL Registers; DSCNTL Register for Virtex-II Pro
  • Page 160 – ISCNTL Registers; DSCNTL Register for Virtex-4
  • Page 161 – Features Introduced in Virtex-4 and Comparison with Virtex-II Pro; ISCNTL Register for Virtex-4
  • Page 162 – DSOCM DCR Registers for Virtex-II Pro
  • Page 163 – DSOCM DCR Registers for Virtex-4
  • Page 164 – ISOCM DCR Registers for Virtex-II Pro
  • Page 165 – ISOCM DCR Registers for Virtex-4
  • Page 166 – DCR Write Access
  • Page 167 – DCR Read Access
  • Page 170 – ISOCM Instruction Fetching
  • Page 171 – Instruction Fetch Timing
  • Page 172 – Writing to ISBRAM
  • Page 174 – DSOCM Data Load, Fixed Latency
  • Page 176 – DSOCM Store, Fixed Latency
  • Page 178 – DSOCM Data Load, Variable Latency
  • Page 179 – DSOCM Data Store, Variable Latency
  • Page 181 – Application Notes and Reference Designs; References
  • Page 183 – Chapter 4; PowerPC 405 APU Controller
  • Page 184 – FCM Instruction Processing; Pipeline Flow Diagram
  • Page 185 – Enabling the APU Controller; Autonomous Instructions; APU Controller-Related MSR Bits
  • Page 186 – Blocking Instructions; Instruction Format; FCM Instruction Format
  • Page 187 – Instruction Decoding; Floating Point Instructions; Description
  • Page 188 – FCM Load/Store Instructions
  • Page 189 – APU Controller User-Defined Instruction Decoding; FCM Pre-Defined Instruction Decoding; Integer Divide Instructions; Field
  • Page 190 – FCM User-Defined Instruction Decoding; FCM Instruction Flushing
  • Page 191 – APU Controller Configuration; General Configuration Register; APU Controller Configuration Register Bit Description
  • Page 192 – UDI Configuration Registers
  • Page 193 – DCR Access to the Configuration Registers; Interface Definition; Name
  • Page 194 – APU Controller Input Signals; FCM Interface Input Signals
  • Page 196 – APU Controller Output Signals; FCM Interface Output Signals
  • Page 197 – APU Controller Attributes
  • Page 198 – Bit Map Between TIEAPUCONTROL and APU Configuration Register
  • Page 199 – FCM Interface Timing Specification; Autonomous Transactions; APU Controller Decoded Autonomous Transaction Example
  • Page 200 – FCM Decoded Autonomous Transaction Example
  • Page 201 – Blocking Transactions; FCM Decoded Blocking Transaction Example
  • Page 202 – Non-Blocking Transactions; APU Controller Decoded Non-Blocking Transaction Example
  • Page 203 – FCM Load Instruction; APU Controller Decoded Load Instruction Example
  • Page 204 – FCM Store Instruction; APU Controller Decoded Store Instruction
  • Page 205 – FCM Exception; APU Controller Decoded Store Instruction with StoreWBOK=1
  • Page 206 – FCM Decoding Using Decode Busy Signal; FCM Decode Asserting DecodeBusy
  • Page 207 – Appendix A; RISCWatch and RISCTrace Interfaces; JTAG-Connector Physical Layout
  • Page 208 – JTAG Connector Signals for RISCWatch
  • Page 209 – RISCTrace Interface
  • Page 210 – Trace Connector Signals for RISCTrace
  • Page 213 – Appendix B; Signal Summary; PowerPC 405 Interface Signals in Alphabetical Order
  • Page 223 – Appendix C; Processor Block Timing Model; Processor Block
  • Page 224 – Clocks and Corresponding Processor Interface Blocks
  • Page 225 – Parameters Relative to the Core Clock (CPMC405CLOCK)
  • Page 226 – Parameter
  • Page 232 – Processor Block Timing Relative to Clock Edge
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PowerPC™ 405 Processor
Block Reference Guide

Embedded Development Kit

UG018 (v2.0) August 20, 2004

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Summary

Page 3 - Version

UG018 (v2.0) August 20, 2004 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.0) August 20, 2004 The following table shows the revision history for this document. Version Revision 09/16/02 1.0 Initial Embedded Developme...

Page 5 - Preface: About This Guide; Table of Contents

PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 5 UG018 (v2.0) August 20, 2004 1-800-255-7778 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Resources . . . ...

Page 6 - Chapter 3: PowerPC 405 OCM Controller

6 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide 1-800-255-7778 UG018 (v2.0) August 20, 2004 R Instruction-Side PLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Instruction-Side PLB I/O Signal Table . . . . . . . . . . . . . . . ....

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