Xilinx UG015 - Manual

Xilinx UG015

Xilinx UG015 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.

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Table of Contents:

  • Page 4 – Version
  • Page 5 – Preface: About This Manual; Additional Resources; Package Contents; Table of Contents
  • Page 6 – User Programmable Pins
  • Page 7 – Preface; About This Manual; Resource
  • Page 8 – Conventions; Typographical; Courier bold
  • Page 9 – Online Document; Convention
  • Page 11 – Features
  • Page 13 – Introduction; Virtex-II Prototype Platform Block Diagram; Service FPGA
  • Page 14 – Detailed Description; Upward On Position
  • Page 15 – Off Position; Power Supply Jacks; Voltage Ranges
  • Page 16 – Configuration Port User PROM and FPGA Header; Frequency Select Switch; Configuration Mode Switch
  • Page 17 – Master Serial PROM Mode; Master Select Map PROM Mode; RW; Master Select Map UPSTREAM Mode; CCLK
  • Page 18 – Slave Serial Mode; JTAG Mode; Select Map Mode
  • Page 19 – Configuration/Readback from the Upstream Connector; External Mode
  • Page 20 – a. Upstream System ACE Connector; b. Downstream System ACE Connector; Upstream System ACE Connector, 20-Pin Female
  • Page 21 – c. Upstream Configuration Interface Connector; Upstream Configuration Interface Connector, 44-Pin Female
  • Page 22 – d. Downstream Configuration Interface Connector; JTAG Control Switch; Downstream Configuration Interface Connector, 44-Pin Male
  • Page 23 – Chip Select Switch; PROM Daughter Card Interface
  • Page 24 – Supply Jumpers; Oscillator Sockets; Function Generator Clock Inputs
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R

Virtex-II
Prototype
Platform

User Guide

UG015 / PN0401974 (v1.1) January 14, 2003

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Summary

Page 4 - Version

Virtex-II Prototype Platform www.xilinx.com UG015 / PN0401974 (v1.1) January 14, 2003 1-800-255-7778 Virtex-II Prototype Platform UG015 / PN0401974 (v1.1) January 14, 2003 The following table shows the revision history for this document. Version Revision 06/29/01 1.0 Initial Xilinx release. 01/14/03...

Page 5 - Preface: About This Manual; Additional Resources; Package Contents; Table of Contents

Virtex-II Prototype Platform www.xilinx.com 5 UG015 / PN0401974 (v1.1) January 14, 2003 1-800-255-7778 Preface: About This Manual Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Conventions . . . . . . . . . . . ....

Page 6 - User Programmable Pins

6 www.xilinx.com Virtex-II Prototype Platform 1-800-255-7778 UG015 / PN0401974 (v1.1) January 14, 2003 R 20. Pin Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2621. User LEDs (Active-High) . . . . . . . . . . . . . . . . ...

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