Page 2 - Data Sheet; Product Specification; This page intentionally left b
Data Sheet 2 www.xilinx.com DS610 July 16, 2007 Product Specification R This page intentionally left b lank.
Page 3 - Introduction; Table 1; Spartan-3A and Spartan-3A DSP FPGA Differences; Features; MicroBlaze; Introduction and Ordering Information; Summary of Spartan-3A DSP FPGA Attributes
DS610-1 (v2.0) July 16, 2007 www.xilinx.com 3 Product Specification © 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks are the proper ty of their respective owners. Al...
Page 4 - Architectural Overview; XtremeDSP DSP48A Slice; Figure 1; Configuration; Xilinx Platform Flash PROM
Introduction and Ordering Information 4 www.xilinx.com DS610-1 (v2.0) July 16, 2007 Product Specification R Architectural Overview The Spartan-3A DSP family architecture consists of five fundamental programmable functional elements: • XtremeDSP DSP48A Slice provides an 18-bit x 18-bit multiplier, 18...
Page 5 - Block RAM; CLBs; XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide.
Introduction and Ordering Information DS610-1 (v2.0) July 16, 2007 www.xilinx.com 5 Product Specification R Figure 1: Spartan-3A DSP Family Architecture CLB Block RAM DCM IOBs IOBs DS610-1_01_031207 IOBs IOBs DCM Block RAM / DSP48A Slice DCM CLBs IOBs DSP48A Slice Notes: 1 . The XC3SD1800A and XC3SD...
Page 6 - Package Marking; Figure 2; Ordering Information; Standard Packaging; Spartan-3A DSP FPGA Package Marking Example; SPARTAN; GQ; XC; us; Device; –5 High Performance
Introduction and Ordering Information 6 www.xilinx.com DS610-1 (v2.0) July 16, 2007 Product Specification R Package Marking Figure 2 shows the top marking for Spartan-3A DSP FPGAs. Use the seven digits of the Lot Code to access additional information for a specific device using the Xilinx web-based ...
Page 7 - Revision History; The following table shows the revision history for this document.; Initial Xilinx release.
Introduction and Ordering Information DS610-1 (v2.0) July 16, 2007 www.xilinx.com 7 Product Specification R Revision History The following table shows the revision history for this document. Date Version Revision 04/02/07 1.0 Initial Xilinx release. 05/25/07 1.0.1 Minor edits. 06/18/07 1.2 Updated f...
Page 9 - XtremeDSP DSP48A for Spartan-3A DSP; Functional Description; Date
DS610-2 (v2.0) July 16, 2007 www.xilinx.com 9 Product Specification © 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks are the proper ty of their respective owners. Al...
Page 11 - DC Electrical Characteristics; Initial estimates are based on simulation, early; Unless; Absolute Maximum Ratings; Stresses beyond those listed under; DC and Switching Characteristics; Device Packaging and Thermal Characteristics; Implementation and Solder Reflow
DS610-3 (v2.0) July 16, 2007 www.xilinx.com 11 Product Specification © 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks are the proper ty of their respective owners. A...
Page 12 - Power Supply Specifications; Supply Voltage Thresholds for Power-On Reset
DC and Switching Characteristics 12 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Power Supply Specifications General Recommended Operating Conditions Table 4: Supply Voltage Thresholds for Power-On Reset Symbol Description Min Max Units V CCINTT Threshold for the V CCINT suppl...
Page 13 - General DC Characteristics for I/O Pins; Add I
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 13 Product Specification R General DC Characteristics for I/O Pins Table 8: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description Test Conditions Min Typ Max Units I L Leakage current a...
Page 14 - Quiescent Current Requirements; Quiescent Supply Current Characteristics; Using Suspend Mode in Spartan-3 Generation FPGAs
DC and Switching Characteristics 14 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Quiescent Current Requirements Table 9: Quiescent Supply Current Characteristics Symbol Description Device Power Typical (2) Commercial Maximum (2) Industrial Maximum (2) Units I CCINTQ Quiescent ...
Page 15 - for Drivers; LVTTL
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 15 Product Specification R Single-Ended I/O Standards Table 10: Recommended Operating Conditions for User I/Os Using Single-Ended Standards IOSTANDARD Attribute V CCO for Drivers (2) V REF V IL V IH Min (V) Nom (V) Max (V) ...
Page 16 - DC Characteristics of User I/Os Using
DC and Switching Characteristics 16 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Table 11: DC Characteristics of User I/Os Using Single-Ended Standards IOSTANDARD Attribute Test Conditions Logic Level Characteristics I OL (mA) I OH (mA) V OL Max (V) V OH Min (V) LVTTL (3) 2 2 ...
Page 17 - Differential I/O Standards; Differential Input Voltages; IOSTANDARD Attribute
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 17 Product Specification R Differential I/O Standards Figure 3: Differential Input Voltages Table 12: Recommended Operating Conditions for User I/Os Using Differential Signal Standards IOSTANDARD Attribute V CCO for Drivers...
Page 18 - Differential Output Voltages
DC and Switching Characteristics 18 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Figure 4: Differential Output Voltages Table 13: DC Characteristics of User I/Os Using Differential Signal Standards IOSTANDARD Attribute V OD V OCM V OH V OL Min (mV) Typ (mV) Max (mV) Min (V) Ty...
Page 19 - External Termination Requirements for Differential I/O; Device DNA Data Retention, Read Endurance; Any B; External Termination Resistors for BLVDS_25 I/O Standard; External Input Resistors Required for TMDS_33 I/O Standard; Device DNA Identifier Memory Characteristics; Symbol; Data retention, continuous usage
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 19 Product Specification R External Termination Requirements for Differential I/O LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards BLVDS_25 I/O Standard TMDS_33 I/O Standard Device DNA Data Retention, Read Endurance Figure 5: ...
Page 20 - Switching Characteristics; Software Version Requirements
DC and Switching Characteristics 20 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Switching Characteristics All Spartan-3A DSP FPGAs ship in two speed grades: –4 and the higher performance –5. Switching characteristics in this document are designated as Preview, Advance, Prelim...
Page 21 - provides the recent history of the Spartan-3A DSP; Spartan-3A DSP Speed File Version History; Minor updates
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 21 Product Specification R To create a Xilinx MySupport user account and sign up for automatic E-mail notification whenever this data sheet is updated: • Sign Up for Alerts on Xilinx MySupport www.xilinx.com/xlnx/xil_ans_di...
Page 22 - ns; add
DC and Switching Characteristics 22 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R I/O Timing Table 17: Pin-to-Pin Clock-to-Output Times for the IOB Output Path Symbol Description Conditions Device Speed Grade Units -5 -4 Max Max Clock-to-Output Times T ICKOFDCM When reading fro...
Page 27 - Timing for the IOB Three-State Path
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 27 Product Specification R Table 22: Timing for the IOB Output Path Symbol Description Conditions Device Speed Grade Units -5 -4 Max Max Clock-to-Output Times T IOCKP When reading from the Output Flip-Flop (OFF), the time f...
Page 31 - Timing Measurement Methodology; Figure 8; Output Test Setup; FPGA Output; Test Methods for Timing Measurement at I/Os
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 31 Product Specification R Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 25 lists the conditions to use for ea...
Page 32 - The capacitive load (C; The Output timing for all standards, as published
DC and Switching Characteristics 32 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R The capacitive load (C L ) is connected between the output and GND. The Output timing for all standards, as published in the speed files and the data sheet, is always based on a C L value of zero....
Page 33 - Using IBIS Models to Simulate Load Conditions in Application; Simultaneously Switching Output Guidelines; Equivalent V
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 33 Product Specification R Using IBIS Models to Simulate Load Conditions in Application IBIS models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS model (V REF...
Page 34 - Recommended Number of Simultaneously
DC and Switching Characteristics 34 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Table 27: Recommended Number of Simultaneously Switching Outputs per V CCO -GND Pair (V CCAUX =3.3V) Signal Standard (IOSTANDARD) Package Type CS484, FG676 Top, Bottom (Banks 0,2) Left, Right (Ban...
Page 35 - Generation FPGA User Guide; Managing Ground Bounce in Large; Signal Standard
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 35 Product Specification R LVCMOS15 Slow 2 55 55 4 31 31 6 18 18 8 – 15 12 – 10 Fast 2 25 25 4 10 10 6 6 6 8 – 4 12 – 3 QuietIO 2 70 70 4 40 40 6 31 31 8 – 31 12 – 20 LVCMOS12 Slow 2 40 40 4 – 25 6 – 18 Fast 2 31 31 4 – 13 ...
Page 37 - Clock Buffer/Multiplexer Switching Characteristics; CLB Distributed RAM Switching Characteristics
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 37 Product Specification R Clock Buffer/Multiplexer Switching Characteristics Table 29: CLB Distributed RAM Switching Characteristics Symbol Description Speed Grade Units -5 -4 Min Max Min Max Clock-to-Output Times T SHCKO ...
Page 38 - Block RAM Timing
DC and Switching Characteristics 38 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Block RAM Timing Table 32: Block RAM Timing Symbol Description Speed Grade Units -5 -4 Min Max Min Max Clock-to-Output Times T RCKO_DOA_NC When reading from block RAM, the delay from the active tr...
Page 39 - To reference the DSP48A block diagram, see the; XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 39 Product Specification R DSP48A Timing To reference the DSP48A block diagram, see the XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide ( UG431 ). Table 33: Setup Times for the DSP48A Symbol Description Preadder Multipl...
Page 42 - Switching Characteristics for the DLL
DC and Switching Characteristics 42 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Table 36: Switching Characteristics for the DLL Symbol Description Device Speed Grade Units -5 -4 Min Max Min Max Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs...
Page 43 - Input Frequency Ranges; Input Clock Jitter Tolerance; Switching Characteristics for the DFS
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 43 Product Specification R Digital Frequency Synthesizer (DFS) Table 37: Recommended Operating Conditions for the DFS Symbol Description Speed Grade Units -5 -4 Min Max Min Max Input Frequency Ranges (2) F CLKIN CLKIN_FREQ_...
Page 44 - Switching Characteristics for the PS in Variable Phase Mode; Miscellaneous DCM Timing
DC and Switching Characteristics 44 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Phase Shifter (PS) Miscellaneous DCM Timing Table 39: Recommended Operating Conditions for the PS in Variable Phase Mode Symbol Description Speed Grade Units -5 -4 Min Max Min Max Operating Freque...
Page 45 - DNA Port Timing; DNA_PORT Interface Timing
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 45 Product Specification R DNA Port Timing Table 42: DNA_PORT Interface Timing Symbol Description Min Max Units T DNASSU Setup time on SHIFT before the rising edge of CLK 1.0 – ns T DNASH Hold time on SHIFT after the rising...
Page 46 - Suspend Mode Timing; Entering Suspend Mode; Suspend Mode Timing Parameters; Using Suspend Mode in Spar tan-3 Generation FPGAs
DC and Switching Characteristics 46 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Suspend Mode Timing Figure 9: Suspend Mode Timing DS610-3_08_061207 Blocked t SUSPEND_DISABLE t SUSPEND_GWE t SUSPENDHIGH_AWAKE t AWAKE_GWE t AWAKE_GTS t SUSPEND_GTS SUSPEND Input AWAKE Output Fli...
Page 47 - Configuration and JTAG Timing; General Configuration Power-On/Reconfigure Timing; Waveforms for Power-On and the Beginning of Configuration; CCINT; Su; Bank 2; tp; CCLK
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 47 Product Specification R Configuration and JTAG Timing General Configuration Power-On/Reconfigure Timing Figure 10: Waveforms for Power-On and the Beginning of Configuration Table 44: Power-On Timing and the Beginning of ...
Page 48 - Configuration Clock (CCLK) Characteristics; Master Mode CCLK Output Period by; Option Setting; ConfigRate
DC and Switching Characteristics 48 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Configuration Clock (CCLK) Characteristics Table 45: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol Description ConfigRate Setting Temperature Range Minimum Maximum Units T CCL...
Page 49 - Slave Mode CCLK Input Low and High Time
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 49 Product Specification R Table 46: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol Description ConfigRate Setting Temperature Range Minimum Maximum Units F CCLK1 Equivalent CCLK clock frequency by Co...
Page 50 - Master Serial and Slave Serial Mode Timing; Waveforms for Master Serial and Slave Serial Configuration; DIN
DC and Switching Characteristics 50 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Master Serial and Slave Serial Mode Timing Figure 11: Waveforms for Master Serial and Slave Serial Configuration Table 49: Timing for the Master Serial and Slave Serial Configuration Modes Symbol ...
Page 51 - Slave Parallel Mode Timing; Waveforms for Slave Parallel Configuration
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 51 Product Specification R Slave Parallel Mode Timing Figure 12: Waveforms for Slave Parallel Configuration Table 50: Timing for the Slave Parallel Configuration Mode Symbol Description All Speed Grades Units Min Max Setup ...
Page 52 - Serial Peripheral Interface (SPI) Configuration Timing; Waveforms for Serial Peripheral Interface (SPI) Configuration; MOSI
DC and Switching Characteristics 52 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Serial Peripheral Interface (SPI) Configuration Timing Figure 13: Waveforms for Serial Peripheral Interface (SPI) Configuration Table 51: Timing for Serial Peripheral Interface (SPI) Configuration...
Page 54 - Byte Peripheral Interface (BPI) Configuration Timing; Waveforms for Byte-wide Peripheral Interface (BPI) Configuration; HDC
DC and Switching Characteristics 54 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Product Specification R Byte Peripheral Interface (BPI) Configuration Timing Figure 14: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration Table 53: Timing for Byte-wide Peripheral Interface (BPI) Configura...
Page 55 - P C B
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 55 Product Specification R Table 54: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol Description Requirement Units T CE (t ELQV ) Parallel NOR Flash PROM chip-select time ns T OE (t GLQV ) Parallel ...
Page 57 - Table 9
DC and Switching Characteristics DS610-3 (v2.0) July 16, 2007 www.xilinx.com 57 Product Specification R Revision History The following table shows the revision history for this document. Date Version Revision 04/02/07 1.0 Initial Xilinx release. 05/25/07 1.0.1 Minor edits. 06/18/07 1.2 Updated for v...
Page 59 - Packaging; section; UG331: Spartan-3 Generation FPGA User Guide; Pin Types; Pinout Descriptions; Code; JTAG
DS610-4 (v2.0) July 16, 2007 www.xilinx.com 59 Product Specification © 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks are the proper ty of their respective owners. A...
Page 60 - Package Pins by Type; . The table shows the; GND; Types of Pins on Spartan-3A DSP FPGAs; VCCINT; Maximum User I/O by Package; CLK
Pinout Descriptions 60 www.xilinx.com DS610-4 (v2.0) July 16, 2007 Product Specification R Package Pins by Type Each package has three separate voltage supply inputs—VCCINT, VCCAUX, and VCCO—and a common ground return, GND. The numbers of pins dedicated to these functions vary by package, as shown i...
Page 61 - Package Thermal Characteristics; XPower Power Estimator; Spartan-3A DSP Package Thermal Characteristics
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www.xilinx.com 61 Product Specification R Package Thermal Characteristics The power dissipated by an FPGA application has implications on package selection and system design. The power consumed by a Spartan-3A DSP FPGA is reported using either the XPo...
Page 62 - lists all the CS484 package pins. They are sorted; Pinout Table; Spartan-3A DSP CS484 Pinout
Pinout Descriptions 62 www.xilinx.com DS610-4 (v2.0) July 16, 2007 Product Specification R CS484: 484-Ball Chip-Scale Ball Grid Array The 484-ball chip-scale ball grid array, CS484, supports both the XC3SD1800A and XC3SD3400A FPGAs. There are no pinout differences between the two devices. Table 60 l...
Page 68 - Footprint Migration Differences; User I/Os Per Bank for the XC3SD1800A in the CS484 Package; User I/Os Per Bank for the XC3SD3400A in the CS484 Package
Pinout Descriptions 68 www.xilinx.com DS610-4 (v2.0) July 16, 2007 Product Specification R User I/Os by Bank Table 61 and Table 62 indicates how the user-I/O pins are distributed between the four I/O banks on the CS484 package. The AWAKE pin is counted as a Dual-Purpose I/O. Footprint Migration Diff...
Page 69 - Ba
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www.xilinx.com 69 Product Specification R CS484 Footprint Left Half of Package (top view) 156 I/O: Unrestricted, general-purpose user I/O. 41 INPUT: Unrestricted, general-purpose input pin. 52 DUAL: Configuration, AWAKE pins, then possible user I/O. 2...
Page 71 - list of differences and migration advice, see the; Spartan-3A DSP FG676 Pinout for
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www.xilinx.com 71 Product Specification R FG676: 676-Ball Fine-Pitch Ball Grid Array The 676-ball fine-pitch ball grid array, FG676, supports both the XC3SD1800A and the XC3SD3400A FPGAs. There are multiple pinout differences between the two devices. ...
Page 80 - Top
Pinout Descriptions 80 www.xilinx.com DS610-4 (v2.0) July 16, 2007 Product Specification R User I/Os by Bank Table 64 indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 64: User I/Os Per Ban...
Page 81 - The boxes with; FG676 Package Footprint for XC3SD1800A FPGA (top view); Ban
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www.xilinx.com 81 Product Specification R FG676 Footprint - XC3SD1800A FPGA Left Half of Package (top view) 314 I/O: Unrestricted, general-purpose user I/O. 82 INPUT: Unrestricted, general-purpose input pin. 52 DUAL: Configuration, AWAKE pins, then po...
Page 83 - lists all the FG676 package pins for the
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www.xilinx.com 83 Product Specification R XC3SD3400A FPGA Table 65 lists all the FG676 package pins for the XC3SD3400A FPGA. They are sorted by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the ta...
Page 92 - indicates how the available user-I/O pins are; User I/Os Per Bank for the XC3SD3400A in the FG676 Package
Pinout Descriptions 92 www.xilinx.com DS610-4 (v2.0) July 16, 2007 Product Specification R User I/Os by Bank Table 66 indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The AWAKE pin is counted as a Dual-Purpose I/O. Table 66: User I/Os Per Ban...
Page 93 - FG676 Package Footprint for XC3SD3400A FPGA (top view)
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www.xilinx.com 93 Product Specification R FG676 Footprint - XC3SD3400A FPGA Left Half of Package (top view) 314 I/O: Unrestricted, general-purpose user I/O. 34 INPUT: Unrestricted, general-purpose input pin. 52 DUAL: Configuration, AWAKE pins, then po...
Page 95 - . Migration from the XC3S1400A Spartan-3A; FG676 Footprint Migration Differences
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www.xilinx.com 95 Product Specification R Footprint Migration Differences There are multiple migration footprint differences between the XC3SD1800A and the XC3SD3400A in the FG676 package. These migration footprint differences are shown in Table 67 . ...
Page 96 - Migration Recommendations; and take the necessary precautions.
Pinout Descriptions 96 www.xilinx.com DS610-4 (v2.0) July 16, 2007 Product Specification R Migration Recommendations There are multiple pinout differences between the XC3SD1800A and the XC3SD3400A FPGAs in the FG676 package. Please note the differences between the two devices from Table 67 and take ...
