Texas Instruments TSB12LV26 - Manual

Page 4 - IMPORTANT NOTICE

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being r...

Page 5 - Contents; Introduction

iii Contents Section Title Page 1 Introduction 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features 1–1 . . . ...

Page 6 - GPIO Interface

iv 4.7 Configuration ROM Header Register 4–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Bus Identification Register 4–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Bus Options Register 4–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 7 - Switching Characteristics for PHY-Link Interface; Mechanical Information

v 7.5 Switching Characteristics for PHY-Link Interface 7–3 . . . . . . . . . . . . . . . . . 8 Mechanical Information 8–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 8 - List of Illustrations; Figure

vi List of Illustrations Figure Title Page 2–1 Terminal Assignments 2–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 TSB12LV26 Block Diagram 3–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 GPIO2 and GPIO3 Logic Diagram ...

Page 9 - List of Tables

vii List of Tables Table Title Page 2–1 Signals Sorted by Terminal Number 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Signal Names Sorted Alphanumerically to Terminal Number 2–3 . . . . . . . . . . 2–3 Power Supply Terminals 2–3 . . . . . . . . . . . . . . . . . . . . . . ....

Page 11 - Introduction; Description

1–1 1 Introduction 1.1 Description The Texas Instruments TSB12LV26 is a PCI-to-1394 host controller compatible with the latest PCI Local Bus, PCI Bus Power Management Interface, IEEE 1394-1995, and 1394 Open Host Controller Interface Specification. Thechip provides the IEEE 1394 link function, and i...

Page 12 - Related Documents; 394 Open Host Controller Interface Specification 1.0; Ordering Information

1–2 1.3 Related Documents • 1394 Open Host Controller Interface Specification 1.0 • P1394 Standard for a High Performance Serial Bus (IEEE 1394-1995) • P1394a Draft Standard for a High Performance Serial Bus (Supplement) • PC 99 Design Guide • PCI Bus Power Management Interface Specification (Revisi...

Page 13 - Terminal Descriptions; Figure 2–1. Terminal Assignments

2–1 2 Terminal Descriptions This section provides the terminal descriptions for the TSB12LV26. Figure 2–1 shows the signal assigned to eachterminal in the package. Table 2–1 is a listing of signal names arranged in terminal number order, and Table 2–2 liststerminals in alphanumeric order by signal n...

Page 14 - Table 2–1. Signals Sorted by Terminal Number

2–2 Table 2–1. Signals Sorted by Terminal Number NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME 1 GND 26 PCI_AD25 51 PCI_SERR 76 PCI_RST 2 GPIO2 27 PCI_AD24 52 PCI_PAR 77 CYCLEOUT 3 GPIO3 28 PCI_C/BE3 53 PCI_C/BE1 78 CYCLEIN 4 SCL 29 PCI_IDSEL 54 PCI_AD15 79 REG_EN 5 SDA 30 ...

Page 15 - Table 2–3. Power Supply Terminals

2–3 Table 2–2. Signal Names Sorted Alphanumerically to Terminal Number TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. CYCLEIN 78 PCI_AD11 59 PCI_CLK 12 PHY_DATA7 81 CYCLEOUT 77 PCI_AD12 58 PCI_CLKRUN 7 PHY_LINKON 98 GND 1 PCI_AD13 57 PCI_DEVSEL 47 PHY_LPS 99 GND 11 PCI_AD14 ...

Page 16 - Table 2–4. PCI System Terminals

2–4 Table 2–4. PCI System Terminals TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION G_RST 10 I Global power reset. This reset brings all of the TSB12LV26 internal registers to their default states, includingthose registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonf...

Page 17 - Table 2–5. PCI Address and Data Terminals

2–5 Table 2–5. PCI Address and Data Terminals TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION PCI_AD31PCI_AD30PCI_AD29PCI_AD28PCI_AD27PCI_AD26PCI_AD25PCI_AD24PCI_AD23PCI_AD22PCI_AD21PCI_AD20PCI_AD19PCI_AD18PCI_AD17PCI_AD16PCI_AD15PCI_AD14PCI_AD13PCI_AD12PCI_AD11PCI_AD10PCI_AD9PCI_AD8PCI_AD7PCI_AD6...

Page 18 - Table 2–6. PCI Interface Control Terminals

2–6 Table 2–6. PCI Interface Control Terminals TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION PCI_C/BE0PCI_C/BE1PCI_C/BE2PCI_C/BE3 65534128 I/O PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCIterminals. During the address phase of a bus cycle ...

Page 19 - Table 2–8. Miscellaneous Terminals

2–7 Table 2–7. IEEE 1394 PHY/Link Terminals TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION PHY_CTL1PHY_CTL0 9293 I/O PHY-link interface control. These bidirectional signals control passage of information between the two devices.The TSB12LV26 can only drive these terminals after the PHY has grante...

Page 21 - TSB12LV26 Controller Programming Model; type column,and a detailed field description. Table 3–1; Table 3–1. Bit Field Access Tag Descriptions

3–1 3 TSB12LV26 Controller Programming Model This section describes the internal registers used to program the TSB12LV26. All registers are detailed in the sameformat: a brief description for each register, followed by the register offset and a bit table describing the reset statefor each register. ...

Page 23 - PCI Configuration Registers; PCI Local Bus; Table 3–2. PCI Configuration Register Map; Vendor ID Register; Vendor ID

3–3 3.1 PCI Configuration Registers The TSB12LV26 is a single-function PCI device. The configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3–2 illustrates the PCI configuration header that includes both thepredefined portion of the configuration space a...

Page 24 - Device ID Register; Device ID; Command Register

3–4 3.3 Device ID Register The device ID register contains a value assigned to the TSB12LV26 by Texas Instruments. The device identificationfor the TSB12LV26 is 8020h. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Device ID Type R R R R R R R R R R R R R R R R Default 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 ...

Page 25 - Status Register; Status

3–5 3.5 Status Register The status register provides status over the TSB12LV26 interface to the PCI bus. All bit functions adhere to thedefinitions in the PCI Local Bus Specification. See Table 3–4 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name St...

Page 26 - Class Code and Revision ID Register; Class code and revision ID; Latency Timer and Class Cache Line Size Register; Latency timer and class cache line size

3–6 3.6 Class Code and Revision ID Register The class code and revision ID register categorizes the TSB12LV26 as a serial bus controller (0Ch), controlling anIEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in theleast significant byte. See Ta...

Page 27 - Header Type and BIST Register; Header type and BIST; OHCI Base Address Register

3–7 3.8 Header Type and BIST Register The header type and BIST register indicates the TSB12LV26 PCI header type, and indicates no built-in self test. SeeTable 3–7 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Header type and BIST Type R R R R R R...

Page 28 - TI Extension Base Address Register; TI extension base address; Subsystem Identification Register; Subsystem identification

3–8 3.10 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TIextension registers. See the OHCI Base Address Register, Section 3.9, for bit field details. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name T...

Page 29 - Power Management Capabilities Pointer Register; Power management capabilities pointer; Interrupt Line and Pin Register

3–9 3.12 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where thePCI power management register block resides. The TSB12LV26 configuration header double-words at offsets 44hand 48h provide the powe...

Page 30 - OHCI Control Register; The OHCI control register is defined by the; OHCI control

3–10 3.14 MIN_GNT and MAX_LAT Register The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of bits 15–8 of thelatency timer and class cache line size register (offset 0Ch, see Section 3.7). If a serial ROM is detected, then thecontents of this register are loade...

Page 31 - Capability ID and Next Item Pointer Register; Capability ID and next item pointer

3–11 3.16 Capability ID and Next Item Pointer Register The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to thenext capability item. See Table 3–13 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 32 - Power Management Capabilities Register; Power management capabilities

3–12 3.17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the TSB12LV26 related to PCI powermanagement. See Table 3–14 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power management ...

Page 33 - Power Management Control and Status Register; Power management control and status; Power Management Extension Register; Power management extension

3–13 3.18 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power managementfunction. This register is not affected by the internally generated reset caused by the transition from the D3 hot to D0 state. See Tab...

Page 34 - Miscellaneous Configuration Register; Miscellaneous configuration

3–14 3.20 Miscellaneous Configuration Register The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3–17 for acomplete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Miscellaneous configuration Type R R R...

Page 35 - Link Enhancement Control Register; Link enhancement control

3–15 3.21 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serialROM, if present. After these bits are set, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the hostcontroller control r...

Page 36 - Subsystem Access Register; Subsystem access

3–16 Table 3–18. Link Enhancement Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 1 enab_accel R/W Enable acceleration enhancements. OHCI-Lynx compatible. When set to 1, this bit notifies the PHYthat the link supports the 1394a acceleration enhancements, i.e., ack-accelerate...

Page 37 - GPIO Control Register; GPIO control; FCh; Table 3–20. GPIO Control Register Description

3–17 3.23 GPIO Control Register The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3–20 for acomplete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name GPIO control Type R/W R R/W R/W R R R RWU R/W R R/W R/W...

Page 39 - OHCI Registers; The OHCI registers defined by the; Table 4–1. OHCI Register Map

4–1 4 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2-Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (seeSection 3.9). These registers are the primary interface...

Page 42 - OHCI Version Register; OHCI version

4–4 4.1 OHCI Version Register This register indicates the OHCI version support, and whether or not the serial ROM is present. See Table 4–2 fora complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name OHCI version Type R R R R R R R R R R R R R R R R D...

Page 43 - GUID ROM Register; GUID ROM

4–5 4.2 GUID ROM Register The GUID ROM register is used to access the serial ROM, and is only applicable if bit 24 (GUID_ROM) in the OHCIversion register (OHCI offset 00h, see Section 4.1) is set. See Table 4–3 for a complete description of the registercontents. Bit 31 30 29 28 27 26 25 24 23 22 21 ...

Page 44 - Asynchronous Transmit Retries Register; Asynchronous transmit retries; CSR Data Register; CSR data; XXXX XXXXh

4–6 4.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the TSB12LV26 attempts a retry forasynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4–4 fora complete description of the register...

Page 45 - CSR Compare Register; CSR compare; CSR Control Register; CSR control

4–7 4.5 CSR Compare Register The CSR compare register is used to access the bus management CSR registers from the host throughcompare-swap operations. This register contains the data to be compared with the existing value of the CSRresource. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name C...

Page 46 - Configuration ROM Header Register; Configuration ROM header; Bus Identification Register

4–8 4.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offsetFFFF F000 0400h. See Table 4–6 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Confi...

Page 47 - Bus Options Register; Bus options

4–9 4.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4–7 for a completedescription of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Bus options Type R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W...

Page 48 - GUID High Register; GUID high; GUID Low Register

4–10 4.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the thirdquadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializesto 0s on a hardware reset, which is an ille...

Page 49 - Configuration ROM Mapping Register; Configuration ROM mapping; Posted Write Address Low Register; Posted write address low

4–11 4.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the startaddress of 1394 configuration ROM for this node. See Table 4–8 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23...

Page 50 - Posted Write Address High Register; Posted write address high; Table 4–9. Posted Write Address High Register Description; Vendor ID Register

4–12 4.14 Posted Write Address High Register The posted write address high register is used to communicate error information if a write request is posted and anerror occurs while writing the posted data packet. See Table 4–9 for a complete description of the register contents. Bit 31 30 29 28 27 26 ...

Page 51 - Host Controller Control Register; Host controller control; set register; Table 4–10. Host Controller Control Register Description

4–13 4.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the TSB12LV26. See Table 4–10 fora complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Host controller control Type R RSC ...

Page 53 - Isochronous Receive Channel Mask High Register; Isochronous receive channel mask high

4–15 4.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register is used to enable packet receives from the upper 32isochronous data channels. A read from either the set register or clear register returns the content of the isochronousreceive chan...

Page 54 - Isochronous Receive Channel Mask Low Register; Isochronous receive channel mask low

4–16 Table 4–12. Isochronous Receive Channel Mask High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 6 isoChannel38 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 38. 5 isoChannel37 RSC When this bit is set, the TSB12LV26 is enabled to receiv...

Page 55 - Interrupt Event Register; 394 Open Host Controller Interface Specification. See; Interrupt event; Table 4–14. Interrupt Event Register Description

4–17 4.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various TSB12LV26 interrupt sources. The interrupt bitsare set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the setregister. The only mechan...

Page 56 - Table 4–14. Interrupt Event Register Description (Continued)

4–18 Table 4–14. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 17 busReset RSCU Indicates that the PHY chip has entered bus reset mode. 16 selfIDcomplete RSCU A selfID packet stream has been received. It is generated at the end of the bus initialization process.Thi...

Page 57 - Interrupt Mask Register; Interrupt mask; Table 4–15. Interrupt Mask Register Description

4–19 4.22 Interrupt Mask Register The interrupt mask set/clear register is used to enable the various TSB12LV26 interrupt sources. Reads from eitherthe set register or the clear register always return the contents of the interrupt mask register. In all cases exceptmasterIntEnable (bit 31) and Vendor...

Page 58 - Isochronous Transmit Interrupt Event Register; Isochronous transmit interrupt event

4–20 4.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmitcontexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* commandcompletes and its int...

Page 59 - Isochronous Transmit Interrupt Mask Register; Isochronous transmit interrupt mask

4–21 4.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrupt source on aper-channel basis. Reads from either the set register or the clear register always return the contents of theisochronous transmit inter...

Page 60 - Isochronous Receive Interrupt Event Register; Isochronous receive interrupt event; Isochronous Receive Interrupt Mask Register; Isochronous receive interrupt mask

4–22 4.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receivecontexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completesand its interrupt bi...

Page 61 - Fairness Control Register; Fairness control; DCh; Table 4–18. Fairness Control Register Description

4–23 4.27 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmitmultiple asynchronous requests during a fairness interval. See Table 4–18 for a complete description of the registercontents. Bit 31 30 29 28 27 26 25 24...

Page 62 - Link Control Register; Link control; Table 4–19. Link Control Register Description

4–24 4.28 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portionsof the TSB12LV26. It contains controls for the receiver and cycle timer. See Table 4–19 for a complete descriptionof the register contents. Bit 31 3...

Page 63 - Node Identification Register; Node identification

4–25 4.29 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indicatesthe valid node number status. The 16-bit combination of the busNumber field (bits 15–6) and the NodeNumber field(bits 5–0) is referred to as the ...

Page 64 - PHY Layer Control Register; PHY layer control; ECh; Table 4–21. PHY Control Register Description

4–26 4.30 PHY Layer Control Register The PHY layer control register is used to read or write a PHY register. See Table 4–21 for a complete description ofthe register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PHY layer control Type RU R R R RU RU RU RU RU RU RU RU RU RU RU RU...

Page 65 - Isochronous Cycle Timer Register; Isochronous cycle timer; Table 4–22. Isochronous Cycle Timer Register Description

4–27 4.31 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the TSB12LV26 is cyclemaster, this register is transmitted with the cycle start message. When the TSB12LV26 is not cycle master, thisregister is loaded with the data fi...

Page 66 - Asynchronous Request Filter High Register; Asynchronous request filter high

4–28 4.32 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register is used to enable asynchronous receive requests on aper-node basis, and handles the upper node IDs. When a packet is destined for either the physical request contextor the ARRQ context, the so...

Page 68 - Asynchronous Request Filter Low Register; Asynchronous request filter low; Table 4–24. Asynchronous Request Filter Low Register Description

4–30 4.33 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register is used to enable asynchronous receive requests on a per-nodebasis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to theasynchronous ...

Page 69 - Physical Request Filter High Register; Physical request filter high; Table 4–25. Physical Request Filter High Register Description

4–31 4.34 Physical Request Filter High Register The physical request filter high set/clear register is used to enable physical receive requests on a per-node basis andhandles the upper node IDs. When a packet is destined for the physical request context and the node ID has beencompared against the A...

Page 71 - Physical Request Filter Low Register; Physical request filter low; Table 4–26. Physical Request Filter Low Register Description

4–33 4.35 Physical Request Filter Low Register The physical request filter low set/clear register is used to enable physical receive requests on a per-node basis andhandles the lower node IDs. When a packet is destined for the physical request context and the node ID has beencompared against the asy...

Page 72 - Physical upper bound

4–34 4.36 Physical Upper Bound Register (Optional Register) The physical upper bound register is an optional register and is not implemented. It returns all 0s when read. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Physical upper bound Type R R R R R R R R R R R R R R R R Default 0 0 0 ...

Page 73 - Asynchronous Context Control Register; Asynchronous context control

4–35 4.37 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. SeeTable 4–27 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Asynchronous con...

Page 74 - Asynchronous Context Command Pointer Register; Asynchronous context command pointer

4–36 4.38 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor blockthat the TSB12LV26 accesses when software enables the context by setting the asynchronous context controlregister (see Section 4.37...

Page 75 - Isochronous Transmit Context Control Register; Isochronous transmit context control

4–37 4.39 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronoustransmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, … , 7). See ...

Page 76 - Isochronous Transmit Context Command Pointer Register; Isochronous transmit context command pointer; Isochronous Receive Context Control Register; Isochronous receive context control

4–38 4.40 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptorblock that the TSB12LV26 accesses when software enables an isochronous transmit context by setting theisochronous transmi...

Page 78 - Isochronous Receive Context Command Pointer Register; Isochronous receive context command pointer

4–40 4.42 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptorblock that the TSB12LV26 accesses when software enables an isochronous receive context by setting theisochronous receive co...

Page 79 - Isochronous Receive Context Match Register; Isochronous receive context match

4–41 4.43 Isochronous Receive Context Match Register The isochronous receive context match register is used to start an isochronous receive context running on a specifiedcycle number, to filter incoming isochronous packets based on tag values, and to wait for packets with a specifiedsync value. The ...

Page 81 - GPIO Interface; Figure 5–1. GPIO2 and GPIO3 Logic Diagram

5–1 5 GPIO Interface The general-purpose input/output (GPIO) interface consists of two GPIO ports. GPIO2 and GPIO3 power up asgeneral-purpose inputs and are programmable via the GPIO control register. Figure 5–1 shows the logic diagram forGPIO2 and GPIO3 implementation. D Q GPIO Read Data GPIO Write...

Page 83 - Serial ROM Interface; Table 6–1. Registers and Bits Loadable through Serial ROM

6–1 6 Serial ROM Interface The TSB12LV26 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCIconfiguration registers through a serial ROM. The TSB12LV26 communicates with the serial ROM via the 2-wire serialinterface. After power-up the serial interface init...

Page 84 - Table 6–2. Serial ROM Map

6–2 Table 6–2. Serial ROM Map BYTE ADDRESS BYTE DESCRIPTION 00 PCI maximum latency (0h) PCI_minimum grant (0h) 01 PCI vendor ID 02 PCI vendor ID (msbyte) 03 PCI subsystem ID (lsbyte) 04 PCI subsystem ID 05 [7] Link_enhancement-Control.enab_unfair [6] HCControl. ProgramPhy Enable [5] RSVD [4] RSVD [3...

Page 85 - Electrical Characteristics; Absolute Maximum Ratings Over Operating Temperature Ranges

7–1 7 Electrical Characteristics 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges † Supply voltage range, V CC –0.5 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply voltage range, V CCP –0.5 V to 5.5 V ....

Page 86 - Recommended Operating Conditions

7–2 7.2 Recommended Operating Conditions OPERATION MIN NOM MAX UNIT VCC Core voltage Commercial 3.3 V 3 3.3 3.6 V VCCP PCI I/O clamping voltage Commercial 3.3 V 3 3.3 3.6 V VCCP PCI I/O clamping voltage Commercial 5 V 4.5 5 5.5 V † PCI 3.3 V 0.475 VCCP VCCP VIH† High level input voltage PCI 5 V 2 VC...

Page 89 - Mechanical Information; PLASTIC QUAD FLATPACK

8–1 8 Mechanical Information The TSB12LV26 is packaged in a 100-terminal PZ package. The following shows the mechanical dimensions for thePZ package. PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 4040149 /B 11/96 50 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 51 25 75 1 12,00 TYP 0,17 76 100 SQ SQ ...

Texas Instruments TSB12LV26 - Manual

Table of Contents:

Summary

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