Texas Instruments TNETX3270 - Manual

Texas Instruments TNETX3270

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Table of Contents:

  • Page 2 – SWITCH; description; architecture, the TNETX3270 design
  • Page 5 – ThunderSWITCH 24/3 ETHERNET SWITCH; Figure 1. TNETX3270 Interface Block Diagram; PRODUCT PREVIEW
  • Page 6 – Terminal Functions
  • Page 9 – SDRAM interface
  • Page 10 – host DIO interface
  • Page 11 – serial MII management PHY interface
  • Page 12 – miscellaneous
  • Page 13 – DIO register groups; Table 1. Internal Register and Statistics Memory Map
  • Page 14 – Table 2. Detailed DIO Register Map
  • Page 18 – interface description; DIO interface; state of DIO signals during hardware reset
  • Page 19 – network management port; IEEE Std 802.1Q VLAN headers on the NM port; 33 Mbit/s). This can be sustained between the DIO port and the; interrupt processing; There are two interrupts available on the NM port.
  • Page 20 – frame format on the NM port
  • Page 21 – Figure 2. NM Frame Format; When; in NMRxcontrol
  • Page 22 – MII serial management interface (PHY management)
  • Page 23 – receive filtering of frames
  • Page 24 – receive versus transmit priority; Source-port pretag on transmission; source-port pretag on transmission
  • Page 26 – The port assignments for these tag bits are shown in Table 6.; Table 6. Received Pretag Port Assignments
  • Page 27 – EEPROM interface; EEPROM downloads can be initiated in one of two ways:; Figure 5. EEPROM Interface Connections; A current-source pullup device is provided on this pin.
  • Page 28 – interaction of EEPROM load with the SIO register; The SIO register is not loaded during the EEPROM download.; summary of EEPROM load outcomes
  • Page 29 – JTAG interface; The following instructions are supported:; Table 8. JTAG Instruction Opcodes
  • Page 30 – Table 10. LED Status Bit Definitions and Shift Order; lamp test; hardware configurations; ports). The remaining control and status signals also are
  • Page 33 – Figure 7. Connecting to TNETE2008 PHY
  • Page 35 – The behavior of these terminals is summarized in Tables 13 and 14.; Table 13. Speed Configuration – MxxFORCE10; Table 14. Duplex Configuration – MxxFORCEHD; The MACs then operate as indicated by the Portxstatus register.
  • Page 37 – Table 15. TNETX3270 Terminal Interface to SDRAMs
  • Page 38 – SDRAM-type and quantity indication; s of inactivity after power has; refresh
  • Page 39 – frame routing; VLAN support; Figure 8. VLAN Overview
  • Page 40 – IEEE Std 802.1Q headers – reception; unknown VLAN; IEEE Std 802.1Q headers – transmission
  • Page 41 – spanning-tree support
  • Page 44 – port mirroring
  • Page 45 – port trunking/load sharing; Bits 31–16 are XORed to produce the middle of the map index.; flow control
  • Page 46 – collision-based flow control; Padding as required/desired
  • Page 47 – pause frame reception; not used by IALE for learning source addresses. They appear in the; pause frame transmission
  • Page 48 – internal wrap test; This causes the following:
  • Page 49 – Figure 10. Internal Wrap Example; The switch is configured in the same manner as internal wrap.; Figure 11. Duplex Wrap Example
  • Page 51 – Supply voltage range: V; JC; Operating case temperature range, T; stg; recommended operating conditions
  • Page 52 – PARAMETER MEASUREMENT INFORMATION; in recommended operating conditions.
  • Page 53 – timing requirements (see Notes 3 through 6 and Figure 13)
  • Page 54 – timing requirements (see Note 7 and Figure 14)
  • Page 56 – The SDRAM interface observes two types of timing:; Figure 16. SDRAM Command to Command
  • Page 57 – SDRAM subcycle
  • Page 60 – serial MII management interface; Figure 20. Serial MII Management Read/Write Cycle
  • Page 62 – LED interface
  • Page 63 – power-up OSCIN and RESET; s to reset the device.
  • Page 64 – MECHANICAL DATA
  • Page 65 – IMPORTANT NOTICE; Copyright
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TNETX3270

ThunderSWITCH

24/3 ETHERNET

SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

1

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

D

Port Configurations:
Twenty-Four 10-Mbit/s Ports
– Ports Arranged in Three Groups of Eight

Ports in a Multiplexed Interface

– Direct Multiplexer Interface to

TNETE2008

– Full and Half Duplex
– Half-Duplex Collision-Based Flow

Control

– Full-Duplex IEEE Std 802.3x Flow Control
– Interoperable Support for IEEE

Std 802.1Q VLAN

– Speed, Duplex, and Pause

Autonegotiation With Physical Layer
(PHY)

Three 10-/100-Mbit/s Ports
– Direct Interface to TNETE2101
– Full and Half Duplex
– Half-Duplex Collision-Based Flow

Control

– Full-Duplex IEEE Std 802.3x Flow Control
– Interoperable Support for IEEE

Std 802.1Q VLAN

– Pretagging Support

D

Port Trunking and Load Sharing

D

LED Indication of Port Status

D

SDRAM Interface
– Direct Interface to 8-Bit/Word and

16-Bit/Word, 16-Mbit, and 64-Mbit
SDRAMs

– 32-Bit-Wide Data Bus

– Up to 32 Mbytes Supported
– 83.33-MHz SDRAM Clock
– 12-ns (–12) SDRAMs Required

D

Remote Monitoring (RMON) Support –
Groups 1, 2, 3, and 9

D

Direct I/O (DIO) Management Interface
– Eight Bits Wide
– CPU Access to Statistics, Registers, and

Management Information Bases (MIBs)

– Internal Network Management Port
– Forwards Spanning-Tree Packets to CPU
– Serial Media-Independent Interface (MII)

for PHY Control

D

EEPROM Interface for Autoconfiguration
(No CPU Required for Nonmanaged Switch)

D

Internal Address-Lookup/Frame-Routing
Engine
– Interoperable Support for IEEE

Std 802.1Q VLAN

– Supports IEEE Std 802.1D Spanning Tree
– Thirty-Two Assignable Virtual LANs

(VLANs)

– Multiple Forwarding Modes
– 2K Total Addresses Supported
– Port Mirroring

D

IEEE Std 1149.1 (JTAG) Interface (3.3-V
Signals)

D

2.5-V Process With 3.3-V-Drive I/O

D

Packaged in 240-Terminal Plastic Quad
Flatpack

Eight Ports
(16–23)
10 Mbit/s

Controller (MAC)
Controller (MAC)

Controller (MAC)

TAP

(JTAG)

Address

Compare

Statistics

Storage

MIB

Three Ports
(24–26)
10/100 Mbit/s

Network

Statistics

Logic

Data Path

LED

Interface

CPU

Interface

SDRAM

Controller

Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)

MUX

Controller (MAC)

Controller (MAC)

MII

MII

MII

Eight Ports
(08–15)
10 Mbit/s

Eight Ports
(00–07)
10 Mbit/s

Queue

Manager

EEPROM

Interface

Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)

MUX

Controller (MAC)
Controller (MAC)

MUX

Copyright

1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI and ThunderSWITCH are trademarks of Texas Instruments Incorporated.
Ethernet is a trademark of Xerox Corporation.
Secure Fast Switching is a trademark of Cabletron Systems, Inc.
Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast
Switching

.

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Summary

Page 2 - SWITCH; description; architecture, the TNETX3270 design

TNETX3270ThunderSWITCH  24/3 ETHERNET  SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description The TNETX3270 provides highly integrated switching solutions that allow network designers to low...

Page 5 - ThunderSWITCH 24/3 ETHERNET SWITCH; Figure 1. TNETX3270 Interface Block Diagram; PRODUCT PREVIEW

TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999  POST OFFICE BOX 655303 DALLAS, TEXAS 75265 • 5 DA12–DA0 MRESET ECLK EDIO DD31–DD0 DCLK DRASDCAS DW LEDDATA LEDCLK SDATA7–SDATA0 SAD1–SAD0 SRNW SCS SRDY DRA...

Page 6 - Terminal Functions

TNETX3270ThunderSWITCH  24/3 ETHERNET  SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions 10-Mbit/s MAC multiplexed interface (ports 00–23) is multiplexed into three groups (TH0, ...

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