Texas Instruments TMS320F28015 - Manual

Texas Instruments TMS320F28015

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Table of Contents:

  • Page 2 – Introduction
  • Page 4 – Migrating From F280x Devices to C280x Devices; Migration Issues; Revision History
  • Page 9 – Digital Signal Processors; Check for; Features
  • Page 10 – Getting Started; SPRAAM0
  • Page 11 – Throughout
  • Page 14 – Pin Assignments; ball grid array (BGA) terminal assignments are shown in
  • Page 18 – Bottom View
  • Page 19 – Signal Descriptions
  • Page 24 – NOTE
  • Page 25 – Functional Overview
  • Page 26 – Memory Maps
  • Page 31 – Table 3-1. Addresses of Flash Sectors in F2809; Table 3-2. Addresses of Flash Sectors in F2808
  • Page 32 – shows how to handle these memory locations.; Table 3-5. Impact of Using the Code Security Module
  • Page 34 – Brief Descriptions; Peripheral Bus
  • Page 35 – ROM
  • Page 36 – Boot ROM; MODE
  • Page 40 – Register Map
  • Page 43 – Figure 3-7. External and PIE Interrupt Sources
  • Page 44 – Figure 3-8. Multiplexing of Interrupts Using the PIE Block
  • Page 45 – Table 3-13. PIE Configuration and Control Registers; External Interrupts
  • Page 46 – System Control
  • Page 47 – OSC and PLL Block; shows the OSC and PLL block on the 280x.
  • Page 48 – The three possible input-clock configurations are shown in; Figure 3-13. Using the Internal Oscillator; Fundamental mode, parallel resonant
  • Page 49 – The PLL-based clock module provides two modes of operation:; Table 3-17. Possible PLL Configuration Modes; SYSCLKOUT
  • Page 50 – Loss of Input Clock
  • Page 51 – Watchdog Block; shows the various functional blocks within the watchdog module.
  • Page 52 – Low-Power Modes Block; The low-power modes on the 280x are similar to the 240x devices.; The various low-power modes operate as follows:
  • Page 53 – Digital I/O and shared pin functions
  • Page 54 – NAME
  • Page 55 – The 280x device contains up to six enhanced PWM Modules (ePWM).; Figure 4-3. Multiple PWM Modules in a 280x System; shows the complete ePWM register set per module.
  • Page 56 – Table 4-2. ePWM Control and Status Registers
  • Page 59 – Figure 4-5. eCAP Functional Block Diagram
  • Page 60 – Table 4-3. eCAP Control and Status Registers; SIZE
  • Page 61 – Data bus; Figure 4-6. eQEP Functional Block Diagram
  • Page 62 – Table 4-4. eQEP Control and Status Registers
  • Page 63 – The digital value of the input analog voltage is derived by:; ePWM start of conversion
  • Page 64 – Figure 4-7. Block Diagram of the ADC Module; shows the ADC pin connections for the 280x; signals is as follows:
  • Page 65 – shows the ADC pin-biasing for internal reference and; Figure 4-8. ADC Pin Connections With Internal Reference
  • Page 66 – Figure 4-9. ADC Pin Connections With External Reference; ADC Connections if the ADC Is Not Used
  • Page 67 – ADC Registers
  • Page 69 – Figure 4-10. eCAN Block Diagram and Interface Circuit
  • Page 75 – shows the SCI module block diagram.
  • Page 76 – NOTE: All four pins can be used as GPIO, if the SPI module is not used.; Two operational modes: master and slave; Delayed transmit control
  • Page 77 – through
  • Page 79 – is a block diagram of the SPI in slave mode.
  • Page 81 – Figure 4-15. I2C Peripheral Module Interfaces; The registers in
  • Page 83 – shows the GPIO
  • Page 85 – Figure 4-17. Qualification Using Sampling Window
  • Page 86 – Device and Development Support Tool Nomenclature
  • Page 88 – Documentation Support; information on types of peripherals.; LITERATURE; The following documents are available on the TI website (; Peripheral Guides
  • Page 89 – describes
  • Page 91 – Software; BSDL Models
  • Page 93 – Absolute Maximum Ratings
  • Page 94 – over recommended operating conditions (unless otherwise noted)
  • Page 95 – Current Consumption
  • Page 99 – Reducing Current Consumption; SPI modules; Table 6-5. Typical Current Consumption by Various; PERIPHERAL; CURRENT; The baseline I; current (current when the core is executing a dummy loop with no; current for a given application,
  • Page 100 – Current Consumption Graphs
  • Page 101 – Current Vs SYSCLKOUT; rr; IDD; Device Power Vs SYSCLKOUT; ic; TOTAL POW ER
  • Page 102 – Emulator Connection Without Signal Buffering for the DSP; shows
  • Page 103 – Transmission Line; Tester Pin Electronics; Data Sheet Timing Reference Point; Timing Parameter Symbology; Lowercase subscripts and their; General Notes on Timing Parameters
  • Page 104 – Device Clock Table; and
  • Page 105 – Clock Requirements and Characteristics; Timing Requirements - PLL Enabled; The possible configuration modes are shown in
  • Page 106 – Power Sequencing; Power Management and Supervisory Circuit Solutions; Table 6-12. Power Management and Supervisory Circuit Solutions; SUPPLIER
  • Page 109 – Figure 6-10. Example of Effect of Writing Into PLLCR Register; PARAMETER
  • Page 111 – Sampling Window Width for Input Signals; Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD
  • Page 112 – Low-Power Mode Wakeup Timing; shows the timing requirements,; Table 6-16. IDLE Mode Timing Requirements
  • Page 114 – Table 6-20. HALT Mode Timing Requirements; Table 6-21. HALT Mode Switching Characteristics
  • Page 115 – Enhanced Control Peripherals; shows the PWM timing requirements and; Table 6-23. ePWM Switching Characteristics
  • Page 116 – Table 6-27. eCAP Switching Characteristics; shows the eQEP timing requirement and; Table 6-29. eQEP Switching Characteristics
  • Page 117 – Table 6-31. External Interrupt Timing Requirements
  • Page 118 – I2C Electrical Specification and Timing; TEST CONDITIONS; lists the timing (clock
  • Page 123 – MIN
  • Page 127 – Figure 6-25. ADC Analog Input Impedance Model
  • Page 128 – Table 6-41. Sequential Sampling Mode Timing; SAMPLE n
  • Page 129 – Figure 6-27. Simultaneous Sampling Mode Timing
  • Page 130 – Detailed Descriptions; Integral Nonlinearity
  • Page 131 – Table 6-43. Flash Endurance for A and S Temperature Material; Equation to compute the OTP wait-state in
  • Page 132 – Equations to compute the page wait-state and random wait-state in; Wait-States at Different Frequencies
  • Page 133 – The V; The PART-ID register value is different for Flash and ROM parts.
  • Page 134 – Changed MIN N; LOCATION
  • Page 137 – PACKAGE OPTION ADDENDUM; PACKAGING INFORMATION
  • Page 141 – MECHANICAL DATA; PLASTIC BALL GRID ARRAY; Seating Plane
  • Page 143 – PLASTIC QUAD FLATPACK; Gage Plane
  • Page 144 – IMPORTANT NOTICE; Products
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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

Digital Signal Processors

Data Manual

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Literature Number: SPRS230L

October 2003 – Revised December 2009

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Summary

Page 2 - Introduction

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Contents 1 F280x, F2801x, C280x DSPs .............................................................................................

Page 4 - Migrating From F280x Devices to C280x Devices; Migration Issues; Revision History

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6.13 ROM Timing (C280x only) .............................................................................................. 132...

Page 9 - Digital Signal Processors; Check for; Features

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Digital Signal Processors Check for Samples: TMS320F2809 , TMS320F2808 , TMS320F2806 , TMS320F2802 , TMS320F2801 , TMS320C280...

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