Texas Instruments TMS320C67X/C67X+ DSP - Manual

Contents vi SPRU733 Contents 3 Instruction Set 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the assembly language instructions of the TMS320C67x DSP. Also described are parallel operations, condition...

Contents ix Contents SPRU733 SPINT (Convert Single-Precision Floating-Point Value to Integer) 3-228 . . . . . . . . . . . . . . . SPTRUNC (Convert Single-Precision Floating-Point Value to Integer With Truncation) 3-230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Contents x SPRU733 Contents 4.2.11 MPYI Instruction 4-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.12 MPYID Instruction 4-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.13 MP...

Contents xi Contents SPRU733 A Instruction Compatibility A-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lists the instructions that are common to the C62x, C64x, and C67x DSPs. B Mapping Between Instruction and Functional Unit B-...

Figures xii SPRU733 Figures Figures 1 − 1 TMS320C67x DSP Block Diagram 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 − 1 TMS320C67x CPU Data Paths 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Tables xiv SPRU733 Tables Tables 1 − 1 Typical Applications for the TMS320 DSPs 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 − 1 40-Bit/64-Bit Register Pairs 2-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Examples xvii Examples SPRU733 Examples 3 − 1 Fully Serial p-Bit Pattern in a Fetch Packet 3-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 − 2 Fully Parallel p-Bit Pattern in a Fetch Packet 3-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

1-1 Introduction SPRU733 a Introduction The TMS320C6000 ™ digital signal processor (DSP) platform is part of the TMS320 ™ DSP family. The TMS320C62x ™ DSP generation and the TMS320C64x ™ DSP generation comprise fixed-point devices in the C6000 ™ DSP platform, and the TMS320C67x ™ DSP generation comp...

TMS320C6000 DSP Family Overview 1-3 Introduction SPRU733 Table 1 − 1. Typical Applications for the TMS320 DSPs Automotive Consumer Control Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Global positioning Navigation Vibration analysis Voice commands Digital r...

TMS320C67x DSP Features and Options 1-5 Introduction SPRU733 40-bit arithmetic options add extra precision for vocoders and othercomputationally intensive applications Saturation and normalization provide support for key arithmeticoperations Field manipulation and instruction extract, set, clear, an...

TMS320C67x DSP Features and Options Introduction 1-6 SPRU733 The VelociTI architecture of the C6000 platform of devices make them the firstoff-the-shelf DSPs to use advanced VLIW to achieve high performancethrough increased instruction-level parallelism. A traditional VLIW architectureconsists of mu...

TMS320C67x DSP Architecture 1-7 Introduction SPRU733 1.4 TMS320C67x DSP Architecture Figure 1 − 1 is the block diagram for the C67x DSP. The C6000 devices come with program memory, which, on some devices, can be used as a programcache. The devices also have varying sizes of data memory. Peripherals ...

TMS320C67x DSP Architecture 1-9 Introduction SPRU733 DMA Controller (C6701 DSP only) transfers data between address rangesin the memory map without intervention by the CPU. The DMA controllerhas four programmable channels and a fifth auxiliary channel. EDMA Controller performs the same functions as ...

2-1 CPU Data Paths and Control SPRU733 CPU Data Paths and Control This chapter focuses on the CPU, providing information about the data paths andcontrol registers. The two register files and the data cross paths are described. Topic Page 2.1 Introduction 2-2 . . . . . . . . . . . . . . . . . . . . ....

Introduction CPU Data Paths and Control 2-2 SPRU733 2.1 Introduction The components of the data path for the TMS320C67x CPU are shown inFigure 2 − 1. These components consist of: Two general-purpose register files (A and B) Eight functional units (.L1, .L2, .S1, .S2, .M1, .M2, .D1, and .D2) Two load...

General-Purpose Register Files 2-3 CPU Data Paths and Control SPRU733 Figure 2 − 1. TMS320C67x CPU Data Paths 8 8 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Á...

General-Purpose Register Files CPU Data Paths and Control 2-4 SPRU733 Table 2 − 1. 40-Bit/64-Bit Register Pairs Register Files A B Devices A1:A0 B1:B0 C67x DSP A3:A2 B3:B2 A5:A4 B5:B4 A7:A6 B7:B6 A9:A8 B9:B8 A11:A10 B11:B10 A13:A12 B13:B12 A15:A14 B15:B14 A17:A16 B17:B16 C67x+ DSP only A19:A18 B19:B...

Functional Units 2-5 CPU Data Paths and Control SPRU733 2.3 Functional Units The eight functional units in the C6000 data paths can be divided into twogroups of four; each functional unit in one data path is almost identical to thecorresponding unit in the other data path. The functional units are d...

Register File Cross Paths CPU Data Paths and Control 2-6 SPRU733 2.4 Register File Cross Paths Each functional unit reads directly from and writes directly to the register filewithin its own data path. That is, the .L1, .S1, .D1, and .M1 units write to registerfile A and the .L2, .S2, .D2, and .M2 u...

Data Address Paths 2-7 CPU Data Paths and Control SPRU733 2.6 Data Address Paths The data address paths (DA1 and DA2) are each connected to the .D units inboth data paths. This allows data addresses generated by any one path toaccess data to or from any register. The DA1 and DA2 resources and their ...

Control Register File CPU Data Paths and Control 2-8 SPRU733 2.7.1 Register Addresses for Accessing the Control Registers Table 2 − 4 lists the register addresses for accessing the control register file. One unit (.S2) can read from and write to the control register file. Each controlregister is acc...

Control Register File 2-9 CPU Data Paths and Control SPRU733 2.7.2 Pipeline/Timing of Control Register Accesses All MVC instructions are single-cycle instructions that complete their access of the explicitly named registers in the E1 pipeline phase. This is true whether MVC is moving a general regis...

Control Register File CPU Data Paths and Control 2-10 SPRU733 2.7.3 Addressing Mode Register (AMR) For each of the eight registers (A4–A7, B4–B7) that can perform linear or circu-lar addressing, the addressing mode register (AMR) specifies the addressing mode. A 2-bit field for each register selects...

Control Register File 2-13 CPU Data Paths and Control SPRU733 2.7.4 Control Status Register (CSR) The control status register (CSR) contains control and status bits. The CSRis shown in Figure 2 − 4 and described in Table 2 − 7. For the PWRD, EN, PCC, and DCC fields, see the device-specific data manu...

Control Register File 2-17 CPU Data Paths and Control SPRU733 2.7.6 Interrupt Enable Register (IER) The interrupt enable register (IER) enables and disables individual interrupts.The IER is shown in Figure 2 − 7 and described in Table 2 − 9. Figure 2 − 7. Interrupt Enable Register (IER) 31 16 Reserv...

Control Register File CPU Data Paths and Control 2-18 SPRU733 2.7.7 Interrupt Flag Register (IFR) The interrupt flag register (IFR) contains the status of INT4 − INT15 and NMI interrupt. Each corresponding bit in the IFR is set to 1 when that interruptoccurs; otherwise, the bits are cleared to 0. If...

Control Register File 2-19 CPU Data Paths and Control SPRU733 2.7.8 Interrupt Return Pointer Register (IRP) The interrupt return pointer register (IRP) contains the return pointer thatdirects the CPU to the proper location to continue program execution afterprocessing a maskable interrupt. A branch ...

Control Register File 2-21 CPU Data Paths and Control SPRU733 2.7.10 Interrupt Service Table Pointer Register (ISTP) The interrupt service table pointer register (ISTP) is used to locate the interruptservice routine (ISR). The ISTB field identifies the base portion of the addressof the interrupt ser...

Control Register File CPU Data Paths and Control 2-22 SPRU733 2.7.11 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP) The NMI return pointer register (NRP) contains the return pointer that directsthe CPU to the proper location to continue program execution after NMIprocessing. A branch usin...

Control Register File Extensions 2-23 CPU Data Paths and Control SPRU733 2.8 Control Register File Extensions The C67x DSP has three additional configuration registers to support floating-point operations. The registers specify the desired floating-point roundingmode for the .L and .M units. They al...

Control Register File Extensions 2-27 CPU Data Paths and Control SPRU733 2.8.2 Floating-Point Auxiliary Configuration Register (FAUCR) The floating-point auxiliary register (FAUCR) contains fields that specifyunderflow or overflow, the rounding mode, NaNs, denormalized numbers, andinexact results fo...

Control Register File Extensions 2-31 CPU Data Paths and Control SPRU733 2.8.3 Floating-Point Multiplier Configuration Register (FMCR) The floating-point multiplier configuration register (FMCR) contains fields thatspecify underflow or overflow, the rounding mode, NaNs, denormalizednumbers, and inex...

3-1 Instruction Set SPRU733 Instruction Set This chapter describes the assembly language instructions of theTMS320C67x DSP. Also described are parallel operations, conditionaloperations, resource constraints, and addressing modes. The C67x floating-point DSP uses all of the instructions available to...

Instruction Operation and Execution Notations Instruction Set 3-2 SPRU733 3.1 Instruction Operation and Execution Notations Table 3 − 1 explains the symbols used in the instruction descriptions. Table 3 − 1. Instruction Operation and Execution Notations Symbol Meaning abs(x) Absolute value of x and ...

Instruction Syntax and Opcode Notations 3-7 Instruction Set SPRU733 3.2 Instruction Syntax and Opcode Notations Table 3 − 2 explains the syntaxes and opcode fields used in the instruction descriptions. The C64x CPU 32-bit opcodes are mapped in Appendix C through Appendix G. Table 3 − 2. Instruction ...

Overview of IEEE Standard Single- and Double-Precision Formats 3-9 Instruction Set SPRU733 3.3 Overview of IEEE Standard Single- and Double-Precision Formats Floating-point operands are classified as single-precision (SP) and double-precision (DP). Single-precision floating-point values are 32-bit v...

Overview of IEEE Standard Single- and Double-Precision Formats 3-11 Instruction Set SPRU733 Figure 3 − 1 shows the fields of a single-precision floating-point number repre- sented within a 32-bit register. Figure 3 − 1. Single-Precision Floating-Point Fields 31 e 23 22 0 30 s f Legend : s sign bit (...

Delay Slots Instruction Set 3-14 SPRU733 3.4 Delay Slots The execution of floating-point instructions can be defined in terms of delayslots and functional unit latency. The number of delay slots is equivalent to thenumber of additional cycles required after the source operands are read for theresult...

Parallel Operations Instruction Set 3-16 SPRU733 3.5 Parallel Operations Instructions are always fetched eight at a time. This constitutes a fetch packet . The basic format of a fetch packet is shown in Figure 3 − 3. Fetch packets are aligned on 256-bit (8-word) boundaries. Figure 3 − 3. Basic Forma...

Parallel Operations 3-17 Instruction Set SPRU733 Example 3 − 1. Fully Serial p -Bit Pattern in a Fetch Packet This p- bit pattern: 0 0 0 0 0 0 0 0 Instruction A Instruction B Instruction C Instruction D Instruction E Instruction F Instruction G Instruction H 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 r...

Parallel Operations Instruction Set 3-18 SPRU733 Example 3 − 3. Partially Serial p -Bit Pattern in a Fetch Packet This p- bit pattern: 31 0 31 0 31 0 31 0 0 0 1 1 31 0 31 0 31 0 31 0 0 1 1 0 Instruction A Instruction B Instruction C Instruction D Instruction E Instruction F Instruction G Instruction...

Conditional Operations 3-19 Instruction Set SPRU733 3.6 Conditional Operations Most instructions can be conditional. The condition is controlled by a 3-bitopcode field ( creg ) that specifies the condition register tested, and a 1-bit field ( z ) that specifies a test for zero or nonzero. The four M...

Resource Constraints Instruction Set 3-20 SPRU733 3.7 Resource Constraints No two instructions within the same execute packet can use the sameresources. Also, no two instructions can write to the same register during thesame cycle. The following sections describe how an instruction can use eachof th...

Resource Constraints Instruction Set 3-24 SPRU733 3.7.6 Constraints on Register Reads More than four reads of the same register cannot occur on the same cycle.Conditional registers are not included in this count. The following execute packets are invalid: MPY .M1 A1, A1, A4 ; five reads of register ...

Addressing Modes Instruction Set 3-30 SPRU733 3.8 Addressing Modes The addressing modes on the C67x DSP are linear, circular using BK0, andcircular using BK1. The addressing mode is specified by the addressing moderegister (AMR), described in section 2.7.3. All registers can perform linear addressin...

Addressing Modes 3-31 Instruction Set SPRU733 3.8.2 Circular Addressing Mode The BK0 and BK1 fields in AMR specify the block sizes for circular addressing,see section 2.7.3. 3.8.2.1 LD and ST Instructions As with linear address arithmetic, offsetR/cst is shifted left by 3, 2, 1, or 0 according to th...

Addressing Modes Instruction Set 3-32 SPRU733 3.8.2.2 ADDA and SUBA Instructions As with linear address arithmetic, offsetR/cst is shifted left by 3, 2, 1, or 0 according to the data size, and is then added to or subtracted from baseR to produce the final address. Circular addressing modifies this s...

Addressing Modes 3-33 Instruction Set SPRU733 Table 3 − 10. Indirect Address Generation for Load/Store Addressing Type No Modification of Address Register Preincrement orPredecrement of Address Register Postincrement orPostdecrement ofAddress Register Register indirect *R *++R* − − R *R++*R − − Regi...

Instruction Compatibility Instruction Set 3-34 SPRU733 3.9 Instruction Compatibility The C62x, C64x, and C67x DSPs share an instruction set. All of the instruc-tions valid for the C62x DSP are also valid for the C67x DSP. See Appendix Afor a list of the instructions that are common to the C62x, C64x...

The way each instruction is described Example 3-35 Instruction Set SPRU733 The way each instruction is described. Example Syntax EXAMPLE (.unit) src , dst .unit = .L1, .L2, .S1, .S2, .D1, .D2 src and dst indicate source and destination, respectively. The ( . unit) dictates which functional unit the ...

Example The way each instruction is described 3-36 Instruction Set SPRU733 Table 3 − 12. Relationships Between Operands, Operand Size, Signed/Unsigned, Functional Units, and Opfields for Example Instruction (ADD) Opcode map field used... For operand type... Unit Opfield src1src2dst sintxsintsint .L1...

The way each instruction is described Example 3-37 Instruction Set SPRU733 Compatibility The C62x, C64x, and C67x DSPs share an instruction set. All of theinstructions valid for the C62x DSP are also valid for the C67x DSP. Thissection identifies which DSP family the instruction is valid. Descriptio...

ABS Absolute Value With Saturation 3-38 Instruction Set SPRU733 Absolute Value With Saturation ABS Syntax ABS (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x op 1 1 0 s p 3 1 5 5 1 7 1...

Absolute Value With Saturation ABS 3-39 Instruction Set SPRU733 Instruction Type Single-cycle Delay Slots 0 See Also ABSDP, ABSSP Example 1 ABS .L1 A1,A5 Before instruction 1 cycle after instruction A1 8000 4E3Dh − 2147463619 A1 8000 4E3Dh − 2147463619 A5 xxxx xxxxh A5 7FFF B1C3h 2147463619 Example ...

ABSDP Absolute Value, Double-Precision Floating-Point 3-40 Instruction Set SPRU733 Absolute Value, Double-Precision Floating-Point ABSDP Syntax ABSDP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 reserved ...

Absolute Value, Double-Precision Floating-Point ABSDP 3-41 Instruction Set SPRU733 Pipeline Stage E1 E2 Read src2_l src2_h Written dst_l dst_h Unit in use .S If dst is used as the source for the ADDDP , CMPEQDP , CMPLTDP , CMPGTDP , MPYDP , or SUBDP instruction, the number of delay slots can be redu...

ABSSP Absolute Value, Single-Precision Floating-Point 3-42 Instruction Set SPRU733 Absolute Value, Single-Precision Floating-Point ABSSP Syntax ABSSP (.unit) src2 , dst .unit = . S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 0 0 0 0 ...

Absolute Value, Single-Precision Floating-Point ABSSP 3-43 Instruction Set SPRU733 Pipeline Stage E1 Read src2 Written dst Unit in use .S Instruction Type Single-cycle Delay Slots 0 Functional UnitLatency 1 See Also ABS, ABSDP Example ABSSP .S1X B1,A5 Before instruction 1 cycle after instruction B1 ...

ADD Add Two Signed Integers Without Saturation 3-44 Instruction Set SPRU733 Add Two Signed Integers Without Saturation ADD Syntax ADD (.unit) src1 , src2 , dst or ADD (.D1 or .D2) src2 , src1 , dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 31 29 28 27 23...

Add Two Signed Integers Without Saturation ADD 3-45 Instruction Set SPRU733 Opcode .S unit 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used... For operand type... Unit Opfield src1src2dst sintxsintsint .S1, .S2 00 0111 src1s...

Add Two Signed Integers Without Saturation ADD 3-47 Instruction Set SPRU733 Example 1 ADD .L2X A1,B1,B2 Before instruction 1 cycle after instruction A1 0000 325Ah 12890 A1 0000 325Ah B1 FFFF FF12h − 238 B1 FFFF FF12h B2 xxxx xxxxh B2 0000 316Ch 12652 Example 2 ADD .L1 A1,A3:A2,A5:A4 Before instructi...

ADDAB Add Using Byte Addressing Mode 3-48 Instruction Set SPRU733 Add Using Byte Addressing Mode ADDAB Syntax ADDAB (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 7 6 5 4 3 2 1 0 creg z dst src2 src1 op 1 0 0 0 0 s p 3 ...

ADDAD Add Using Doubleword Addressing Mode 3-50 Instruction Set SPRU733 Add Using Doubleword Addressing Mode ADDAD Syntax ADDAD (.unit) src2 , src1 , dst .unit = . D1 or .D2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 7 6 5 4 3 2 1 0 creg z dst src2 src1 op 1 0 0 0 0 s p 3 ...

ADDAH Add Using Halfword Addressing Mode 3-52 Instruction Set SPRU733 Add Using Halfword Addressing Mode ADDAH Syntax ADDAH (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 7 6 5 4 3 2 1 0 creg z dst src2 src1 op 1 0 0 0 ...

ADDAW Add Using Word Addressing Mode 3-54 Instruction Set SPRU733 Add Using Word Addressing Mode ADDAW Syntax ADDAW (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 7 6 5 4 3 2 1 0 creg z dst src2 src1 op 1 0 0 0 0 s p 3 ...

ADDDP Add Two Double-Precision Floating-Point Values 3-56 Instruction Set SPRU733 Add Two Double-Precision Floating-Point Values ADDDP Syntax ADDDP (.unit) src1 , src2 , dst (C67x and C67x+ CPU) .unit = .L1 or .L2or ADDDP (.unit) src1 , src2 , dst (C67x+ CPU only) .unit = .S1 or .S2 Compatibility C6...

Add Two Double-Precision Floating-Point Values ADDDP 3-57 Instruction Set SPRU733 Notes: 1) This instruction takes the rounding mode from and sets the warning bits in FADCR, not FAUCR as for other .S unit instructions. 2) If rounding is performed, the INEX bit is set. 3) If one source is SNaN or QNa...

ADDDP Add Two Double-Precision Floating-Point Values 3-58 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 E5 E6 E7 Read src1_lsrc2_l src1_hsrc2_h Written dst _ l dst _ h Unit in use .L or .S .L or .S For the C67x CPU, if dst is used as the source for the ADDDP , CMPEQDP , CMPLTDP , CMPGTDP , MPYD...

Add Signed 16-Bit Constant to Register ADDK 3-59 Instruction Set SPRU733 Add Signed 16-Bit Constant to Register ADDK Syntax ADDK (.unit) cst , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 7 6 5 4 3 2 1 0 creg z dst cst16 1 0 1 0 0 s p 3 1 5 16 1 1 Opc...

ADDSP Add Two Single-Precision Floating-Point Values 3-60 Instruction Set SPRU733 Add Two Single-Precision Floating-Point Values ADDSP Syntax ADDSP (.unit) src1 , src2 , dst (C67x and C67x+ CPU) .unit = .L1 or .L2or ADDSP (.unit) src1 , src2 , dst (C67x+ CPU only) .unit = .S1 or .S2 Compatibility C6...

Add Two Unsigned Integers Without Saturation ADDU 3-63 Instruction Set SPRU733 Add Two Unsigned Integers Without Saturation ADDU Syntax ADDU (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 ...

Add Two 16-Bit Integers on Upper and Lower Register Halves ADD2 3-65 Instruction Set SPRU733 Add Two 16-Bit Integers on Upper and Lower Register Halves ADD2 Syntax ADD2 (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 27 23 22 18 17 13 12 11 6 5...

Bitwise AND AND 3-67 Instruction Set SPRU733 Bitwise AND AND Syntax AND (.unit) src1 , src2 , dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map fiel...

Branch Using a Displacement B 3-69 Instruction Set SPRU733 Branch Using a Displacement B Syntax B (.unit) label .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 7 6 5 4 3 2 1 0 creg z cst21 0 0 1 0 0 s p 3 1 21 1 1 Opcode map field used... For operand type... Unit ...

B Branch Using a Displacement 3-70 Instruction Set SPRU733 Target Instruction Pipeline Stage E1 PS PW PR DP DC E1 Read WrittenBranchTaken Unit in use .S Instruction Type Branch Delay Slots 5 Example Table 3 − 13 gives the program counter values and actions for the following code example. 0000 0000 B...

Branch Using a Register B 3-71 Instruction Set SPRU733 Branch Using a Register B Syntax B (.unit) src2 .unit = .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z 0 0 0 0 0 src2 0 0 0 0 0 x 0 0 1 1 0 1 1 0 0 0 s p 3 1 5 1 1 1 Opcode map fiel...

Branch Using an Interrupt Return Pointer B IRP 3-73 Instruction Set SPRU733 Branch Using an Interrupt Return Pointer B IRP Syntax B (.unit) IRP .unit = .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst 0 0 1 1 0 0 0 0 0 0 x 0 0 0 0 1 1...

Branch Using NMI Return Pointer B NRP 3-75 Instruction Set SPRU733 Branch Using NMI Return Pointer B NRP Syntax B (.unit) NRP .unit = .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst 0 0 1 1 1 0 0 0 0 0 x 0 0 0 0 1 1 1 0 0 0 s p 3 1 5...

Clear a Bit Field CLR 3-77 Instruction Set SPRU733 Clear a Bit Field CLR Syntax CLR (.unit) src2 , csta , cstb , dst or CLR (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode Constant form 31 29 28 27 23 22 18 17 13 12 8 7 6 5 4 3 2 1 0 creg z dst src2 ...

CMPEQ Compare for Equality, Signed Integers 3-80 Instruction Set SPRU733 Compare for Equality, Signed Integers CMPEQ Syntax CMPEQ (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1...

CMPEQDP Compare for Equality, Double-Precision Floating-Point Values 3-82 Instruction Set SPRU733 Compare for Equality, Double-Precision Floating-Point Values CMPEQDP Syntax CMPEQDP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 ...

Compare for Equality, Double-Precision Floating-Point Values CMPEQDP 3-83 Instruction Set SPRU733 Notes: 1) In the case of NaN compared with itself, the result is false. 2) No configuration bits besides those in the preceding table are set, except the NaNn and DENn bits when appropriate. Pipeline St...

CMPEQSP Compare for Equality, Single-Precision Floating-Point Values 3-84 Instruction Set SPRU733 Compare for Equality, Single-Precision Floating-Point Values CMPEQSP Syntax CMPEQSP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 ...

CMPGT Compare for Greater Than, Signed Integers 3-86 Instruction Set SPRU733 Compare for Greater Than, Signed Integers CMPGT Syntax CMPGT (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src...

Compare for Greater Than, Double-Precision Floating-Point Values CMPGTDP 3-89 Instruction Set SPRU733 Compare for Greater Than, Double-Precision Floating-Point Values CMPGTDP Syntax CMPGTDP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 1...

CMPGTDP Compare for Greater Than, Double-Precision Floating-Point Values (C67x CPU) 3-90 Instruction Set SPRU733 Note: No configuration bits other than those shown above are set, except the NaNn and DENn bits when appropriate. Pipeline Stage E1 E2 Read src1_lsrc2_l src1_hsrc2_h Written dst Unit in u...

Compare for Greater Than, Single-Precision Floating-Point Values CMPGTSP 3-91 Instruction Set SPRU733 Compare for Greater Than, Single-Precision Floating-Point Values CMPGTSP Syntax CMPGTSP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 1...

CMPGTSP Compare for Greater Than, Single-Precision Floating-Point Values 3-92 Instruction Set SPRU733 Note: No configuration bits other than those shown above are set, except for the NaNn and DENn bits when appropriate. Pipeline Stage E1 Read src1src2 Written dst Unit in use .S Instruction Type Sing...

Compare for Greater Than, Unsigned Integers CMPGTU 3-93 Instruction Set SPRU733 Compare for Greater Than, Unsigned Integers CMPGTU Syntax CMPGTU (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst s...

Compare for Less Than, Signed Integers CMPLT 3-95 Instruction Set SPRU733 Compare for Less Than, Signed Integers CMPLT Syntax CMPLT (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op...

CMPLTDP Compare for Less Than, Double-Precision Floating-Point Values 3-98 Instruction Set SPRU733 Compare for Less Than, Double-Precision Floating-Point Values CMPLTDP Syntax CMPLTDP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1...

CMPLTSP Compare for Less Than, Single-Precision Floating-Point Values 3-100 Instruction Set SPRU733 Compare for Less Than, Single-Precision Floating-Point Values CMPLTSP Syntax CMPLTSP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 ...

CMPLTU Compare for Less Than, Unsigned Integers 3-102 Instruction Set SPRU733 Compare for Less Than, Unsigned Integers CMPLTU Syntax CMPLTU (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 s...

DPINT Convert Double-Precision Floating-Point Value to Integer 3-104 Instruction Set SPRU733 Convert Double-Precision Floating-Point Value to Integer DPINT Syntax DPINT (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z d...

DPSP Convert Double-Precision Floating-Point Value to Single-Precision Floating-Point Value 3-106 Instruction Set SPRU733 Convert Double-Precision Floating-Point Value to Single-Precision Floating-Point Value DPSP Syntax DPSP (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opc...

DPTRUNC Convert Double-Precision Floating-Point Value to Integer With Truncation 3-108 Instruction Set SPRU733 Convert Double-Precision Floating-Point Value to Integer With Truncation DPTRUNC Syntax DPTRUNC (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 ...

EXT Extract and Sign-Extend a Bit Field 3-110 Instruction Set SPRU733 Extract and Sign-Extend a Bit Field EXT Syntax EXT (.unit) src2 , csta , cstb , dst or EXT (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode Constant form 31 29 28 27 23 22 18 17 13 ...

Extract and Sign-Extend a Bit Field EXT 3-111 Instruction Set SPRU733 Description The field in src2 , specified by csta and cstb , is extracted and sign-extended to 32 bits. The extract is performed by a shift left followed by a signed shift right. csta and cstb are the shift left amount and shift r...

Extract and Zero-Extend a Bit Field EXTU 3-113 Instruction Set SPRU733 Extract and Zero-Extend a Bit Field EXTU Syntax EXTU (.unit) src2 , csta , cstb , dst or EXTU (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode Constant width and offset form: 31 29...

IDLE Multicycle NOP With No Termination Until Interrupt 3-116 Instruction Set SPRU733 Multicycle NOP With No Termination Until Interrupt IDLE Syntax IDLE .unit = none Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 1 1 1 1 0 0 0 0 0 0...

Convert Signed Integer to Double-Precision Floating-Point Value INTDP 3-117 Instruction Set SPRU733 Convert Signed Integer to Double-Precision Floating-Point Value INTDP Syntax INTDP (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 ...

Convert Unsigned Integer to Double-Precision Floating-Point Value INTDPU 3-119 Instruction Set SPRU733 Convert Unsigned Integer to Double-Precision Floating-Point Value INTDPU Syntax INTDPU (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11...

Convert Signed Integer to Single-Precision Floating-Point Value INTSP 3-121 Instruction Set SPRU733 Convert Signed Integer to Single-Precision Floating-Point Value INTSP Syntax INTSP (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 ...

INTSPU Convert Unsigned Integer to Single-Precision Floating-Point Value 3-122 Instruction Set SPRU733 Convert Unsigned Integer to Single-Precision Floating-Point Value INTSPU Syntax INTSPU (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11...

Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDB(U) 3-123 Instruction Set SPRU733 Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDB(U) Syntax Register Offset LDB (.unit) *+ baseR[offsetR] , dst or LDBU (.unit) *+ baseR[offsetR] , dst...

LDB(U) Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-124 Instruction Set SPRU733 The addressing arithmetic that performs the additions and subtractionsdefaults to linear mode. However, for A4 − A7 and for B4 − B7, the mode can be changed to circular mode by writing...

Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDB(U) 3-125 Instruction Set SPRU733 Example LDB .D1 * − A5[4],A7 Before LDB 1 cycle after LDB 5 cycles after LDB A5 0000 0204h A5 0000 0204h A5 0000 0204h A7 1951 1970h A7 1951 1970h A7 FFFF FFE1h AMR 0000 0000h AMR 0000...

Load Byte From Memory With a 15-Bit Unsigned Constant Offset LDB(U) 3-127 Instruction Set SPRU733 Execution if (cond) mem → dst else nop Note: This instruction executes only on the B side (.D2). Pipeline Stage E1 E2 E3 E4 E5 Read B14 / B15 Written dst Unit in use .D2 Instruction Type Load Delay Slot...

LDDW Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset 3-128 Instruction Set SPRU733 Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset LDDW Syntax Register Offset LDDW (.unit) *+ baseR[offsetR] , dst Unsigned Constant Offset LDDW (.unit) *+...

Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset LDDW 3-129 Instruction Set SPRU733 Increments and decrements default to 1 and offsets default to 0 when nobracketed register, bracketed constant, or constant enclosed in parenthesesis specified. Square brackets, [ ], ind...

LDDW Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset 3-130 Instruction Set SPRU733 Delay Slots 4 Functional UnitLatency 1 See Also LDB, LDH, LDW Example 1 LDDW .D2 *+B10[1],A1:A0 Before instruction 5 cycles after instruction A1:A0 xxxx xxxxh xxxx xxxxh A1:A0 4021 3333...

Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDH(U) 3-133 Instruction Set SPRU733 Example LDH .D1 *++A4[A1],A8 Before LDH 1 cycle after LDH 5 cycles after LDH A1 0000 0002h A1 0000 0002h A1 0000 0002h A4 0000 0020h A4 0000 0024h A4 0000 0024h A8 1103 51FFh A8 11...

LDH(U) Load Halfword From Memory With a 15-Bit Unsigned Constant Offset 3-134 Instruction Set SPRU733 Load Halfword From Memory With a 15-Bit Unsigned Constant Offset LDH(U) Syntax LDH (.unit) *+B14/B15[ ucst15 ], dst or LDHU (.unit) *+B14/B15[ ucst15 ], dst .unit = .D2 Compatibility C62x, C64x, C67...

LDW Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-136 Instruction Set SPRU733 Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDW Syntax Register Offset LDW (.unit) *+ baseR[offsetR] , dst Unsigned Constant Offset LDW (.unit) *+ baseR...

Load Word From Memory With a 15-Bit Unsigned Constant Offset LDW 3-139 Instruction Set SPRU733 Load Word From Memory With a 15-Bit Unsigned Constant Offset LDW Syntax LDW (.unit) *+B14/B15[ ucst15 ], dst .unit = .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 9...

Leftmost Bit Detection LMBD 3-141 Instruction Set SPRU733 Leftmost Bit Detection LMBD Syntax LMBD (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1/cst5 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 ...

Multiply Signed 16 LSB x Signed 16 LSB MPY 3-143 Instruction Set SPRU733 Multiply Signed 16 LSB Signed 16 LSB MPY Syntax MPY (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src2 src1 x op 0 ...

Multiply Two Double-Precision Floating-Point Values MPYDP 3-145 Instruction Set SPRU733 Multiply Two Double-Precision Floating-Point Values MPYDP Syntax MPYDP (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z ...

Multiply Signed 16 MSB x Signed 16 MSB MPYH 3-147 Instruction Set SPRU733 Multiply Signed 16 MSB Signed 16 MSB MPYH Syntax MPYH (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src2 src1 x 0 ...

Multiply Signed 16 MSB x Signed 16 LSB MPYHL 3-149 Instruction Set SPRU733 Multiply Signed 16 MSB Signed 16 LSB MPYHL Syntax MPYHL (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src2 src1 x...

Multiply Unsigned 16 MSB x Unsigned 16 LSB MPYHLU 3-151 Instruction Set SPRU733 Multiply Unsigned 16 MSB Unsigned 16 LSB MPYHLU Syntax MPYHLU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst ...

MPYHSLU Multiply Signed 16 MSB x Unsigned 16 LSB 3-152 Instruction Set SPRU733 Multiply Signed 16 MSB Unsigned 16 LSB MPYHSLU Syntax MPYHSLU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst s...

Multiply Signed 16 MSB x Unsigned 16 MSB MPYHSU 3-153 Instruction Set SPRU733 Multiply Signed 16 MSB Unsigned 16 MSB MPYHSU Syntax MPYHSU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src2...

MPYHU Multiply Unsigned 16 MSB x Unsigned 16 MSB 3-154 Instruction Set SPRU733 Multiply Unsigned 16 MSB Unsigned 16 MSB MPYHU Syntax MPYHU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src...

Multiply Unsigned 16 MSB x Signed 16 LSB MPYHULS 3-155 Instruction Set SPRU733 Multiply Unsigned 16 MSB Signed 16 LSB MPYHULS Syntax MPYHULS (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst s...

MPYHUS Multiply Unsigned 16 MSB x Signed 16 MSB 3-156 Instruction Set SPRU733 Multiply Unsigned 16 MSB Signed 16 MSB MPYHUS Syntax MPYHUS (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src2...

MPYI Multiply 32-Bit x 32-Bit Into 32-Bit Result 3-158 Instruction Set SPRU733 Functional UnitLatency 4 See Also MPYID Example MPYI .M1X A1,B2,A3 Before instruction 9 cycles after instruction A1 0034 5678h 3430008 A1 0034 5678h 3430008 B2 0011 2765h 1124197 B2 0011 2765h 1124197 A3 xxxx xxxxh A3 CBC...

Multiply 32-Bit x 32-Bit Into 64-Bit Result MPYID 3-159 Instruction Set SPRU733 Multiply 32-Bit 32-Bit Into 64-Bit Result MPYID Syntax MPYID (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src2 src1 x op...

Multiply Signed 16 LSB x Signed 16 MSB MPYLH 3-161 Instruction Set SPRU733 Multiply Signed 16 LSB Signed 16 MSB MPYLH Syntax MPYLH (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src2 src1 x...

Multiply Unsigned 16 LSB x Unsigned 16 MSB MPYLHU 3-163 Instruction Set SPRU733 Multiply Unsigned 16 LSB Unsigned 16 MSB MPYLHU Syntax MPYLHU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst ...

MPYLSHU Multiply Signed 16 LSB x Unsigned 16 MSB 3-164 Instruction Set SPRU733 Multiply Signed 16 LSB Unsigned 16 MSB MPYLSHU Syntax MPYLSHU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst s...

Multiply Unsigned 16 LSB x Signed 16 MSB MPYLUHS 3-165 Instruction Set SPRU733 Multiply Unsigned 16 LSB Signed 16 MSB MPYLUHS Syntax MPYLUHS (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst s...

MPYSP Multiply Two Single-Precision Floating-Point Values 3-166 Instruction Set SPRU733 Multiply Two Single-Precision Floating-Point Values MPYSP Syntax MPYSP (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z ...

MPYSPDP Multiply Single-Precision Value x Double-Precision Value (C67x+ CPU) 3-168 Instruction Set SPRU733 Multiply Single-Precision Floating-Point Value Double-Precision Floating-Point Value MPYSPDP Syntax MPYSPDP (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x+ CPU only Opcode 31 2...

MPYSP2DP Multiply Two Single-Precision Floating-Point Values for Double-Precision Result (C67x+ CPU) 3-170 Instruction Set SPRU733 Multiply Two Single-Precision Floating-Point Values for Double-Precision Result MPYSP2DP Syntax MPYSP2DP (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x+...

MPYSU Multiply Signed 16 LSB x Unsigned 16 LSB 3-172 Instruction Set SPRU733 Multiply Signed 16 LSB Unsigned 16 LSB MPYSU Syntax MPYSU (.unit) src1, src2, dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src2 src1...

MPYU Multiply Unsigned 16 LSB x Unsigned 16 LSB 3-174 Instruction Set SPRU733 Multiply Unsigned 16 LSB Unsigned 16 LSB MPYU Syntax MPYU (.unit) src1, src2, dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src2 src...

MPYUS Multiply Unsigned 16 LSB x Signed 16 LSB 3-176 Instruction Set SPRU733 Multiply Unsigned 16 LSB Signed 16 LSB MPYUS Syntax MPYUS (.unit) src1, src2, dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 7 6 5 4 3 2 1 0 creg z dst src2 src1...

MV Move From Register to Register 3-178 Instruction Set SPRU733 Move From Register to Register MV Syntax MV (.unit) src2, dst .unit = .L1, .L2, .S1, .S2, .D1, .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x op ...

MVC Move Between Control File and Register File 3-180 Instruction Set SPRU733 Move Between Control File and Register File MVC Syntax MVC (.unit) src2 , dst .unit = .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x op 1...

Move Signed Constant Into Register and Sign Extend MVK 3-183 Instruction Set SPRU733 Move Signed Constant Into Register and Sign Extend MVK Syntax MVK (.unit) cst , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 7 6 5 4 3 2 1 0 creg z dst cst16 0 1 0 1 ...

MVK Move Signed Constant Into Register and Sign Extend 3-184 Instruction Set SPRU733 Instruction Type Single cycle Delay Slots 0 See Also MVKH, MVKL, MVKLH Example 1 MVK .L2 − 5,B8 Before instruction 1 cycle after instruction B8 xxxx xxxxh B8 FFFF FFFBh Example 2 MVK .D2 14,B8 Before instruction 1 c...

Move 16-Bit Constant Into Upper Bits of Register MVKH/MVKLH 3-185 Instruction Set SPRU733 Move 16-Bit Constant Into Upper Bits of Register MVKH/MVKLH Syntax MVKH (.unit) cst , dst or MVKLH (.unit) cst , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 7 6...

MVKH/MVKLH Move 16-Bit Constant Into Upper Bits of Register 3-186 Instruction Set SPRU733 Instruction Type Single-cycle Delay Slots 0 Note: Use the MVK instruction (page 3-183) to load 16-bit constants. The assem- bler generates a warning for any constant over 16 bits. To load 32-bit constants, such...

Move Signed Constant Into Register and Sign Extend − Used with MVKH MVKL 3-187 Instruction Set SPRU733 Move Signed Constant Into Register and Sign Extend MVKL Syntax MVKL (.unit) cst , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 7 6 5 4 3 2 1 0 creg ...

Negate NEG 3-189 Instruction Set SPRU733 Negate NEG Syntax NEG (.unit) src2, dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .S unit 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 0 1 0 1 1 0 1 0 0 0 s p 3 1 5 5 1 1 1 Opcode map field u...

NOP No Operation 3-190 Instruction Set SPRU733 No Operation NOP Syntax NOP [ count ] .unit = none Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 18 17 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 src 0 0 0 0 0 0 0 0 0 0 0 0 p 14 4 1 Opcode map field used... For operand type... Unit src ucs...

NORM Normalize Integer 3-192 Instruction Set SPRU733 Normalize Integer NORM Syntax NORM (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x op 1 1 0 s p 3 1 5 5 1 7 1 1 Opcode map field us...

NOT Bitwise NOT 3-194 Instruction Set SPRU733 Bitwise NOT NOT Syntax NOT (.unit) src2, dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 1 1 1 1 1 x 1 1 0 1 1 1 0 1 1 0 s p 3 1 5 5 1 1 1 Opcode map...

Bitwise OR OR 3-195 Instruction Set SPRU733 Bitwise OR OR Syntax OR (.unit) src1 , src2 , dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field us...

Double-Precision Floating-Point Reciprocal Approximation RCPDP 3-197 Instruction Set SPRU733 Double-Precision Floating-Point Reciprocal Approximation RCPDP Syntax RCPDP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z...

Single-Precision Floating-Point Reciprocal Approximation RCPSP 3-199 Instruction Set SPRU733 Single-Precision Floating-Point Reciprocal Approximation RCPSP Syntax RCPSP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z...

Double-Precision Floating-Point Square-Root Reciprocal Approximation RSQRDP 3-201 Instruction Set SPRU733 Double-Precision Floating-Point Square-Root Reciprocal Approximation RSQRDP Syntax RSQRDP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13...

Single-Precision Floating-Point Square-Root Reciprocal Approximation RSQRSP 3-203 Instruction Set SPRU733 Single-Precision Floating-Point Square-Root Reciprocal Approximation RSQRSP Syntax RSQRSP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13...

Add Two Signed Integers With Saturation SADD 3-205 Instruction Set SPRU733 Add Two Signed Integers With Saturation SADD Syntax SADD (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op...

Add Two Signed Integers With Saturation SADD 3-207 Instruction Set SPRU733 Example 3 SADD .L1X B2,A5:A4,A7:A6 Before instruction 1 cycle after instruction A5:A4 0000 0000h 7C83 39B1h 1922644401 † A5:A4 0000 0000h 7C83 39B1h A7:A6 xxxx xxxxh xxxx xxxxh A7:A6 0000 0000h 8DAD 7953h 2376956243 † B2 112A...

SAT Saturate a 40-Bit Integer to a 32-Bit Integer 3-208 Instruction Set SPRU733 Saturate a 40-Bit Integer to a 32-Bit Integer SAT Syntax SAT (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0...

SET Set a Bit Field 3-210 Instruction Set SPRU733 Set a Bit Field SET Syntax SET (.unit) src2 , csta , cstb , dst or SET (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode Constant form: 31 29 28 27 23 22 18 17 13 12 8 7 6 5 4 3 2 1 0 creg z dst src2 cs...

Arithmetic Shift Left SHL 3-213 Instruction Set SPRU733 Arithmetic Shift Left SHL Syntax SHL (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode...

Arithmetic Shift Right SHR 3-215 Instruction Set SPRU733 Arithmetic Shift Right SHR Syntax SHR (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opco...

Logical Shift Right SHRU 3-217 Instruction Set SPRU733 Logical Shift Right SHRU Syntax SHRU (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode ...

Multiply Signed 16 LSB x Signed 16 LSB With Left Shift and Saturation SMPY 3-219 Instruction Set SPRU733 Multiply Signed 16 LSB Signed 16 LSB With Left Shift and Saturation SMPY Syntax SMPY (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 ...

Multiply Signed 16 MSB x Signed 16 MSB With Left Shift and Saturation SMPYH 3-221 Instruction Set SPRU733 Multiply Signed 16 MSB Signed 16 MSB With Left Shift and Saturation SMPYH Syntax SMPYH (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 ...

SMPYHL Multiply Signed 16 MSB x Signed 16 LSB With Left Shift and Saturation 3-222 Instruction Set SPRU733 Multiply Signed 16 MSB Signed 16 LSB With Left Shift and Saturation SMPYHL Syntax SMPYHL (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 ...

SMPYLH Multiply Signed 16 LSB x Signed 16 MSB With Left Shift and Saturation 3-224 Instruction Set SPRU733 Multiply Signed 16 LSB Signed 16 MSB With Left Shift and Saturation SMPYLH Syntax SMPYLH (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 ...

SPDP Convert Single-Precision Floating-Point Value to Double-Precision Floating-Point Value 3-226 Instruction Set SPRU733 Convert Single-Precision Floating-Point Value to Double-Precision Floating-Point Value SPDP Syntax SPDP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opc...

SPINT Convert Single-Precision Floating-Point Value to Integer 3-228 Instruction Set SPRU733 Convert Single-Precision Floating-Point Value to Integer SPINT Syntax SPINT (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z d...

SPTRUNC Convert Single-Precision Floating-Point Value to Integer With Truncation 3-230 Instruction Set SPRU733 Convert Single-Precision Floating-Point Value to Integer With Truncation SPTRUNC Syntax SPTRUNC (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 ...

SSHL Shift Left With Saturation 3-232 Instruction Set SPRU733 Shift Left With Saturation SSHL Syntax SSHL (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1...

SSUB Subtract Two Signed Integers With Saturation 3-234 Instruction Set SPRU733 Subtract Two Signed Integers With Saturation SSUB Syntax SSUB (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2...

STB Store Byte to Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-236 Instruction Set SPRU733 Store Byte to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STB Syntax Register Offset STB (.unit) src , *+ baseR[offsetR] Unsigned Constant Offset STB (.unit) src , *+ b...

Store Byte to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STB 3-237 Instruction Set SPRU733 Increments and decrements default to 1 and offsets default to zero when nobracketed register or constant is specified. Stores that do no modification tothe baseR can use the syntax *R. Squ...

STB Store Byte to Memory With a 15-Bit Unsigned Constant Offset 3-238 Instruction Set SPRU733 Store Byte to Memory With a 15-Bit Unsigned Constant Offset STB Syntax STB (.unit) src , *+B14/B15[ ucst15 ] .unit = .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 8 7 6 4 3 2 1 ...

STH Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-240 Instruction Set SPRU733 Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STH Syntax Register Offset STH (.unit) src , *+ baseR[offsetR] Unsigned Constant Offset STH (.unit) sr...

Store Halfword to Memory With a 15-Bit Unsigned Constant Offset STH 3-243 Instruction Set SPRU733 Store Halfword to Memory With a 15-Bit Unsigned Constant Offset STH Syntax STH (.unit) src , *+B14/B15[ ucst15 ] .unit = .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 8 7 6 ...

Store Word to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STW 3-245 Instruction Set SPRU733 Store Word to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STW Syntax Register Offset STW (.unit) src , *+ baseR[offsetR] Unsigned Constant Offset STW (.unit) src , *+ b...

Store Word to Memory With a 15-Bit Unsigned Constant Offset STW 3-247 Instruction Set SPRU733 Store Word to Memory With a 15-Bit Unsigned Constant Offset STW Syntax STW (.unit) src , *+B14/B15[ ucst15 ] .unit = .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 8 7 6 4 3 2 1 ...

Subtract Two Signed Integers Without Saturation SUB 3-249 Instruction Set SPRU733 Subtract Two Signed Integers Without Saturation SUB Syntax SUB (.unit) src1 , src2 , dst or SUB (.D1 or .D2) src2 , src1 , dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 31 ...

SUB Subtract Two Signed Integers Without Saturation 3-250 Instruction Set SPRU733 Opcode .S unit 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used... For operand type... Unit Opfield src1src2dst sintxsintsint .S1, .S2 01 0111...

Subtract Using Byte Addressing Mode SUBAB 3-253 Instruction Set SPRU733 Subtract Using Byte Addressing Mode SUBAB Syntax SUBAB (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 7 6 5 4 3 2 1 0 creg z dst src2 src1 op 1 0 0...

Subtract Using Halfword Addressing Mode SUBAH 3-255 Instruction Set SPRU733 Subtract Using Halfword Addressing Mode SUBAH Syntax SUBAH (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 7 6 5 4 3 2 1 0 creg z dst src2 src1 ...

SUBAW Subtract Using Word Addressing Mode 3-256 Instruction Set SPRU733 Subtract Using Word Addressing Mode SUBAW Syntax SUBAW (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 7 6 5 4 3 2 1 0 creg z dst src2 src1 op 1 0 0...

SUBC Subtract Conditionally and Shift − Used for Division 3-258 Instruction Set SPRU733 Subtract Conditionally and Shift—Used for Division SUBC Syntax SUBC (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 c...

SUBDP Subtract Two Double-Precision Floating-Point Values 3-260 Instruction Set SPRU733 Subtract Two Double-Precision Floating-Point Values SUBDP Syntax SUBDP (.unit) src1 , src2 , dst (C67x and C67x+ CPU) .unit = .L1 or .L2or SUBDP (.unit) src1 , src2 , dst (C67x+ CPU only) .unit = .S1 or .S2 Compa...

Subtract Two Single-Precision Floating-Point Values SUBSP 3-263 Instruction Set SPRU733 Subtract Two Single-Precision Floating-Point Values SUBSP Syntax SUBSP (.unit) src1 , src2 , dst (C67x and C67x+ CPU) .unit = .L1 or .L2or SUBSP (.unit) src1 , src2 , dst (C67x+ CPU only) .unit = .S1 or .S2 Compa...

SUBU Subtract Two Unsigned Integers Without Saturation 3-266 Instruction Set SPRU733 Subtract Two Unsigned Integers Without Saturation SUBU Syntax SUBU (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg ...

SUB2 Subtract Two 16-Bit Integers on Upper and Lower Register Halves 3-268 Instruction Set SPRU733 Subtract Two 16-Bit Integers on Upper and Lower Register Halves SUB2 Syntax SUB2 (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 1...

XOR Bitwise Exclusive OR 3-270 Instruction Set SPRU733 Bitwise Exclusive OR XOR Syntax XOR (.unit) src1 , src2 , dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 ...

ZERO Zero a Register 3-272 Instruction Set SPRU733 Zero a Register ZERO Syntax ZERO (.unit) dst .unit = .L1, .L2, .D1, .D2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode Opcode map field used... For operand type... Unit Opfield dst sint .L1, .L2 001 0111 dst slong .L1, .L2 011 0111 d...

4-1 Pipeline SPRU733 Pipeline The C67x DSP pipeline provides flexibility to simplify programming andimprove performance. Two factors provide this flexibility: Control of the pipeline is simplified by eliminating pipeline interlocks. Increased pipelining eliminates traditional architectural bottlenec...

Pipeline Operation Overview Pipeline 4-2 SPRU733 4.1 Pipeline Operation Overview The pipeline phases are divided into three stages: Fetch Decode Execute All instructions in the C67x DSP instruction set flow through the fetch, decode,and execute stages of the pipeline. The fetch stage of the pipeline...

Pipeline Operation Overview 4-3 Pipeline SPRU733 Figure 4 − 2. Fetch Phases of the Pipeline PR PW PS PG PW Memory PS PR PG Registers units Functional (a) (b) CPU PR PW PS PG 256 MVK LDW LDW SHL ADD MVK LDW LDW NOP MVK MV B SADD SMPYH SADD SHR SMPY SHR SMPYH LDW LDW LDW LDW MVK B SMPY SMPYH MV MVKLH ...

Pipeline Operation Overview Pipeline 4-6 SPRU733 4.1.4 Pipeline Operation Summary Figure 4 − 5 shows all the phases in each stage of the C67x DSP pipeline in sequential order, from left to right. Figure 4 − 5. Pipeline Phases Fetch Execute Decode PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 Figu...

Pipeline Operation Overview 4-7 Pipeline SPRU733 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 4 − 1. Operations Occurring During Pipeline Phases Stage Phase Symbol During This Phase Instruction Type Completed Programfetch Program addressgeneration PG The address of the fetch p...

Pipeline Operation Overview Pipeline 4-10 SPRU733 Registers used by the instructions in E1 are shaded in Figure 4 − 7. The multi- plexers used for the input operands to the functional units are also shaded inthe figure. The bold crosspaths are used by the MPY and SUBSP instructions. Figure 4 − 7. Pi...

Pipeline Execution of Instruction Types Pipeline 4-12 SPRU733 4.2 Pipeline Execution of Instruction Types The pipeline operation of the C67x DSP instructions can be categorized intofourteen instruction types. Thirteen of these are shown in Table 4 − 2 ( NOP is not included in the table), which is a ...

Pipeline Execution of Instruction Types 4-13 Pipeline SPRU733 Table 4 − 2. Execution Stage Length Description for Each Instruction Type (Continued) Instruction Type Executionphases 2-Cycle DP 4-Cycle INTDP DP Compare E1 Compute the lowerresults and write toregister Read sources andstart computation ...

Pipeline Execution of Instruction Types Pipeline 4-16 SPRU733 4.2.1 Single-Cycle Instructions Single-cycle instructions complete execution during the E1 phase of the pipe-line (see Table 4 − 3). Figure 4 − 8 shows the fetch, decode, and execute phases of the pipeline that single-cycle instructions u...

Pipeline Execution of Instruction Types 4-17 Pipeline SPRU733 4.2.2 16 y 16-Bit Multiply Instructions The 16 × 16-bit multiply instructions use both the E1 and E2 phases of the pipeline to complete their operations (see Table 4 − 4). Figure 4 − 10 shows the fetch, decode, and execute phases of the p...

Pipeline Execution of Instruction Types Pipeline 4-18 SPRU733 4.2.3 Store Instructions Store instructions require phases E1 through E3 of the pipeline to completetheir operations (see Table 4 − 5). Figure 4 − 12 shows the fetch, decode, and execute phases of the pipeline that the store instructions ...

Pipeline Execution of Instruction Types Pipeline 4-26 SPRU733 4.2.8 INTDP Instruction The INTDP instruction uses the E1 through E5 phases of the pipeline tocomplete its operations (see Table 4 − 10). src2 is read on E1, the lower 32 bits of the result are written on E4, and the upper 32 bits of the ...

Pipeline Execution of Instruction Types Pipeline 4-28 SPRU733 4.2.10 ADDDP/SUBDP Instructions The ADDDP/SUBDP instructions use the E1 through E7 phases of the pipelineto complete their operations (see Table 4 − 12). The lower 32 bits of the result are written on E6, and the upper 32 bits of the resu...

Pipeline Execution of Instruction Types 4-29 Pipeline SPRU733 4.2.11 MPYI Instruction The MPYI instruction uses the E1 through E9 phases of the pipeline tocomplete its operations (see Table 4 − 13). The sources are read on cycles E1 through E4 and the result is written on E9. The MPYI instruction is...

Pipeline Execution of Instruction Types Pipeline 4-30 SPRU733 4.2.12 MPYID Instruction The MPYID instruction uses the E1 through E10 phases of the pipeline tocomplete its operations (see Table 4 − 14). The sources are read on cycles E1 through E4, the lower 32 bits of the result are written on E9, a...

Pipeline Execution of Instruction Types Pipeline 4-32 SPRU733 4.2.14 MPYSPDP Instruction The MPYSPDP instruction uses the E1 through E7 phases of the pipeline tocomplete its operations (see Table 4 − 16). src1 is read on E1 and E2. The lower 32 bits of src2 are read on E1, and the upper 32 bits of s...

Functional Unit Constraints 4-33 Pipeline SPRU733 4.2.15 MPYSP2DP Instruction The MPYSP2DP instruction uses the E1 through E5 phases of the pipeline tocomplete its operations (see Table 4 − 17). src1 and src2 are read on E1. The lower 32 bits of the result are written on E4, and the upper 32 bits of...

Functional Unit Constraints Pipeline 4-34 SPRU733 4.3.1 .S-Unit Constraints Table 4 − 18 shows the instruction constraints for single-cycle instructions executing on the .S unit. Table 4 − 18. Single-Cycle .S-Unit Instruction Constraints Instruction Execution Cycle 1 2 Single-cycle RW Instruction Ty...

Functional Unit Constraints Pipeline 4-42 SPRU733 Table 4 − 26 shows the instruction constraints for MPYI instructions executing on the .M unit. Table 4 − 26. MPYI .M-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 7 8 9 10 MPYI R R R R W Instruction Type Subsequent Same-Unit In...

Performance Considerations Pipeline 4-56 SPRU733 4.4 Performance Considerations The C67x DSP pipeline is most effective when it is kept as full as the algorithmsin the program allow it to be. It is useful to consider some situations that canaffect pipeline performance.A fetch packet (FP) is a groupi...

Performance Considerations 4-57 Pipeline SPRU733 Figure 4 − 28. Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets Clock cycle Fetch packet (FP) Execute packet (EP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n k PG PS PW PR ÉÉ ÉÉ DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 n k+1 ÉÉ ...

Performance Considerations Pipeline 4-58 SPRU733 4.4.2 Multicycle NOPs The NOP instruction has an optional operand, count , that allows you to issue a single instruction for multicycle NOP s. A NOP 2, for example, fills in extra delay slots for the instructions in its execute packet and for all prev...

Performance Considerations 4-59 Pipeline SPRU733 Figure 4 − 30 shows how a multicycle NOP can be affected by a branch. If the delay slots of a branch finish while a multicycle NOP is still dispatching NOP s into the pipeline, the branch overrides the multicycle NOP and the branch target begins execu...

Performance Considerations Pipeline 4-60 SPRU733 4.4.3 Memory Considerations The C67x DSP has a memory configuration with program memory in onephysical space and data memory in another physical space. Data loads andprogram fetches have the same operation in the pipeline, they just use differ-ent pha...

Performance Considerations 4-61 Pipeline SPRU733 Depending on the type of memory and the time required to complete anaccess, the pipeline may stall to ensure proper coordination of data andinstructions. This is discussed in section 4.4.3.1. In the instance where multiple accesses are made to a singl...

Performance Considerations 4-63 Pipeline SPRU733 Table 4 − 41. Loads in Pipeline from Example 4 − 2 i i + 1 i + 2 i + 3 i + 4 i + 5 LDW .D1 Bank 0 E1 E2 E3 − E4 E5 LDW .D2 Bank 0 E1 E2 − E3 E4 E5 For devices that have more than one memory space (see Figure 4 − 34), an access to bank 0 in one space d...

5-1 Interrupts SPRU733 9 Interrupts This chapter describes CPU interrupts, including reset and the nonmaskableinterrupt (NMI). It details the related CPU control registers and their functionsin controlling interrupts. It also describes interrupt processing, the method theCPU uses to detect automatic...

Overview Interrupts 5-2 SPRU733 5.1 Overview Typically, DSPs work in an environment that contains multiple externalasynchronous events. These events require tasks to be performed by the DSPwhen they occur. An interrupt is an event that stops the current process in theCPU so that the CPU can attend t...

Overview 5-3 Interrupts SPRU733 Table 5 − 1. Interrupt Priorities Priority Interrupt Name Interrupt Type Highest Reset Reset NMI Nonmaskable INT4 Maskable INT5 Maskable INT6 Maskable INT7 Maskable INT8 Maskable INT9 Maskable INT10 Maskable INT11 Maskable INT12 Maskable INT13 Maskable INT14 Maskable ...

Overview Interrupts 5-4 SPRU733 5.1.1.2 Nonmaskable Interrupt (NMI) NMI is the second-highest priority interrupt and is generally used to alert theCPU of a serious hardware problem such as imminent power failure. For NMI processing to occur, the nonmaskable interrupt enable (NMIE) bit inthe interrup...

Overview 5-5 Interrupts SPRU733 5.1.1.4 Interrupt Acknowledgment (IACK) and Interrupt Number (INUM n ) The IACK and INUM n signals alert hardware external to the C6000 that an interrupt has occurred and is being processed. The IACK signal indicates thatthe CPU has begun processing an interrupt. The ...

Overview Interrupts 5-6 SPRU733 5.1.2 Interrupt Service Table (IST) When the CPU begins processing an interrupt, it references the interruptservice table (IST). The IST is a table of fetch packets that contain code forservicing the interrupts. The IST consists of 16 consecutive fetch packets.Each in...

Overview 5-7 Interrupts SPRU733 5.1.2.1 Interrupt Service Fetch Packet (ISFP) An ISFP is a fetch packet used to service an interrupt. Figure 5 − 2 shows an ISFP that contains an interrupt service routine small enough to fit in a singlefetch packet (FP). To branch back to the main program, the FP con...

Overview Interrupts 5-8 SPRU733 If the interrupt service routine for an interrupt is too large to fit in a single fetchpacket, a branch to the location of additional interrupt service routine code isrequired. Figure 5 − 3 shows that the interrupt service routine for INT4 was too large for a single f...

Overview 5-9 Interrupts SPRU733 5.1.2.2 Interrupt Service Table Pointer (ISTP) The reset fetch packet must be located at address 0, but the rest of the IST canbe at any program memory location that is on a 256-word boundary. Thelocation of the IST is determined by the interrupt service table base (I...

Overview Interrupts 5-10 SPRU733 5.1.3 Summary of Interrupt Control Registers Table 5 − 2 lists the interrupt control registers on the C67x CPU. Table 5 − 2. Interrupt Control Registers Acronym Register Name Description Page CSR Control status register Allows you to globally set or disable interrupt...

Globally Enabling and Disabling Interrupts 5-11 Interrupts SPRU733 5.2 Globally Enabling and Disabling Interrupts The control status register (CSR) contains two fields that control interrupts:GIE and PGIE, as shown in Figure 2 − 4 (page 2-13) and described in Table 2 − 7 (page 2-14). The global inte...

Individual Interrupt Control 5-13 Interrupts SPRU733 5.3 Individual Interrupt Control Servicing interrupts effectively requires individual control of all three types ofinterrupts: reset, nonmaskable, and maskable. Enabling and disabling individ-ual interrupts is done with the interrupt enable regist...

Interrupt Detection and Processing Interrupts 5-16 SPRU733 5.4 Interrupt Detection and Processing When an interrupt occurs, it sets a flag in the interrupt flag register (IFR).Depending on certain conditions, the interrupt may or may not be processed.This section discusses the mechanics of setting t...

Interrupt Detection and Processing Interrupts 5-18 SPRU733 5.4.3 Actions Taken During Nonreset Interrupt Processing During CPU cycles 6 through 14 of Figure 5 − 4, the following interrupt proces- sing actions occur: Processing of subsequent nonreset interrupts is disabled. For all interrupts except ...

Interrupt Detection and Processing Interrupts 5-20 SPRU733 5.4.5 Actions Taken During RESET Interrupt Processing A low signal on the RESET pin is the only requirement to process a reset. OnceRESET makes a high-to-low transition, the pipeline is flushed and CPU regis-ters are returned to their reset ...

Performance Considerations 5-21 Interrupts SPRU733 5.5 Performance Considerations The interaction of the C6000 CPU and sources of interrupts present perfor-mance issues for you to consider when you are developing your code. 5.5.1 General Performance Overhead . Overhead for all CPU interrupts is 9 cy...

Programming Considerations Interrupts 5-22 SPRU733 5.6 Programming Considerations The interaction of the C6000 CPUs and sources of interrupts present program-ming issues for you to consider when you are developing your code. 5.6.1 Single Assignment Programming Using the same register to store differ...

Programming Considerations 5-23 Interrupts SPRU733 Example 5 − 11. Code Using Single Assignment LDW .D1 *A0,A6 ADD .L1 A1,A2,A3 NOP 3 MPY .M1 A6,A4,A5 ; uses A6 5.6.2 Nested Interrupts Generally, when the CPU enters an interrupt service routine, interrupts aredisabled. However, when the interrupt se...

Programming Considerations Interrupts 5-26 SPRU733 5.6.4 Traps A trap behaves like an interrupt, but is created and controlled with software.The trap condition can be stored in any one of the conditional registers: A1,A2, B0, B1, or B2. If the trap condition is valid, a branch to the trap handlerrou...

A-1 Instruction Compatibility SPRU733 Appendix A Instruction Compatibility The C62x, C64x, and C67x DSPs share an instruction set. All of the instruc-tions valid for the C62x DSP are also valid for the C67x and C67x+ DSPs. TheC67x DSP adds specific instructions for 32-bit integer multiply, doublewor...

B-1 Mapping Between Instruction and Functional Unit SPRU733 Appendix A Mapping Between Instruction and Functional Unit Table B − 1 lists the instructions that execute on each functional unit. Table B − 1. Functional Unit to Instruction Mapping Functional Unit Instruction .L Unit .M Unit .S Unit .D U...

C-1 .D Unit Instructions and Opcode Maps SPRU733 Appendix A .D Unit Instructions and Opcode Maps This appendix lists the instructions that execute in the .D functional unit andillustrates the opcode maps for these instructions. Topic Page C.1 Instructions Executing in the .D Functional Unit C-2 . . ...

Instructions Executing in the .D Functional Unit .D Unit Instructions and Opcode Maps C-2 SPRU733 C.1 Instructions Executing in the .D Functional Unit Table C − 1 lists the instructions that execute in the .D functional unit. Table C − 1. Instructions Executing in the .D Functional Unit Instruction ...

Opcode Map Symbols and Meanings C-3 .D Unit Instructions and Opcode Maps SPRU733 C.2 Opcode Map Symbols and Meanings Table C − 2 lists the symbols and meanings used in the opcode maps. Table C − 2. .D Unit Opcode Map Symbol Definitions Symbol Meaning baseR base address register creg 3-bit field spec...

D-1 .L Unit Instructions and Opcode Maps SPRU733 Appendix A .L Unit Instructions and Opcode Maps This appendix lists the instructions that execute in the .L functional unit andillustrates the opcode maps for these instructions. Topic Page D.1 Instructions Executing in the .L Functional Unit D-2 . . ...

Instructions Executing in the .L Functional Unit .L Unit Instructions and Opcode Maps D-2 SPRU733 D.1 Instructions Executing in the .L Functional Unit Table D − 1 lists the instructions that execute in the .L functional unit. Table D − 1. Instructions Executing in the .L Functional Unit Instruction ...

Opcode Map Symbols and Meanings D-3 .L Unit Instructions and Opcode Maps SPRU733 D.2 Opcode Map Symbols and Meanings Table D − 2 lists the symbols and meanings used in the opcode maps. Table D − 2. .L Unit Opcode Map Symbol Definitions Symbol Meaning creg 3-bit field specifying a conditional registe...

E-1 .M Unit Instructions and Opcode Maps SPRU733 Appendix A .M Unit Instructions and Opcode Maps This appendix lists the instructions that execute in the .M functional unit andillustrates the opcode maps for these instructions. Topic Page E.1 Instructions Executing in the .M Functional Unit E-2 . . ...

Instructions Executing in the .M Functional Unit .M Unit Instructions and Opcode Maps E-2 SPRU733 E.1 Instructions Executing in the .M Functional Unit Table E − 1 lists the instructions that execute in the .M functional unit. Table E − 1. Instructions Executing in the .M Functional Unit Instruction ...

Opcode Map Symbols and Meanings E-3 .M Unit Instructions and Opcode Maps SPRU733 E.2 Opcode Map Symbols and Meanings Table E − 2 lists the symbols and meanings used in the opcode maps. Table E − 2. .M Unit Opcode Map Symbol Definitions Symbol Meaning creg 3-bit field specifying a conditional registe...

32-Bit Opcode Maps .M Unit Instructions and Opcode Maps E-4 SPRU733 E.3 32-Bit Opcode Maps The C67x CPU 32-bit opcodes used in the .M unit are mapped in Figure E − 1 through Figure E − 3. Figure E − 1. Extended M-Unit with Compound Operations 31 29 28 27 23 22 18 17 13 12 11 10 6 5 4 3 2 1 0 creg z ...

F-1 .S Unit Instructions and Opcode Maps SPRU733 Appendix A .S Unit Instructions and Opcode Maps This appendix lists the instructions that execute in the .S functional unit andillustrates the opcode maps for these instructions. Topic Page F.1 Instructions Executing in the .S Functional Unit F-2 . . ...

Instructions Executing in the .S Functional Unit .S Unit Instructions and Opcode Maps F-2 SPRU733 F.1 Instructions Executing in the .S Functional Unit Table F − 1 lists the instructions that execute in the .S functional unit. Table F − 1. Instructions Executing in the .S Functional Unit Instruction ...

Opcode Map Symbols and Meanings F-3 .S Unit Instructions and Opcode Maps SPRU733 F.2 Opcode Map Symbols and Meanings Table F − 2 lists the symbols and meanings used in the opcode maps. Table F − 2. .S Unit Opcode Map Symbol Definitions Symbol Meaning creg 3-bit field specifying a conditional registe...

G-1 No Unit Specified Instructions and Opcode Maps SPRU733 Appendix A No Unit Specified Instructions and Opcode Maps This appendix lists the instructions that execute with no unit specified andillustrates the opcode maps for these instructions. For a list of the instructions that execute in the .D f...

Instructions Executing With No Unit Specified No Unit Specified Instructions and Opcode Maps G-2 SPRU733 G.1 Instructions Executing With No Unit Specified Table G − 1 lists the instructions that execute with no unit specified. Table G − 1. Instructions Executing With No Unit Specified Instruction ID...

32-Bit Opcode Maps G-3 No Unit Specified Instructions and Opcode Maps SPRU733 G.3 32-Bit Opcode Maps The C67x CPU 32-bit opcodes used in the no unit instructions are mapped inFigure G − 1 through Figure G − 3. Figure G − 1. Loop Buffer Instruction Format 31 29 28 27 23 22 18 17 16 13 12 11 10 9 8 7 ...

Index Index-1 SPRU733 Index 1X and 2X paths 2-62-cycle DP instructions, .S-unit instruction constraints 4-36 4-cycle instructions .L-unit instruction constraints 4-49.M-unit instruction constraints 4-41 A A4 MODE bits 2-10A5 MODE bits 2-10A6 MODE bits 2-10A7 MODE bits 2-10ABS instruction 3-38ABSDP i...