Texas Instruments TMS320C64x DSP - Manual

Page 2 - IMPORTANT NOTICE

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections,modifications, enhancements, improvements, and other changes to its products and services atany time and to discontinue any product or service without notice. Customers should obtain thela...

Page 3 - Preface; Read This First; About This Manual; TMS320C6000 CPU and Instruction Set Reference Guide (literature

iii Contents SPRU629 Preface Read This First About This Manual This document describes the video port and VCXO interpolated control (VIC) portin the digital signal processors (DSPs) of the TMS320C6000  DSP family. Notational Conventions This document uses the following conventions. - Hexadecimal nu...

Page 4 - application programming interface (API), which allows you to; Trademarks

Trademarks iv SPRU629 Code Composer Studio Application Programming Interface Reference Guide (literature number SPRU321) describes the Code ComposerStudio  application programming interface (API), which allows you to program custom plug-ins for Code Composer. TMS320C6x Peripheral Support Library Pr...

Page 5 - Contents; Overview

Contents v Contents SPRU629 Contents 1 Overview 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides an overview of the video port peripheral in the digital signal processors (DSPs) of theTMS320C6...

Page 6 - Video Capture Port; Discusses operation of the video capture port.

Contents vi SPRU629 2.6 Video Port Throughput and Latency 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 Video Capture Throughput 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 Video Display Throughput ...

Page 8 - Video Display Port; Discusses the video display port.

Contents viii SPRU629 4 Video Display Port 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discusses the video display port. 4.1 Video Display Mode Selection 4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 9 - General Purpose I/O Operation

Contents ix Contents SPRU629 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) 4-64 . . . . . . . . 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) 4-65 . . . . . . . 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) 4-67 . . . . . ....

Page 10 - VCXO Interpolated Control Port; Provides an overview of the VCXO interpolated control (VIC) port.; Video Port Configuration Examples

Contents x SPRU629 6 VCXO Interpolated Control Port 6-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides an overview of the VCXO interpolated control (VIC) port. 6.1 Overview 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Page 11 - Figures

Figures xi Figures SPRU629 Figures 1–1 Video Port Block Diagram 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 BT.656 Video Capture FIFO Configuration 1-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 15 - Tables

Tables xv Tables SPRU629 Tables 1–1 Video Capture Signal Mapping 1-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Video Display Signal Mapping 1-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 18 - DSP family. Included are an; Topic; Video Port; Chapter 1

1-1 Overview This chapter provides an overview of the video port peripheral in the digitalsignal processors (DSPs) of the TMS320C6000  DSP family. Included are an overview of the video port functions, FIFO configurations, and signal mapping. Topic Page 1.1 Video Port 1-2 . . . . . . . . . . . . . ....

Page 19 - Capture rate up to 80 MHz.

Video Port Overview 1-2 SPRU629 1.1 Video Port The video port peripheral can operate as a video capture port, video displayport, or transport stream interface (TSI) capture port. It provides the followingfunctions: - Video capture mode: J Capture rate up to 80 MHz. J Two channels of 8/10-bit digital...

Page 21 - Figure 1–1. Video Port Block Diagram; Channel B

Video Port Overview 1-4 SPRU629 Figure 1–1. Video Port Block Diagram Internal peripheral bus Memorymapped registers Raw video display pipeline Channel B Channel A Raw video display pipeline Y/C video display pipeline BT.656 display pipeline Y/C video capture pipeline Capture/display buffer (2560 byt...

Page 22 - Video Port FIFO; DMA Interface

Video Port FIFO 1-5 Overview SPRU629 1.2 Video Port FIFO The video port includes a FIFO to store data coming into or out from the videoport. The video port operates in conjunction with DMA transfers to move databetween the video port FIFO and external or on-chip memory. You can pro-gram threshold se...

Page 23 - Video Capture FIFO Configurations; Figure 1–2. BT.656 Video Capture FIFO Configuration

Video Port FIFO Overview 1-6 SPRU629 1.2.2 Video Capture FIFO Configurations During video capture operation, the video port FIFO has one of four configura-tions depending on the capture mode. For BT.656 operation, the FIFO is splitinto channel A and B, as shown in Figure 1–2. Each FIFO is clocked in...

Page 25 - Figure 1–4. Y/C Video Capture FIFO Configuration

Video Port FIFO Overview 1-8 SPRU629 For Y/C video capture, the FIFO is configured as a single channel split into sep-arate Y, Cb, and Cr buffers with separate write pointers and read registers(YSRCA, CBSRCA, and CRSRCA). Figure 1–4 shows how Y data is receivedon the VDIN[9–0] half of the bus and Cb...

Page 26 - Video Display FIFO Configurations; Figure 1–6. BT.656 Video Display FIFO Configuration

Video Port FIFO 1-9 Overview SPRU629 For 16/20-bit raw video, the FIFO is configured as a single buffer, as shownin Figure 1–5. The FIFO receives 16/20-bit data from the VDIN[19–0] bus. TheFIFO has a single write pointer and read register (YSRCA). Figure 1–5. 16/20-Bit Raw Video Capture FIFO Configu...

Page 28 - Figure 1–8. 8/10 Bit Locked Raw Video Display FIFO Configuration

Video Port FIFO 1-11 Overview SPRU629 Figure 1–8. 8/10 Bit Locked Raw Video Display FIFO Configuration Buffer A (2560 bytes) YDSTA VDOUT[9–0] 64 8/10 Display FIFO A Buffer B (2560 bytes) YDSTB VDOUT[19–10] 64 8/10 Display FIFO B For 16/20-bit raw video, the FIFO is configured as a single buffer, as ...

Page 29 - Figure 1–10. Y/C Video Display FIFO Configuration; Video Port Registers; The registers for controlling the video port are in section 2.7.

Video Port Registers Overview 1-12 SPRU629 For Y/C video display, the FIFO is configured as a single channel split into sep-arate Y, Cb, and Cr buffers with separate read pointers and write registers(YDSTA, CBDST, and CRDST). Figure 1–10 shows how Y data is output onthe VDOUT[9–0] half of the bus an...

Page 30 - Video Port Pin Mapping; Table 1–1. Video Capture Signal Mapping

Video Port Pin Mapping 1-13 Overview SPRU629 1.4 Video Port Pin Mapping The video port requires 21 external signal pins for full functionality. Pin usageand direction changes depend on the selected operating mode. Pin functional-ity detail for video capture mode is listed in Table 1–1. Pin functiona...

Page 31 - Table 1–2. Video Display Signal Mapping

Video Port Pin Mapping Overview 1-14 SPRU629 Table 1–2. Video Display Signal Mapping Usage Raw Data Display Mode Video Port Signal I/O BT.656 Display Mode Y/C Display Mode 8/10-Bit 16/20-Bit 8/10-Bit Dual Sync VDATA[9–0] I/O VDOUT[9–0] (Out) VDOUT[9–0] (Out) (Y) VDOUT[9–0] (Out) VDOUT[9–0] (Out) VDO...

Page 32 - VDIN Bus Usage for Capture Modes; Table 1–3. VDIN Data Bus Usage for Capture Modes; Capture Mode

Video Port Pin Mapping 1-15 Overview SPRU629 1.4.1 VDIN Bus Usage for Capture Modes The alignment and usage of data on the VDIN bus depends on the capturemode as shown in Table 1–3. Table 1–3. VDIN Data Bus Usage for Capture Modes Capture Mode BT.656 Y/C Raw Data Data Bus 10-Bit 8-Bit 10-Bit 8-Bit 8...

Page 33 - VDOUT Data Bus Usage for Display Modes; Table 1–4. VDOUT Data Bus Usage for Display Modes; Display Mode

Video Port Pin Mapping Overview 1-16 SPRU629 1.4.2 VDOUT Data Bus Usage for Display Modes The alignment and usage of data on the VDOUT bus depends on the displaymode as shown in Table 1–4. Table 1–4. VDOUT Data Bus Usage for Display Modes Display Mode BT.656 Y/C Dual Sync Raw Data Raw Data Data Bus ...

Page 34 - Chapter 2

2-1 Video Port This chapter discusses the basic operation of the video port. Included is adiscussion of the sources and types of resets, interrupt operation, DMA opera-tion, external clock inputs, video port throughput and latency, and the videoport control registers. Topic Page 2.1 Reset Operation ...

Page 35 - Reset Operation; Peripheral Bus Reset; Clears PEREN bit in PCR to 0.

Reset Operation Video Port 2-2 SPRU629 2.1 Reset Operation The video port has several sources and types of resets. The actions performedby these resets and the state of the port following the resets is described in thefollowing sections. 2.1.1 Power-On Reset Power-on reset is an asynchronous hardwar...

Page 36 - Software Port Reset

Reset Operation 2-3 Video Port SPRU629 If software sets the PEREN bit in PCR but the VPHLT bit in VPCTL remainsset: - VCLK1, VCLK2, and STCLK are enabled to the port (allowing logic resetto complete). - Peripheral bus accesses are acknowledged (RREADY/WREADYreturned) to prevent DMA lock-up. (Any val...

Page 37 - Display Channel Reset; No new DMA events are generated.

Reset Operation Video Port 2-4 SPRU629 Once the port is configured and the VCEN bit is set, the setting of otherVCxCTL bits (except VCEN, RSTCH, and BLKCAP) is prohibited and thecapture counters begin counting. When BLKCAP is cleared, data capture andevent generation may begin. 2.1.5 Display Channel...

Page 38 - Interrupt Operation; Upon receiving an interrupt you should:

Interrupt Operation 2-5 Video Port SPRU629 2.2 Interrupt Operation The video port can generate an interrupt to the DSP core after any of the follow-ing events occur: - Capture complete (CCMPx) bit is set. - Capture overrun (COVRx) bit is set. - Synchronization byte error (SERRx) bit is set. - Vertic...

Page 39 - DMA Operation; Capture DMA Event Generation

DMA Operation Video Port 2-6 SPRU629 2.3 DMA Operation The video port uses up to three DMA events per channel for a total of sixpossible events. Each DMA event uses a dedicated event output. The outputsare: - VPYEVTA - VPCbEVTA - VPCrEVTA - VPYEVTB - VPCbEVTB - VPCrEVTB 2.3.1 Capture DMA Event Gener...

Page 40 - Figure 2–1. Capture DMA Event Generation Flow Diagram

DMA Operation 2-7 Video Port SPRU629 Figure 2–1. Capture DMA Event Generation Flow Diagram Error Overflow error Yes Overflow error FIFO overflow ? No Yes Yes Capture data, DMA active, new events enabled No FIFO overflow ? DMA complete ? Capture Data, DMA active & DMA pending DMA complete ? No Ge...

Page 41 - Display DMA Event Generation; the threshold space still available in the FIFO

DMA Operation Video Port 2-8 SPRU629 Because the capture FIFOs may hold multiple thresholds worth of data, aproblem arises at the boundaries between fields. Since Field 1 and Field 2may have different threshold values, the amount of data in the FIFO requiredto generate the DMA event changes dependin...

Page 42 - Figure 2–2. Display DMA Event Generation Flow Diagram

DMA Operation 2-9 Video Port SPRU629 Figure 2–2. Display DMA Event Generation Flow Diagram Start of fieldFIFO empty Generate DMA event, new events disabled Display data, no DMA pending F ield complete ? Underrun error FIFO underrun ? Display data EOF No Underrun error Underrun error FIFO underrun ? ...

Page 43 - DMA Size and Threshold Restrictions; pixel

DMA Operation Video Port 2-10 SPRU629 A DMA event counter is used to track the number of DMA events generatedin each field as programmed in the VDDISPEVT register. The DISPEVT1 orDISPEVT2 value (depending on the current display field) is loaded at the startof each field. The event counter then decre...

Page 44 - Similarly if a subhorizontal line length is desired (; DMA Interface Operation

DMA Operation 2-11 Video Port SPRU629 Similarly if a subhorizontal line length is desired ( ½ line, for example), then the line length and threshold must be chosen such that the threshold is divisibleby 2. (This can also be stated as the line length must be an even multiple of#DMAs/line × 8). For th...

Page 45 - Clocks; the CPU clock; Table 2–1. Video Port Functional Clocks; Clock; Video Port Functionality Subsets; Data Bus Width

Clocks Video Port 2-12 SPRU629 2.4 Clocks The video port has three external clock inputs as shown in Table 2–1. Nosynchronization is required between the clocks sourced by the external pins.VCLK1 and VCLK2 clock frequencies should be less than the DMA interfaceclock. On 64x devices, the DMA interfac...

Page 46 - FIFO Size; Video Port Throughput and Latency; Video Capture Throughput; is

Video Port Throughput and Latency 2-13 Video Port SPRU629 2.5.2 FIFO Size Some low-cost device implementations with narrow video ports width orrestricted to lower video frequency operations may use a reduced FIFO size.FIFO size does not affect the DMA request mechanism. The selection of 8-bitor 10-b...

Page 47 - Table 2–2. Y/C Video Capture FIFO Capacity; Sample; calculated as the FIFO size divided by t

Video Port Throughput and Latency Video Port 2-14 SPRU629 Table 2–2. Y/C Video Capture FIFO Capacity Sample 8-Bit 10-Bit Dense 10-Bit Y Samples 2560 1920 1280 Cb Samples 1280 960 640 Cr Samples 1280 960 640 Using these values and the formula above, the maximum time to empty theFIFO (t O ) may be cal...

Page 48 - Video Display Throughput; Table 2–3. Raw Video Display FIFO Capacity

Video Port Throughput and Latency 2-15 Video Port SPRU629 2.6.2 Video Display Throughput Video display throughput may be calculated in a manner similar to video capture.In this case, the time to fill the display FIFO must be less than the time to emptythe FIFO or underflow occurs. The 110 MHz displa...

Page 49 - Video Port Control Registers; Table 2–4. Video Port Control Registers; Acronym

Video Port Control Registers Video Port 2-16 SPRU629 A DMA write throughput of at least 330 MBytes/s is required for the highestdisplay rate operation supported by 20-bit implementations of the video port.C64x devices including the video port typically have more than enough DMAbandwidth to support t...

Page 50 - Table 2–5. Video Port Control Register (VPCTL) Field Descriptions; Bit; Value

Video Port Control Registers 2-17 Video Port SPRU629 2.7.1 Video Port Control Register (VPCTL) The video port control register (VPCTL) determines the basic operation of thevideo port. The VPCTL is shown in Figure 2–3 and described in Table 2–5. Not all combinations of the port control bits are uniqu...

Page 52 - Table 2–6. Video Port Operating Mode Selection

Video Port Control Registers 2-19 Video Port SPRU629 Table 2–5. Video Port Control Register (VPCTL) Field Descriptions (Continued) Bit Description Value symval † field † 2 TSI TSI capture mode select bit. NONE 0 TSI capture mode is disabled. CAPTURE 1 TSI capture mode is enabled. 1 DISP Display mode...

Page 53 - Table 2–7. Video Port Status Register (VPSTAT) Field Descriptions

Video Port Control Registers Video Port 2-20 SPRU629 2.7.2 Video Port Status Register (VPSTAT) The video port status register (VPSTAT) indicates the current condition of thevideo port. The VPSTAT is shown in Figure 2–4 and described in Table 2–7. Figure 2–4. Video Port Status Register (VPSTAT) 31 16...

Page 54 - Video Port Interrupt Enable Register (VPIE)

Video Port Control Registers 2-21 Video Port SPRU629 2.7.3 Video Port Interrupt Enable Register (VPIE) The video port interrupt enable register (VPIE) enables sources of the videoport interrupt to the DSP. The VPIE is shown in Figure 2–5 and described inTable 2–8. Figure 2–5. Video Port Interrupt En...

Page 57 - Video Port Interrupt Status Register (VPIS)

Video Port Control Registers Video Port 2-24 SPRU629 2.7.4 Video Port Interrupt Status Register (VPIS) The video port interrupt status register (VPIS) displays the status of video portinterrupts to the DSP. The interrupt is only sent to the DSP if the correspondingenable bit in VPIE is set. All VPIS...

Page 63 - Chapter 3

3-1 Video Capture Port Video capture works by sampling video data on the input pins and saving it tothe video port FIFO. When the amount of captured data reaches aprogrammed threshold level, a DMA is performed to move data from the FIFOinto DSP memory. In some cases, color separation is performed on...

Page 64 - Video Capture Mode Selection; Table 3–1. Video Capture Mode Selection; TSI Bit

Video Capture Mode Selection Video Capture Port 3-2 SPRU629 3.1 Video Capture Mode Selection The video capture module operates in one of nine modes as listed inTable 3–1. The transport stream interface (TSI) selection is made using theTSI bit in the video port control register (VPCTL). The CMODE bit...

Page 65 - BT.656 Video Capture Mode; BT.656 Capture Channels

BT.656 Video Capture Mode 3-3 Video Capture Port SPRU629 3.2 BT.656 Video Capture Mode The BT.656 capture mode captures 8-bit or 10-bit 4:2:2 luma and chroma datamultiplexed into a single data stream. Video data is conveyed in the orderCb,Y,Cr,Y,Cb,Y,Cr, etc. where the sequence Cb,Y,Cr refers to co-...

Page 66 - BT.656 Timing Reference Codes; Table 3–2. BT.656 Video Timing Reference Codes; Data Bit; Byte; Byte

BT.656 Video Capture Mode Video Capture Port 3-4 SPRU629 3.2.2 BT.656 Timing Reference Codes For standard digital video, there are two reference signals, one at the begin-ning of each video data block (start of active video, SAV), and one at the endof each video block (end of active video, EAV). (Te...

Page 67 - Line Information Bits; Table 3–4. Error Correction by Protection Bits; Received

BT.656 Video Capture Mode 3-5 Video Capture Port SPRU629 Bits P0, P1, P2, and P3 have different states depending on the state of bits F,V, and H as shown in Table 3–3. Table 3–3. BT.656 Protection Bits Line Information Bits Protection Bits F V H P3 P2 P1 P0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 ...

Page 68 - BT.656 Image Window and Capture; VCXSTOP and

BT.656 Video Capture Mode Video Capture Port 3-6 SPRU629 Table 3–4. Error Correction by Protection Bits (Continued) Received P 3 –P 0 Bits Received F, V, and H Bits Received P 3 –P 0 Bits 111 110 101 100 011 010 001 000 0111 100 – – 011 100 100 100 – 1000 000 – – – – 101 110 – 1001 – 001 010 – – – –...

Page 69 - Figure 3–1. Video Capture Parameters; Video Source

BT.656 Video Capture Mode 3-7 Video Capture Port SPRU629 Figure 3–1. Video Capture Parameters Capture Image Ystart Xstart Ystop Xstop Field 1 Capture Image Ystart Xstart Ystop Xstop Field 2 Hcount=0 Ycount=1 Ycount=1 Table 3–5 shows common digital camera standards and the number of fieldsper second,...

Page 74 - Y/C Video Capture Mode; Y/C Timing Reference Codes

Y/C Video Capture Mode Video Capture Port 3-12 SPRU629 3.3 Y/C Video Capture Mode The Y/C capture mode is similar to the BT.656 capture mode but captures 8or 10-bit 4:2:2 data on separate luma and chroma data streams. One datastream contains Y samples and the other stream contains multiplexed Cb and...

Page 75 - Y/C Image Window and Capture

Y/C Video Capture Mode 3-13 Video Capture Port SPRU629 3.3.3 Y/C Image Window and Capture The SDTV Y/C format (CCIR601) is an interlaced format consisting of twofields just like BT.656. HDTV Y/C formats may be interlaced or progressivescan. For interlaced capture, the capture windows are programmed ...

Page 79 - BT.656 and Y/C Mode Field and Frame Operation; Capture Determination and Notification

BT.656 and Y/C Mode Field and Frame Operation 3-17 Video Capture Port SPRU629 3.4 BT.656 and Y/C Mode Field and Frame Operation Because DMAs are used to transfer data from the capture FIFOs to memory,there is a large amount of flexibility in the way that capture fields and framesare transferred and ...

Page 80 - CON

BT.656 and Y/C Mode Field and Frame Operation Video Capture Port 3-18 SPRU629 Table 3–6. BT.656 and Y/C Mode Capture Operation VCxCTL Bit CON FRAME CF2 CF1 Operation 0 0 0 0 Reserved 0 0 0 1 Noncontinuous field 1 capture. Capture only field 1. F1C is set afterfield 1 capture and causes CCMPx to be s...

Page 81 - Vertical Synchronization

BT.656 and Y/C Mode Field and Frame Operation 3-19 Video Capture Port SPRU629 Table 3–6. BT.656 and Y/C Mode Capture Operation (Continued) VCxCTL Bit CON Operation CF1 CF2 FRAME 1 0 1 0 Continuous field 2 capture. Capture only field 2. F2C is set after field 2capture and causes CCMPx to be set (CCMP...

Page 82 - Table 3–7. Vertical Synchronization Programming; VMode

BT.656 and Y/C Mode Field and Frame Operation Video Capture Port 3-20 SPRU629 Table 3–7. Vertical Synchronization Programming VCxCTL Bit VMode EXC VRST Vertical Counter Reset Point 0 0 0 First EAV with V=1 after EAV with V=0 – beginning of vertical blanking period.VCOUNT increments on each EAV. 1 0 ...

Page 84 - Horizontal Synchronization; Table 3–8. Horizontal Synchronization Programming

BT.656 and Y/C Mode Field and Frame Operation Video Capture Port 3-22 SPRU629 3.4.3 Horizontal Synchronization Horizontal synchronization determines when the horizontal pixel/samplecounter is reset. The EXC and HRST bits in VCxCTL allow you to program theevent that triggers the start of a line. The ...

Page 86 - Field Identification; Table 3–9. Field Identification Programming; EXC

BT.656 and Y/C Mode Field and Frame Operation Video Capture Port 3-24 SPRU629 3.4.4 Field Identification In order to properly synchronize to the source data stream and capture thecorrect fields, field identification needs to be performed. Field identification ismade using one of three methods: EAV, ...

Page 87 - 4 clock detection window around HSYNC. If both HSYNC and VSYNC; Figure 3–11. Field 1 Detection Timing; Short and Long Field Detect

BT.656 and Y/C Mode Field and Frame Operation 3-25 Video Capture Port SPRU629 The field detect method uses HYSNC and VSYNC based field detect logic.This is used for BT.656 or Y/C systems that provide only HSYNC and VSYNC.The field detect logic samples the state of the HSYNC input on the VSYNCactive ...

Page 88 - Video Input Filtering; Input Filter Modes; scaling, chrominance; Table 3–10. Input Filter Mode Selection; CMODE

Video Input Filtering Video Capture Port 3-26 SPRU629 VCTL2 is a VSYNC (vertical sync) input, then a long field is always detected.(Even if VCYSTOPn is set to the last active line, VCOUNT usually incrementspast VCYSTOPn + 1 while it counts the vertical front porch lines that occurprior to VSYNC acti...

Page 89 - Chrominance Resampling Operation; Figure 3–12. Chrominance Resampling; Scaling Operation; The

Video Input Filtering 3-27 Video Capture Port SPRU629 3.5.2 Chrominance Resampling Operation Chrominance resampling computes chrominance values at sample pointsmidway between the input luminance samples based on the input co-sitedchrominance samples. This filter performs the horizontal portion of a ...

Page 90 - Figure 3–14. 1/2 Scaled Chrominance Resampled Filtering; Note that because input scaling is limited to

Video Input Filtering Video Capture Port 3-28 SPRU629 Figure 3–13. 1/2 Scaled Co-Sited Filtering YCbCr 4:2:2 co-sited input samples 1/2 scaled co-sited capture results Luma (Y)sample Y’ h = (–3Y e + 32Y g + 70Y h + 32Y i – 3Y k ) / 128 – Chroma (Cb/Cr)samples – a b c d e f g h i j k l Y’ f = (–3Y c ...

Page 91 - Edge Pixel Replication; Figure 3–15. Edge Pixel Replication

Video Input Filtering 3-29 Video Capture Port SPRU629 3.5.4 Edge Pixel Replication Because the filters make use of preceding and trailing samples, filtering arti-facts can occur at the beginning of the BT.656 or Y/C active line because nosamples exist before the SAV code, and at the end of the BT.65...

Page 92 - Figure 3–16. Capture Window Not Requiring Edge Pixel Replication

Video Input Filtering Video Capture Port 3-30 SPRU629 Figure 3–16 shows an example of a capture window that is smaller than theBT.656 active line. Sample a is the first sample in the horizontal capturewindow and sample n is the last sample. In this case, any filtering done on thefirst sample locatio...

Page 93 - Ancillary Data Capture

Ancillary Data Capture 3-31 Video Capture Port SPRU629 3.6 Ancillary Data Capture The BT.656 and some Y/C specifications includes provision for carrying ancillary(nonvideo) data within the horizontal and vertical blanking regions. Horizontalancillary (HANC) data appears between the EAV code and SAV ...

Page 94 - Raw Data Capture Mode; Raw Data Capture Notification

Raw Data Capture Mode Video Capture Port 3-32 SPRU629 3.7 Raw Data Capture Mode In the raw data capture mode, the data is sampled by the interface only whenthe CAPEN signal is active. Data is captured at the rate of the sender’s clock,without any interpretation or start/stop of capture based on the ...

Page 95 - Raw Data Mode Capture Operation; Raw Data FIFO Packing

Raw Data Capture Mode 3-33 Video Capture Port SPRU629 Table 3–11. Raw Data Mode Capture Operation VCxCTL Bit CON FRAME CF2 CF1 Operation 0 0 x x Noncontinuous frame capture. FRMC is set after data block captureand causes CCMPx to be set. Capture will halt upon completion of thenext frame unless the ...

Page 96 - Figure 3–18. 10-Bit Raw Data FIFO Packing

Raw Data Capture Mode Video Capture Port 3-34 SPRU629 The 8-bit raw-data mode stores all data in a single FIFO. Four samples arepacked into each word as shown in Figure 3–17. Figure 3–17. 8-Bit Raw Data FIFO Packing Raw FIFO Raw 2 Raw 4 Raw 6 Raw 1 Raw 3 Raw 5 Raw 7 VDIN[9–2] / VDIN[19–12] VCLKINA /...

Page 97 - Figure 3–19. 10-Bit Dense Raw Data FIFO Packing

Raw Data Capture Mode 3-35 Video Capture Port SPRU629 The 10-bit dense raw data mode stores all data into a single FIFO. Three sam-ples are packed into each word with zero extension as shown in Figure 3–19. Figure 3–19. 10-Bit Dense Raw Data FIFO Packing VDOUT[9–0] VCLKOUT 32 Y FIFO Raw 0 Raw 2 Raw ...

Page 98 - Figure 3–21. 20-Bit Raw Data FIFO Packing

Raw Data Capture Mode Video Capture Port 3-36 SPRU629 The 20-bit raw data mode stores all data into a single FIFO. One sample isplaced right justified in each word and zero or sign extended as shown inFigure 3–21. Figure 3–21. 20-Bit Raw Data FIFO Packing VDIN[19–0] VCLKINA 63 5251 32 Y FIFO Raw 0 R...

Page 99 - TSI Capture Mode; TSI Capture Features

TSI Capture Mode 3-37 Video Capture Port SPRU629 3.8 TSI Capture Mode The transport stream interface (TSI) capture mode captures MPEG-2 trans-port data. 3.8.1 TSI Capture Features The video port TSI capture mode supports the following features: - Supports SYNC detect using the PACSTRT input from a f...

Page 100 - Figure 3–22. Parallel TSI Capture; TSI Capture Error Detection

TSI Capture Mode Video Capture Port 3-38 SPRU629 Figure 3–22. Parallel TSI Capture PACSTRT VCLKIN CAPEN VDIN[9:2] Sync Byte Byte 1 Byte 2 Byte 3 ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉÉ Byte 4 Start Capture 3.8.3 TSI Capture Error Detection The video port checks for two types of errors during TSI capture. The first isa pa...

Page 101 - Figure 3–24. System Time Clock Counter Operation

TSI Capture Mode 3-39 Video Capture Port SPRU629 Figure 3–23. Program Clock Reference (PCR) Header Format 47 15 14 9 8 0 PCR Reserved PCR extension The video port, in conjunction with the VCXO interpolated control (VIC), allowsa combined hardware and software solution to synchronize the local system...

Page 102 - TSI Data Capture Notification; Table 3–12. TSI Capture Mode Operation; VCACTL Bit

TSI Capture Mode Video Capture Port 3-40 SPRU629 The system time clock counter is initialized by software with the PCR of the firstpacket with a PCR header. After initialization, the counter can be reinitializedby software upon detecting a discontinuity in subsequent packet PCR headervalues. The sys...

Page 103 - Writing to the FIFO; Figure 3–25. TSI FIFO Packing

TSI Capture Mode 3-41 Video Capture Port SPRU629 3.8.6 Writing to the FIFO The captured TSI packet data and the associated timestamps are written intothe receive FIFO. The packet data is written first, followed by the timestamp.The FIFO controller controls both data writes and timestamp writes into ...

Page 104 - Reading from the FIFO; Capture Line Boundary Conditions

Capture Line Boundary Conditions Video Capture Port 3-42 SPRU629 Figure 3–27. TSI Timestamp Format (Big Endian) 63 56 55 48 47 40 39 32 PCR(7–0) PCR(15–8) PCR(23–16) PCR(31–24) 31 25 24 23 18 17 16 PCR extension (6–0) PCR32 Reserved PCR ext (8–7) 15 8 7 6 5 0 Reserved PERR PSTERR Reserved 3.8.7 Read...

Page 105 - Figure 3–28. Capture Line Boundary Example

Capture Line Boundary Conditions 3-43 Video Capture Port SPRU629 In Figure 3–28 (8-bit Y/C mode), the line length is not a doubleword. When thecondition HCOUNT = VCXSTOP occurs, the FIFO location is written eventhough 8 bytes have not been received. The next capture line then begins inthe next FIFO ...

Page 106 - ) Set the last pixel to be captured in VCxSTOP1 and VCxSTOP2 (set the

Capturing Video in BT.656 or Y/C Mode Video Capture Port 3-44 SPRU629 3.10 Capturing Video in BT.656 or Y/C Mode In order to capture video in the BT.656 or Y/C format, the following steps areneeded: 1) Set the last pixel to be captured in VCxSTOP1 and VCxSTOP2 (set the VCXSTOP and VCYSTOP bits). 2) ...

Page 107 - Set VCEN bit to enable capture.

Capturing Video in BT.656 or Y/C Mode 3-45 Video Capture Port SPRU629 8) Write to VCxCTL to: - Set capture mode (CMODE = 00x for BT.656 input, 10x for Y/C input). - Set desired field/frame operation (CON, FRAME, CF2, CF1 bits). - Set sync and field ID control (VRST, HRST, FDD, FINV, VCTL1 bits). - S...

Page 108 - Capturing Video in Raw Data Mode

Capturing Video in Raw Data Mode Video Capture Port 3-46 SPRU629 3.11 Capturing Video in Raw Data Mode In order to capture video in the raw data mode, the following steps are needed: 1) Set VCxSTOP1 to specify size of an image to be captured (VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper...

Page 109 - Handling FIFO Overrun Condition in Raw Data Mode; Capturing Data in TSI Capture Mode; Enable error packet filtering (ERRFILT) if desired

Capturing Data in TSI Capture Mode 3-47 Video Capture Port SPRU629 3.11.1 Handling FIFO Overrun Condition in Raw Data Mode In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiatesan interrupt to the DSP, if the overrun interrupt is enabled (setting the COVRxbit in VPIE enabl...

Page 110 - needed to initiate an interrupt, based on STC absolute time.; Handling FIFO Overrun Condition in TSI Capture Mode

Capturing Data in TSI Capture Mode Video Capture Port 3-48 SPRU629 6) Write to TSISTCMPL, TSISTCMPM, TSISTMSKL, and TSISTMSKM if needed to initiate an interrupt, based on STC absolute time. 7) Write to TSITICKS if an interrupt is desired every x cycles of STC. 8) Write to VPCTL to select TSI capture...

Page 111 - Video Capture Registers; Table 3–13. Video Capture Control Registers

Video Capture Registers 3-49 Video Capture Port SPRU629 3.13 Video Capture Registers The registers for controlling the video capture mode of operation are listed inTable 3–13. See the device-specific datasheet for the memory address ofthese registers. Table 3–13. Video Capture Control Registers Acro...

Page 113 - Table 3–14. Video Capture Channel x Status Register (VCxSTAT); Description

Video Capture Registers 3-51 Video Capture Port SPRU629 Table 3–14. Video Capture Channel x Status Register (VCxSTAT) Field Descriptions Description Bit field † symval † Value BT.656 or Y/C Mode Raw Data Mode TSI Mode 31 FSYNC Current frame sync bit. CLEARD 0 VCOUNT = VINT1 orVINT2, as selectedby th...

Page 115 - Figure 3–30. Video Capture Channel A Control Register (VCACTL)

Video Capture Registers 3-53 Video Capture Port SPRU629 3.13.2 Video Capture Channel A Control Register (VCACTL) Video capture is controlled by the video capture channel A control register(VCACTL) shown in Figure 3–30 and described in Table 3–15. Figure 3–30. Video Capture Channel A Control Register...

Page 116 - Table 3–15. Video Capture Channel A Control Register (VCACTL)

Video Capture Registers Video Capture Port 3-54 SPRU629 Table 3–15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) Description Bit TSI Mode Raw Data Mode BT.656 or Y/C Mode Value symval † field † 30 BLKCAP Block capture events bit. BLKCAP functions as a capture FIFO...

Page 126 - Field Descriptions

Video Capture Registers Video Capture Port 3-64 SPRU629 Table 3–20. Video Capture Channel x Vertical Interrupt Register (VCxVINT) Field Descriptions Description Bit field † symval † Value BT.656 or Y/C Mode Raw Data Mode TSI Mode 31 VIF2 Setting of VINT in field 2 enable bit. DISABLE 0 Setting of VI...

Page 127 - VCTHRLD1, certain restrictions are placed on what VCTHRLD1

Video Capture Registers 3-65 Video Capture Port SPRU629 3.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) The video capture channel x threshold register (VCATHRLD, VCBTHRLD)determines when DMA requests are sent. VCxTHRLD is shown inFigure 3–36 and described in Table 3–21. The VC...

Page 130 - Video Capture Channel B Control Register (VCBCTL); Figure 3–38. Video Capture Channel B Control Register (VCBCTL)

Video Capture Registers Video Capture Port 3-68 SPRU629 3.13.10 Video Capture Channel B Control Register (VCBCTL) Video capture is controlled by the video capture channel B control register(VCBCTL) shown in Figure 3–38 and described in Table 3–23. Figure 3–38. Video Capture Channel B Control Registe...

Page 131 - Table 3–23. Video Capture Channel B Control Register (VCBCTL)

Video Capture Registers 3-69 Video Capture Port SPRU629 Table 3–23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) Description Bit TSI Mode Raw Data Mode BT.656 or Y/C Mode Value symval † field † 30 BLKCAP Block capture events bit. BLKCAP functions as a capture FIFO...

Page 136 - TSI Clock Initialization LSB Register (TSICLKINITL); Figure 3–40. TSI Clock Initialization LSB Register (TSICLKINITL)

Video Capture Registers Video Capture Port 3-74 SPRU629 3.13.12 TSI Clock Initialization LSB Register (TSICLKINITL) The transport stream interface clock initialization LSB register (TSICLKINITL)is used to initialize the hardware counter to synchronize with the system timeclock. TSICLKINITL is shown ...

Page 137 - TSI Clock Initialization MSB Register (TSICLKINITM); Figure 3–41. TSI Clock Initialization MSB Register (TSICLKINITM)

Video Capture Registers 3-75 Video Capture Port SPRU629 3.13.13 TSI Clock Initialization MSB Register (TSICLKINITM) The transport stream interface clock initialization MSB register (TSICLKINITM)is used to initialize the hardware counter to synchronize with the system timeclock. TSICLKINITM is shown ...

Page 138 - TSI System Time Clock LSB Register (TSISTCLKL)

Video Capture Registers Video Capture Port 3-76 SPRU629 3.13.14 TSI System Time Clock LSB Register (TSISTCLKL) The transport stream interface system time clock LSB register (TSISTCLKL)contains the 32 least-significant bits (LSBs) of the program clock reference(PCR). The system time clock value is ob...

Page 139 - TSI System Time Clock MSB Register (TSISTCLKM)

Video Capture Registers 3-77 Video Capture Port SPRU629 3.13.15 TSI System Time Clock MSB Register (TSISTCLKM) The transport stream interface system time clock MSB register (TSISTCLKM)contains the most-significant bit (MSB) of the program clock reference (PCR)and the 9 bits of the PCR extension. The...

Page 140 - TSI System Time Clock Compare LSB Register (TSISTCMPL); Figure 3–44. TSI System Time Clock Compare LSB Register (TSISTCMPL); Table 3–29. TSI System Time Clock Compare LSB Register (TSISTCMPL)

Video Capture Registers Video Capture Port 3-78 SPRU629 3.13.16 TSI System Time Clock Compare LSB Register (TSISTCMPL) The transport stream interface system time clock compare LSB register(TSISTCMPL) is used to generate an interrupt at some absolute time basedon the STC. TSISTCMPL holds the 32 least...

Page 141 - TSI System Time Clock Compare MSB Register (TSISTCMPM); Figure 3–45. TSI System Time Clock Compare MSB Register (TSISTCMPM); Table 3–30. TSI System Time Clock Compare MSB Register (TSISTCMPM)

Video Capture Registers 3-79 Video Capture Port SPRU629 3.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM) The transport stream interface system time clock compare MSB register(TSISTCMPM) is used to generate an interrupt at some absolute time basedon the STC. TSISTCMPM holds the most-sig...

Page 142 - TSI System Time Clock Compare Mask LSB Register (TSISTMSKL)

Video Capture Registers Video Capture Port 3-80 SPRU629 3.13.18 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) The transport stream interface system time clock compare mask LSB register(TSISTMSKL) holds the 32 least-significant bits (LSBs) of the absolute timecompare mask (ATCM). This v...

Page 143 - TSI System Time Clock Compare Mask MSB Register (TSISTMSKM)

Video Capture Registers 3-81 Video Capture Port SPRU629 3.13.19 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) The transport stream interface system time clock compare mask MSB register(TSISTMSKM) holds the most-significant bit (MSB) of the absolute timecompare mask (ATCM). This value i...

Page 144 - TSI System Time Clock Ticks Interrupt Register (TSITICKS)

Video Capture Registers Video Capture Port 3-82 SPRU629 3.13.20 TSI System Time Clock Ticks Interrupt Register (TSITICKS) The transport stream interface system time clock ticks interrupt register(TSITICKS) is used to generate an interrupt after a certain number of ticks ofthe 27-MHz system time cloc...

Page 145 - Video Capture FIFO Registers; Table 3–34. Video Capture FIFO Registers

Video Capture FIFO Registers 3-83 Video Capture Port SPRU629 3.14 Video Capture FIFO Registers The capture FIFO mapping registers are listed in Table 3–34. These registersprovide read access to the capture FIFOs. These pseudo-registers should bemapped into DSP memory space rather than configuration ...

Page 146 - Chapter 4

4-1 Video Display Port The video port peripheral can operate as a video capture port, video displayport, or transport stream interface (TSI) capture port. This chapter discussesthe video display port. Topic Page 4.1 Video Display Mode Selection 4-2 . . . . . . . . . . . . . . . . . . . . . . . . . ....

Page 147 - Video Display Mode Selection; Table 4–1. Video Display Mode Selection; DMODE Bits; Image Timing

Video Display Mode Selection Video Display Port 4-2 SPRU629 4.1 Video Display Mode Selection The video display module operates in one of three modes as listed inTable 4–1. The DMODE bits are in the video display control register (VDCTL).The Y/C and 16/20-bit raw display modes may only be selected if...

Page 148 - Figure 4–1. NTSC Compatible Interlaced Display; Figure 4–2. SMPTE 296M Compatible Progressive Scan Display

Video Display Mode Selection 4-3 Video Display Port SPRU629 Figure 4–1. NTSC Compatible Interlaced Display Line 20 Line 21 Line 22 Line 261 Line 262 Line 263 Line 282 Line 283 Line 284 Line 523 Line 524 Line 525 Field 1 Field 2 Figure 4–2. SMPTE 296M Compatible Progressive Scan Display Line 26 Line ...

Page 149 - Figure 4–3. Interlaced Blanking Intervals and Video Areas

Video Display Mode Selection Video Display Port 4-4 SPRU629 Figure 4–3. Interlaced Blanking Intervals and Video Areas Field 1 Vertical Blanking Horizontal Blanking Field 1 Image Horiz. Of fset Field 1 Image Vertical Offset Field 1 Image Width Field 1 Image Height Field 1 Active Video Field 1 Frame F...

Page 150 - Figure 4–4. Progressive Blanking Intervals and Video Area; Video Display Counters

Video Display Mode Selection 4-5 Video Display Port SPRU629 Figure 4–4. Progressive Blanking Intervals and Video Area Field 1 Image Width Field 1 Frame Field 1 Image Height Field 1 Vertical Blanking Field 1 Image Vertical Offset Field 1 Active Video 4.1.2 Video Display Counters To generate the image...

Page 151 - Figure 4–5. Horizontal Blanking and Horizontal Sync Timing

Video Display Mode Selection Video Display Port 4-6 SPRU629 The image line counter (ILCOUNT) and the image pixel counter (IPCOUNT)track the visible image within the field. ILCOUNT begins counting at the firstdisplay image line in each field. IPCOUNT begins counting at the first dis-played image pixe...

Page 152 - Figure 4–6. Vertical Blanking, Sync and Even/Odd Frame Signal Timing; Sync Signal Generation

Video Display Mode Selection 4-7 Video Display Port SPRU629 Note that the signals can transition at any place along the video line (specifiedby the XSTART and XSTOP bits of the appropriate registers). In this case,VBLNK starts at horizontal count VBLNKXSTART2 = 429 on scan lineVBLNKYSTART2 = 263 (56...

Page 153 - External Sync Operation; Figure 4–7. Video Display Module Synchronization Chain

Video Display Mode Selection Video Display Port 4-8 SPRU629 4.1.4 External Sync Operation The video display module may be synchronized with an external video sourceusing external sync signals. VCTL1 may be configured as an external horizon-tal sync input. When the external HSYNC is asserted, FPCOUNT...

Page 154 - BT.656 Video Display Mode; Display Timing Reference Codes

BT.656 Video Display Mode 4-9 Video Display Port SPRU629 4.2 BT.656 Video Display Mode The BT.656 display mode outputs 8-bit or 10-bit 4:2:2 co-sited luma and chromadata multiplexed into a single data stream. Pixels are output in pairs with eachpair consisting of two luma samples and two chroma samp...

Page 155 - HBLNKSTART. The SAV code is inserted when; Line Number

BT.656 Video Display Mode Video Display Port 4-10 SPRU629 Figure 4–10. 625/50 BT.656 Horizontal Blanking Timing One Line 861 862 863 0 1 2 718 719 720 721 722 723 720 721 722 723 FPCOUNT Active Video Blanking VCLKOUT Next Line 4 4 280 1440 VDOUT[9–0] 80.0 80.0 10.0 FF .C 00.0 00.0 Cb 0 Y 2 Cb 359 Y ...

Page 156 - Figure 4–11. Digital Vertical F and V Transitions; LIne Number

BT.656 Video Display Mode 4-11 Video Display Port SPRU629 Figure 4–11. Digital Vertical F and V Transitions Blanking Optional blanking Line 4 Image: Field 1 Blanking Line 266 Optional blanking Image: Field 2 Line 3 H = 1 (EAV) H = 0 (SAV) 1(V = 1) 10 (V = X) 20 (V = 0) 264 (V = 1) 273 (V = X) 283 (V...

Page 157 - Blanking Codes

BT.656 Video Display Mode Video Display Port 4-12 SPRU629 4.2.2 Blanking Codes The time between the EAV and SAV code on each line represents the horizontalblanking interval. During this time, the video port outputs digital video blankingvalues. These values are 10.0h for luma (Y) samples and 80.0h f...

Page 158 - BT.656 FIFO Unpacking

BT.656 Video Display Mode 4-13 Video Display Port SPRU629 4.2.4 BT.656 FIFO Unpacking Display data is always packed into the FIFOs in 64-bit words and must beunpacked before being sent to the video display data pipeline. The unpackingand byte ordering is dependant upon the display data size and the ...

Page 161 - Y/C Video Display Mode; Y/C Display Timing Reference Codes

Y/C Video Display Mode Video Display Port 4-16 SPRU629 4.3 Y/C Video Display Mode The Y/C display mode is similar to the BT.656 display mode but outputs 8 or10-bit data on separate luma and chroma data streams. One data streamcontains Y samples and the other stream contains multiplexed Cb and Crsamp...

Page 166 - Video Output Filtering; Output Filter Modes; The output filter has four modes of operation: no-filtering, 2; Table 4–3. Output Filter Mode Selection; VDCTL Bit

Video Output Filtering 4-21 Video Display Port SPRU629 4.4 Video Output Filtering The video output filter performs simple hardware scaling and resampling onoutgoing 8-bit BT.656 or 8-bit Y/C data. Filtering hardware is disabled during10-bit or raw data display modes. 4.4.1 Output Filter Modes The ou...

Page 167 - Figure 4–19. Chrominance Resampling

Video Output Filtering Video Display Port 4-22 SPRU629 4.4.2 Chrominance Resampling Operation Chrominance resampling computes chrominance values at sample pointscorresponding to output luminance samples based on the input interspersedchrominance samples. This filter performs the conversion between i...

Page 168 - Figure 4–21. 2x Interspersed Scaling; Figure 4–22. Output Edge Pixel Replication

Video Output Filtering 4-23 Video Display Port SPRU629 Figure 4–20. 2x Co-Sited Scaling 2 × upscaled output YCbCr 4:2:2 co–sited source pixels Luma (Y) sample Y’d’ = (–1Yc + 17Yd + 17Ye – 1Yf ) / 32 Cb’d = (–1Cba + 17Cbc + 17Cbe – 1Cbg ) / 32Cr’d = (–1Cra + 17Crc + 17Cre – 1Crg ) / 32 – Chroma (Cb/C...

Page 169 - Examples of luma edge and chroma edge replication for 2; Figure 4–23. Luma Edge Replication

Video Output Filtering Video Display Port 4-24 SPRU629 Examples of luma edge and chroma edge replication for 2 × interspersed to co-sited output are shown in Figure 4–23 and Figure 4–24, respectively. Figure 4–23. Luma Edge Replication a a’ b b’ c a y’ z z’ x x’ y a b c z x y Horizontal Image Size L...

Page 170 - Ancillary Data Display

Ancillary Data Display 4-25 Video Display Port SPRU629 4.5 Ancillary Data Display The following sections discuss ancillary data display. No special previsions aremade for the display of horizontal ancillary (HANC) or vertical ancillary (VANC),also called vertical blanking interval (VBI), data. 4.5.1...

Page 171 - Raw Mode RGB Output Support; unpacking is selected (RGBX bit in; Raw Data FIFO Unpacking

Raw Data Display Mode Video Display Port 4-26 SPRU629 4.6.1 Raw Mode RGB Output Support The raw data display mode has a special pixel count feature that allows theFPCOUNT increment rate to be set. FPCOUNT increments only when INCPIXsamples have been sent out. This option allows proper tracking of th...

Page 172 - Figure 4–27. 10-Bit Raw Dense FIFO Unpacking

Raw Data Display Mode 4-27 Video Display Port SPRU629 For 10-bit operation, two samples are unpacked from each FIFO word. Thisis shown in Figure 4–26. Figure 4–26. 10-Bit Raw FIFO Unpacking VDOUT[9–0] VCLKOUT 63 58 57 48 47 42 41 32 Raw 15 Raw 11 Raw 7 Raw 3 Y FIFO Raw 0 Raw 2 Raw 4 Raw 6 Raw 1 Raw ...

Page 174 - mode, three samples are unpacked from the FIFO and the

Raw Data Display Mode 4-29 Video Display Port SPRU629 In 8-bit raw ¾ mode, three samples are unpacked from the FIFO and the remaining byte is ignored. This is shown in Figure 4–30. Figure 4–30. 8-Bit Raw 3/4 FIFO Unpacking Big-Endian Unpacking Raw FIFO Raw 0 (R0) VDOUT[9–2] VCLKOUT 63 56 55 48 47 40...

Page 175 - Video Display Field and Frame Operation; Display Determination and Notification

Video Display Field and Frame Operation Video Display Port 4-30 SPRU629 4.7 Video Display Field and Frame Operation As a video source, the video port always outputs entire frames of data andtransmits continuous video control signals. Depending on the DMA structure,however, the video port may need to...

Page 176 - Table 4–4. Display Operation

Video Display Field and Frame Operation 4-31 Video Display Port SPRU629 Table 4–4. Display Operation VDCTL Bit CON FRAME DF2 DF1 Operation 0 0 0 0 Reserved 0 0 0 1 Noncontinuous field 1 display. Display only field 1. F1D is set afterfield 1 display and causes DCMPx to be set. The F1D bit must beclea...

Page 177 - Video Display Event Generation

Video Display Field and Frame Operation Video Display Port 4-32 SPRU629 Table 4–4. Display Operation (Continued) VDCTL Bit CON Operation DF1 DF2 FRAME 1 0 1 0 Continuous field 2 display. Display only field 2. F2D is set after field 2display and causes DCMPx to be set (DCMPx interrupt can be dis-able...

Page 178 - Display Line Boundary Conditions

Display Line Boundary Conditions 4-33 Video Display Port SPRU629 4.8 Display Line Boundary Conditions In order to simplify DMA transfers, FIFO doublewords do not contain data frommore than one display line. This means that a FIFO read must be performedwhenever 8-bytes have been output or when the li...

Page 179 - Figure 4–32. Display Line Boundary Example

Display Line Boundary Conditions Video Display Port 4-34 SPRU629 Figure 4–32. Display Line Boundary Example Y FIFO Cb FIFO Y 74 Y 76 Y 78 Y73 Y 75 Y 77 Y 79 VDOUT[9–2] VCLKOUT 63 5655 4847 4039 32 Y 5 Y 4 Y 7 Y 6 Y 69 Y 68 Y 71 Y 70 Y 77 Y 76 Cb 37 Cb 36 Cb 38 Little-Endian Packing Y 80 Y 82 Y 81 Y ...

Page 180 - Display Timing Examples; Interlaced BT.656 Timing Example; This section shows an example of BT.656 display output for a 704

Display Timing Examples 4-35 Video Display Port SPRU629 4.9 Display Timing Examples The following are examples of display output for several modes of operation. 4.9.1 Interlaced BT.656 Timing Example This section shows an example of BT.656 display output for a 704 × 408 inter- laced output image as ...

Page 181 - Figure 4–33. BT.656 Interlaced Display Horizontal Timing Example

Display T iming Examples 4-36 V ideo Display Port SPRU629 Figure 4–33. BT.656 Interlaced Display Horizontal Timing Example 720 721 722 723 735 736 799 800 855 856 857 0 1 7 8 9 10 710 711 712 718 719 720 721 703 703 703 703 703 703 703 703 703 703 703 703 0 1 2 702 703 703 703 703 703 703 n + 1 n FL...

Page 183 - Figure 4–34. BT.656 Interlaced Display Vertical Timing Example

Display Timing Examples Video Display Port 4-38 SPRU629 Figure 4–34. BT.656 Interlaced Display Vertical Timing Example ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ 5 FLCOUNT 525 240 240 ILCOUNT Field 1 Blanking Field 2 Blanking Field 1 Activ...

Page 184 - Interlaced Raw Display Example; VDTHRLD

Display Timing Examples 4-39 Video Display Port SPRU629 4.9.2 Interlaced Raw Display Example This section shows an example of raw display output for the same 704 × 408 interlaced image. The horizontal output timing is shown in Figure 4–35. This diagram assumesthat there is a two VCLK pipeline delay ...

Page 185 - Figure 4–35. Raw Interlaced Display Horizontal Timing Example

Display T iming Examples 4-40 V ideo Display Port SPRU629 Figure 4–35. Raw Interlaced Display Horizontal Timing Example É É É ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ É É É É É É É É É ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ É É É ÉÉ ÉÉ ÉÉ É É É ÉÉ ÉÉ ÉÉ É É É É É É É É É É É É FLCOUNT VDOUT[19–0] § VCLKOUT VCLKIN IPCOUNT VCTL1 (HBLNK)† § VCTL...

Page 187 - Figure 4–36. Raw Interlaced Display Vertical Timing Example

Display Timing Examples Video Display Port 4-42 SPRU629 Figure 4–36. Raw Interlaced Display Vertical Timing Example ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ 5 FLCOUNT 525 240 240 ILCOUNT Field 1 Blanking Field 2 Blanki...

Page 188 - Y/C Progressive Display Example; 16 progressive output image.

Display Timing Examples 4-43 Video Display Port SPRU629 4.9.3 Y/C Progressive Display Example This section shows an example of progressive display operation. The outputformat follows SMPTE 296M-2001 specifications for a 1280 × 720/60 system. The example is for a 1264 × 716 progressive output image. ...

Page 189 - Figure 4–37. Y/C Progressive Display Horizontal Timing Example

Display T iming Examples 4-44 V ideo Display Port SPRU629 Figure 4–37. Y/C Progressive Display Horizontal Timing Example ‡ ÉÉ ÉÉ ÉÉ VCLKIN FPCOUNT IPCOUNT VCTL1 (HBLNK)† § VCTL1 (HSYNC)† § VCLKOUT VDOUT[9–0] § VDOUT[19–0] § FLCOUNT n – 1 n + 1 n EAV Blanking Data SAV EAV Blanking Active Video Displa...

Page 191 - Figure 4–38. Y/C Progressive Display Vertical Timing Example

Display Timing Examples Video Display Port 4-46 SPRU629 Figure 4–38. Y/C Progressive Display Vertical Timing Example ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ 5 FLCOUNT 750 716 716 ILCOUNT Field 1 Blanking Field 1 Blanking Field 1 Active 4 3 2 1 716716716716 252627 716716716 745746747748749 71...

Page 192 - ) Set the frame size in VDFRMSZ. Set the number of lines per frame

Displaying Video in BT.656 or Y/C Mode 4-47 Video Display Port SPRU629 4.10 Displaying Video in BT.656 or Y/C Mode In order to display video in the BT.656 or Y/C format, the following steps areneeded: 1) Set the frame size in VDFRMSZ. Set the number of lines per frame (FRMHIGHT) and the number of pi...

Page 194 - Displaying Video in Raw Data Mode

Displaying Video in Raw Data Mode 4-49 Video Display Port SPRU629 22) If continuous display is enabled, the video port begins displaying again at the start of the next field or frame. If noncontinuous field 1 and field 2 orframe display is enabled, the next field or frame is displayed, during whicht...

Page 195 - 4) Configure a DMA to move data from table in the DSP memory to YDSTA

Displaying Video in Raw Data Mode Video Display Port 4-50 SPRU629 11) Set the horizontal synchronization in VDHSYNC. Specify the frame pixel counter value for a pixel where HSYNC gets asserted (HSYNCYSTART)and width of the HSYNC pulse (HSYNCSTOP) in frame pixel clocks. 12) Set the video display fiel...

Page 196 - Handling Underrun Condition of the Display FIFO

Displaying Video in Raw Data Mode 4-51 Video Display Port SPRU629 22) If continuous display is enabled, the video port begins displaying again at the start of the next field or frame. If noncontinuous field 1 and field 2 orframe display is enabled, the next field or frame is displayed, during whicht...

Page 197 - Video Display Registers; Table 4–5. Video Display Control Registers

Video Display Registers Video Display Port 4-52 SPRU629 4.12 Video Display Registers The registers for controlling the video display mode of operation are listed inTable 4–5. See the device-specific datasheet for the memory address of theseregisters. Table 4–5. Video Display Control Registers Acrony...

Page 206 - Figure 4–42. Video Display Horizontal Blanking Register (VDHBLNK)

Video Display Registers 4-61 Video Display Port SPRU629 4.12.4 Video Display Horizontal Blanking Register (VDHBLNK) The video display horizontal blanking register (VDHBLNK) controls the displayhorizontal blanking. The VDHBLNK is shown in Figure 4–42 and described inTable 4–9. Every time the frame pi...

Page 214 - Figure 4–47. Video Display Field 1 Image Offset Register (VDIMGOFF1)

Video Display Registers 4-69 Video Display Port SPRU629 Figure 4–47. Video Display Field 1 Image Offset Register (VDIMGOFF1) 31 30 28 27 16 NV Reserved IMGVOFF1 R/W-0 R-0 R/W-0 15 14 12 11 0 NH Reserved IMGHOFF1 R/W-0 R-0 R/W-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 4–...

Page 215 - Video Display Field 1 Image Size Register (VDIMGSZ1); Figure 4–48. Video Display Field 1 Image Size Register (VDIMGSZ1)

Video Display Registers Video Display Port 4-70 SPRU629 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) The video display field 1 image size register (VDIMGSZ1) defines the field 1image area and specifies the size of the displayed image within the active dis-play. The VDIMGSZ1 is shown ...

Page 216 - Video Display Field 2 Image Offset Register (VDIMGOFF2); Figure 4–49. Video Display Field 2 Image Offset Register (VDIMGOFF2)

Video Display Registers 4-71 Video Display Port SPRU629 4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2) The video display field 2 image offset register (VDIMGOFF2) defines thefield 2 image offset and specifies the starting location of the displayed imagerelative to the start of the a...

Page 217 - Table 4–16. Video Display Field 2 Image Offset Register (VDIMGOFF2)

Video Display Registers Video Display Port 4-72 SPRU629 Table 4–16. Video Display Field 2 Image Offset Register (VDIMGOFF2) Field Descriptions Description Bit field † symval † Value BT.656 and Y/C Mode Raw Data Mode 31 NV Negative vertical image offset enable bit. NONE 0 Not used. NEGOFF 1 Display i...

Page 218 - Video Display Field 2 Image Size Register (VDIMGSZ2); Figure 4–50. Video Display Field 2 Image Size Register (VDIMGSZ2)

Video Display Registers 4-73 Video Display Port SPRU629 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) The video display field 2 image size register (VDIMGSZ2) defines the field 2image area and specifies the size of the displayed image within the active dis-play. The VDIMGSZ2 is shown ...

Page 219 - Video Display Field 1 Timing Register (VDFLDT1)

Video Display Registers Video Display Port 4-74 SPRU629 4.12.13 Video Display Field 1 Timing Register (VDFLDT1) The video display field 1 timing register (VDFLDT1) sets the timing of the fieldidentification signal. The VDFLDT1 is shown in Figure 4–51 and described inTable 4–18. In raw data mode, the...

Page 220 - Video Display Field 2 Timing Register (VDFLDT2)

Video Display Registers 4-75 Video Display Port SPRU629 4.12.14 Video Display Field 2 Timing Register (VDFLDT2) The video display field 2 timing register (VDFLDT2) sets the timing of the fieldidentification signal. The VDFLDT2 is shown in Figure 4–52 and described inTable 4–19. In raw data mode, the...

Page 221 - Video Display Threshold Register (VDTHRLD); the VDTHRLDn value rounded up to the next doubleword

Video Display Registers Video Display Port 4-76 SPRU629 4.12.15 Video Display Threshold Register (VDTHRLD) The video display threshold register (VDTHRLD) sets the display FIFO thresh-old to determine when to load more display data. The VDTHRLD is shown inFigure 4–53 and described in Table 4–20. The ...

Page 223 - Video Display Horizontal Synchronization Register (VDHSYNC)

Video Display Registers Video Display Port 4-78 SPRU629 4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC) The video display horizontal synchronization register (VDHSYNC) controlsthe timing of the horizontal synchronization signal. The VDHSYNC is shownin Figure 4–54 and described in...

Page 228 - Video Display Counter Reload Register (VDRELOAD); Figure 4–59. Video Display Counter Reload Register (VDRELOAD)

Video Display Registers 4-83 Video Display Port SPRU629 4.12.21 Video Display Counter Reload Register (VDRELOAD) When external horizontal or vertical synchronization are used, the videodisplay counter reload register (VDRELOAD) determines what values areloaded into the counters when an external sync...

Page 229 - Video Display Display Event Register (VDDISPEVT); Figure 4–60. Video Display Display Event Register (VDDISPEVT)

Video Display Registers Video Display Port 4-84 SPRU629 4.12.22 Video Display Display Event Register (VDDISPEVT) The video display display event register (VDDISPEVT) is programmed withthe number of DMA events to be generated for display field 1 and field 2. TheVDDISPEVET is shown in Figure 4–60 and ...

Page 231 - Video Display Default Display Value Register (VDDEFVAL); and

Video Display Registers Video Display Port 4-86 SPRU629 4.12.24 Video Display Default Display Value Register (VDDEFVAL) The video display default display value register (VDDEFVAL) defines thedefault value to be output during the portion of the active video window that isnot part of the displayed ima...

Page 233 - Video Display Vertical Interrupt Register (VDVINT); Figure 4–64. Video Display Vertical Interrupt Register (VDVINT)

Video Display Registers Video Display Port 4-88 SPRU629 4.12.25 Video Display Vertical Interrupt Register (VDVINT) The video display vertical interrupt register (VDVINT) controls the generationof vertical interrupts in field 1 and field 2. The VDVINT is shown in Figure 4–64and described in Table 4–3...

Page 234 - Video Display Field Bit Register (VDFBIT)

Video Display Registers 4-89 Video Display Port SPRU629 4.12.26 Video Display Field Bit Register (VDFBIT) The video display field bit register (VDFBIT) controls the F bit value in the EAVand SAV timing control codes. The VDFBIT is shown in Figure 4–65 anddescribed in Table 4–31. The FBITCLR and FBIT...

Page 235 - Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)

Video Display Registers Video Display Port 4-90 SPRU629 4.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) The video display field 1 vertical blanking bit register (VDVBIT1) controls theV bit value in the EAV and SAV timing control codes for field 1. The VDVBIT1is shown in Figure...

Page 237 - Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)

Video Display Registers Video Display Port 4-92 SPRU629 4.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) The video display field 2 vertical blanking bit register (VDVBIT2) controls theV bit in the EAV and SAV timing control words for field 2. The VDVBIT2 isshown in Figure 4–67 ...

Page 239 - Video Display Registers Recommended Values; Table 4–34. Video Display Register Recommended Values; Register

Video Display Registers Recommended Values Video Display Port 4-94 SPRU629 4.13 Video Display Registers Recommended Values Sample recommended values (decimal) for video display registers for BT.656output are given in Table 4–34. Table 4–34. Video Display Register Recommended Values Register Field 52...

Page 240 - Table 4–34. Video Display Register Recommended Values (Continued)

Video Display Registers Recommended Values 4-95 Video Display Port SPRU629 Table 4–34. Video Display Register Recommended Values (Continued) Register 625/50 Value 525/60 Value Field VDVSYNS2 VSYNCXSTART2 360 † 360 † VSYNCYSTART2 266 † 313 † VDVSYNE2 VSYNCXSTOP2 360 † 720 † VSYNCYSTOP2 269 † 316 † VD...

Page 241 - Video Display FIFO Registers; Table 4–35. Video Display FIFO Registers; Table 4–36. Video Display FIFO Registers Function

Video Display FIFO Registers Video Display Port 4-96 SPRU629 4.14 Video Display FIFO Registers The display FIFO mapping registers are listed in Table 4–35. These registersprovide DMA write access to the display FIFOs. These pseudo-registersshould be mapped into DSP memory space rather than configura...

Page 242 - GPIO Registers; Chapter 5

5-1 General Purpose I/O Operation Signals not used for video display or video capture can be used as general-purpose input/output (GPIO) signals. Topic Page 5.1 GPIO Registers 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 5

Page 243 - Table 5–1. Video Port Registers

GPIO Registers General Purpose I/O Operation 5-2 SPRU629 5.1 GPIO Registers The GPIO register set includes required registers such as peripheral identifi-cation and emulation control. The GPIO registers are listed in Table 5–1. Seethe device-specific datasheet for the memory address of these registe...

Page 244 - Video Port Peripheral Identification Register (VPPID); Figure 5–1. Video Port Peripheral Identification Register (VPPID)

GPIO Registers 5-3 General Purpose I/O Operation SPRU629 5.1.1 Video Port Peripheral Identification Register (VPPID) The video port peripheral identification register (VPPID) is a read-only registerused to store information about the peripheral. The VPPID is shown inFigure 5–1 and described in Table...

Page 245 - Video Port Peripheral Control Register (PCR)

GPIO Registers General Purpose I/O Operation 5-4 SPRU629 5.1.2 Video Port Peripheral Control Register (PCR) The video port peripheral control register (PCR) determines operation duringemulation. The video port peripheral control register is shown in Figure 5–2and described in Table 5–3. Normal opera...

Page 252 - Video Port Pin Data Input Register (PDIN)

GPIO Registers 5-11 General Purpose I/O Operation SPRU629 5.1.5 Video Port Pin Data Input Register (PDIN) The read-only video port pin data input register (PDIN) is shown in Figure 5–5and described in Table 5–6. PDIN reflects the state of the video port pins.When read, PDIN returns the value from th...

Page 254 - Video Port Pin Data Output Register (PDOUT); PDOUT has these aliases:

GPIO Registers 5-13 General Purpose I/O Operation SPRU629 5.1.6 Video Port Pin Data Output Register (PDOUT) The video port pin data output register (PDOUT) is shown in Figure 5–6 anddescribed in Table 5–7. The bits of PDOUT determine the value driven on thecorresponding GPIO pin, if the pin is confi...

Page 258 - Video Port Pin Data Clear Register (PDCLR)

GPIO Registers 5-17 General Purpose I/O Operation SPRU629 5.1.8 Video Port Pin Data Clear Register (PDCLR) The video port pin data clear register (PDCLR) is shown in Figure 5–8 anddescribed in Table 5–9. PDCLR is an alias of the video port pin data output reg-ister (PDOUT) for writes only and provid...

Page 260 - Video Port Pin Interrupt Enable Register (PIEN)

GPIO Registers 5-19 General Purpose I/O Operation SPRU629 5.1.9 Video Port Pin Interrupt Enable Register (PIEN) The video port pin interrupt enable register (PIEN) is shown in Figure 5–9 anddescribed in Table 5–10. The GPIOs can be used to generate DSP interruptsor DMA events. The PIEN selects which...

Page 262 - Figure 5–10. Video Port Pin Interrupt Polarity Register (PIPOL)

GPIO Registers 5-21 General Purpose I/O Operation SPRU629 5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) The video port pin interrupt polarity register (PIPOL) is shown in Figure 5–10and described in Table 5–11. The PIPOL determines the GPIO pin signalpolarity that generates an interrupt....

Page 264 - Figure 5–11. Video Port Pin Interrupt Status Register (PISTAT)

GPIO Registers 5-23 General Purpose I/O Operation SPRU629 5.1.11 Video Port Pin Interrupt Status Register (PISTAT) The video port pin interrupt status register (PISTAT) is shown in Figure 5–11and described in Table 5–12. PISTAT is a read-only register that indicates theGPIO pin that has a pending in...

Page 266 - Figure 5–12. Video Port Pin Interrupt Clear Register (PICLR)

GPIO Registers 5-25 General Purpose I/O Operation SPRU629 5.1.12 Video Port Pin Interrupt Clear Register (PICLR) The video port pin interrupt clear register (PICLR) is shown in Figure 5–12 anddescribed in Table 5–13. PICLR is an alias of the video port pin interrupt statusregister (PISTAT) for write...

Page 268 - Chapter 6

6-1 VCXO Interpolated Control Port SPRU629 VCXO Interpolated Control Port This chapter provides an overview of the VCXO interpolated control (VIC) port. Topic Page 6.1 Overview 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Interface...

Page 269 - The VIC port supports following features:; Figure 6–1. TSI System Block Diagram

Overview VCXO Interpolated Control Port 6-2 SPRU629 6.1 Overview The VCXO interpolated control (VIC) port provides single-bit interpolatedVCXO control with resolution from 9 bits to up to 16 bits. The frequency of inter-polation is dependent on the resolution needed. When the video port is used in t...

Page 270 - Interface; Table 6–1. VIC Port Interface Signals; VIC Port Signal; Operational Details

Interface 6-3 VCXO Interpolated Control Port SPRU629 6.2 Interface The pin list for VIC port is shown in Table 6–1 (pins are 3.3V I/Os). Table 6–1. VIC Port Interface Signals VIC Port Signal Direction Description VCTL Output VCXO control STCLK Input System time clock 6.3 Operational Details Synchron...

Page 271 - kf; Equation 6–2. Relationship of Frequency Multiplier to Precision; Table 6–2 gives some k and R values for different; Table 6–2. Example Values for Interpolation Rate

Operational Details VCXO Interpolated Control Port 6-4 SPRU629 Any time a packet with a PCR is received, the timestamp for that packet iscompared with the PCR value in software. A PLL is implemented in softwareto synchronize the STCLK with the system time clock. The DSP updates theVIC input register...

Page 272 - Enabling VIC Port; Perform the following steps to enable the VIC port.; VIC Port Registers; Table 6–3. VIC Port Registers

Enabling VIC Port 6-5 VCXO Interpolated Control Port SPRU629 6.4 Enabling VIC Port Perform the following steps to enable the VIC port. 1) Clear the GO bit in the VIC control register (VICCTL) to 0. 2) Set the PRECISION bits in VICCTL to the desired precision. 3) Set the VIC clock divider register (V...

Page 273 - Table 6–4. VIC Control Register (VICCTL) Field Descriptions

VIC Port Registers VCXO Interpolated Control Port 6-6 SPRU629 6.5.1 VIC Control Register (VICCTL) The VIC control register (VICCTL) is shown in Figure 6–3 and described inTable 6–4. Figure 6–3. VIC Control Register (VICCTL) 31 16 Reserved R-0 15 4 3 1 0 Reserved PRECISION GO R-0 R/W-0 R/W-0 Legend: ...

Page 276 - Divider; Table 6–6. VIC Clock Divider Register (VICDIV) Field Descriptions

VIC Port Registers 6-9 VCXO Interpolated Control Port SPRU629 6.5.3 VIC Clock Divider Register (VICDIV) The VIC clock divider register (VICDIV) defines the clock divider for the VICinterpolation frequency. The VIC interpolation frequency is obtained by divid-ing the module clock. The divider value w...

Page 277 - Example 1: Noncontinuous Frame Capture for 525/60 Format; Appendix A

A-1 Appendix A Video Port Configuration Examples This appendix describes how to configure the video port in different modeswith the help of examples. All examples in this appendix use the video portChip Support Library (CSL). Topic Page A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format A-...

Page 297 - Index

Index Index-1 SPRU629 Index A ancillary data capture 3-31 ancillary data display 4-25 architecture 1-3 ATC bit in TSISTCMPL 3-78 in TSISTCMPM 3-79 ATCM bit in TSISTMSKL 3-80 in TSISTMSKM 3-81 B BLKCAP bit in VCACTL 3-53 in VCBCTL 3-68 BLKDIS bit 4-55 block diagrams 16/20-bit raw video capture FIFO c...

Texas Instruments TMS320C64x DSP - Manual

Table of Contents:

Summary

Other Texas Instruments Models