Texas Instruments TMS320C645X - Manual
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Table of Contents:
- Page 3 – Contents
- Page 10 – RapidIO Documents and Links
- Page 13 – Read This First; About This Manual; TMS320C6455 Technical Reference (literature number; Trademarks
- Page 14 – Overview; General RapidIO System; RapidIO Architectural Hierarchy; Figure 1
- Page 15 – Figure 1. RapidIO Architectural Hierarchy
- Page 16 – RapidIO Interconnect Architecture; Figure 2; Figure 2. RapidIO Interconnect Architecture
- Page 17 – RapidIO Feature Support in SRIO; Figure 3. Serial RapidIO Device to Device Interface Diagrams
- Page 18 – Features Not Supported:; Compliance with the Global Shared Memory specification (GSM); Document
- Page 19 – SRIO Functional Description; Peripheral Data Flow; Figure 4
- Page 20 – Figure 4. SRIO Peripheral Block Diagram; Operation Sequence
- Page 21 – Figure 5; Figure 5. Operation Sequence; Example Packet – Streaming Write
- Page 22 – Control Symbols; Figure 7. Serial RapidIO Control Symbol Format
- Page 23 – details the handling of such packets.; Ftype; Packet type definition:
- Page 24 – Table 3; Table 3. Pin Description; Figure 8
- Page 25 – Figure 8. SRIO Conceptual Block Diagram
- Page 26 – SERDES and its Configurations; % operation. This provides for excellent power; Bit
- Page 27 – Table 5. Line Rate versus PLL Output Clock Frequency; Table 6; Table 6. RATE Bit Effects
- Page 28 – Here is the frequency range versus MPY:; Table 7. Frequency Range versus MPY; Enabling the Receiver
- Page 30 – Low Freq Gain; Enabling the Transmitter
- Page 32 – SERDES Configuration Example; DirectIO
- Page 33 – Table 13. Control/Command Register Field Mapping; Control/Command Register
- Page 34 – Table 14. Status Fields; Status Field
- Page 35 – Figure 11. LSU Registers Timing
- Page 36 – Detailed Data Path Description
- Page 37 – TX Operation
- Page 39 – RX Operation
- Page 40 – So the general flow is as follows:; Message Passing; The following rules exist for all CPPI traffic:
- Page 41 – Figure 14. CPPI RX Scheme for RapidIO; shows the packet; Figure 15. Message Request Packet
- Page 43 – and
- Page 44 – . There is an ICSR bit for each supported queue, as shown in; Figure 19. RX Buffer Descriptor Fields
- Page 45 – Table 17. RX Buffer Descriptor Field Descriptions; Field
- Page 46 – Table 17. RX Buffer Descriptor Field Descriptions (continued); . This scenario is similar
- Page 47 – Figure 20. RX CPPI Mode Explanation
- Page 48 – Teardown of an Rx queue causes the following actions:; Figure 21. CPPI Boundary Diagram
- Page 49 – Figure 22. TX Buffer Descriptor Fields
- Page 52 – Name
- Page 54 – No new messages will be sent
- Page 55 – Message Passing Software Requirements
- Page 56 – Initialization Example
- Page 57 – Figure 24. RX Buffer Descriptor
- Page 58 – Figure 25. TX Buffer Descriptor
- Page 59 – Doorbell; , is used by a processing element to send a very short message to; Figure 26. Doorbell Operation
- Page 60 – Congestion Control; Table 1
- Page 62 – Figure 28. Transmit Source Flow Control Masks
- Page 63 – Endianness; Figure 6; Figure 29. Configuration Bus Example
- Page 64 – Figure 30. DMA Example
- Page 65 – Reset Summary
- Page 66 – Table 24. Enable and Enable Status Bit Field Descriptions
- Page 68 – Software Shutdown Details; Emulation
- Page 69 – Table 25. Emulation Control Signals; Enabling the SRIO Peripherals
- Page 70 – PLL, Ports, Device ID and Data Rate Initializations; Peripheral Initializations; Set Device ID Registers
- Page 71 – Assert the PEREN bit to enable logical layer data flow
- Page 72 – Bootload Capability; Configuration; Figure 40. Bootload Operation; Bootload Data Movement
- Page 73 – Logical/Transport Error Handling and Logging; illustrates the detectable errors.; Figure 41. Detectable Errors; Logical Layer Error Detect CSR:
- Page 74 – CPU Interrupts; Interrupt Conditions; The following interrupts are supported by the RIO peripheral.; Figure 42. RapidIO DOORBELL Packet for Interrupt Use
- Page 75 – Interrupt Condition Control Registers
- Page 76 – Table 26. Interrupt Source Configuration Options; Figure 43. DOORBELL0 Interrupt Registers for Direct I/O Transfers
- Page 77 – Figure 45. DOORBELL2 Interrupt Registers for Direct I/O Transfers; Figure 46. DOORBELL3 Interrupt Registers for Direct I/O Transfers
- Page 78 – Figure 47. RX_CPPI Interrupts Using Messaging Mode Data Transfers; Figure 48. TX _CPPI Interrupts Using Messaging Mode Data Transfers
- Page 79 – Figure 49. LSU Load/Store Module Interrupts
- Page 81 – Table 27. Interrupt Condition Routing Options; Figure 51. Doorbell 0 Interrupt Condition Routing Registers
- Page 83 – Interrupt Status Decode Registers
- Page 84 – Figure 54. Sharing of ISDR Bits; illustrates the decode routing.
- Page 85 – Figure 56. INTDSTn_Decode Interrupt Status Decode Register
- Page 86 – Interrupt Handling
- Page 88 – Introduction; SRIO Registers; manual for the memory address of these registers.; Offset
- Page 100 – Table 30. Peripheral Control Register (PCR) Field Descriptions
- Page 110 – There are four of these registers, to support four ports.
- Page 112 – Descriptions
- Page 115 – Amplitude Reduction
- Page 117 – Each of the four doorbells is supported by a register of this type.
- Page 127 – DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR)
- Page 133 – LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0)
- Page 134 – LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1)
- Page 135 – LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2)
- Page 136 – LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3)
- Page 140 – There are eight of these registers.
- Page 142 – There are four of these registers, one for each LSU.
- Page 150 – There are sixteen of these registers.
- Page 155 – There are eight registers of this type. See
- Page 183 – Each of the four ports is supported by a register of this type.
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TMS320C645x Serial Rapid IO (SRIO)
User's Guide
Literature Number: SPRU976
March 2006
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Summary
Page 3 - Contents
Contents Preface .............................................................................................................................. 13 1 Overview .................................................................................................................. 14 1.1 General RapidIO Syst...
Page 10 - RapidIO Documents and Links
List of Tables 1 RapidIO Documents and Links ........................................................................................... 18 2 Packet Type ................................................................................................................. 23 3 Pin Description ..............
Page 13 - Read This First; About This Manual; TMS320C6455 Technical Reference (literature number; Trademarks
Preface SPRU976 – March 2006 Read This First About This Manual This document describes the Serial Rapid IO (SRIO) on the TMS320C645x devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 4...
