Page 6 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; the TMS320C6000TM DSPs and includes application program examples.
Preface SPRUGK7A – March 2009 – Revised July 2010 Read This First About This Manual This guide describes the host port interface (HPI) on the TMS320C6457 digital signal processors (DSPs).The HPI enables an external host processor (host) to directly access the internal or external memory ofthe DSP us...
Page 7 - Introduction to the HPI; Figure 1; Figure 1. HPI Position in the Host-DSP System
HPID R/W FIFOs HPIA Increment HPIC Access type HD[31:0]/HD[15:0] HDS1, HDS2 HR/W HAS HCNTL0 HCNTL1 (optional) HINT HRDY HPI Host Data Address ALE R/W IRQ Ready HCS Chip select DSP HPI DMA logic HHWIL (if needed) Data strobes Switched central resource C64x+ megamodule External memory I/F Other periph...
Page 8 - Section 2; Summary of the HPI Registers; Table 1
Introduction to the HPI www.ti.com The HPI uses multiplexed operation, meaning the data bus carries both address and data. When the hostdrives an address on the bus, the address is stored in the address register (HPIA) in the HPI, so that thebus can then be used for data. The HPI supports two interf...
Page 9 - Table 1. Summary of HPI Registers; Summary of the HPI Signals; Table 2; CAUTION
www.ti.com Introduction to the HPI Table 1. Summary of HPI Registers Host Access CPU Access Read/Write Access Requirements Read/Write Offset Register Description Permissions Permissions Address PWREMU_MGMT Power and Emulation None - Read/Write 04h Management Register HPIC Host Port Interface Control...
Page 11 - Using the Address Registers
www.ti.com Using the Address Registers 2 Using the Address Registers The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for writeoperations (HPIAW). These roles are unchanging from the position of the HPI DMA logic. HPI DMA logiccollects the address from HPIAR whe...
Page 12 - HPI Operation; Host-HPI Signal Connections
Address or I/O Read/Write Chip select Data strobe A Data/address Interrupt Ready HCNTL[1:0] HR/W HCS HDS1 HDS2 HD[31:0] HINT HRDY HPI Host Address latch enable HAS No connect HHWIL Logic high 2 32 DSP HPI Operation www.ti.com 3 HPI Operation 3.1 Host-HPI Signal Connections Figure 2 and Figure 3 show...
Page 13 - in the 32-Bit Multiplexed Mode; in the 16-Bit Multiplexed Mode
Address or I/O Read/Write Chip select Data strobe A Data/address Interrupt Ready HCNTL[1:0] HR/W HCS HDS1 HDS2 HD[31:0] HINT HRDY HPI Host Logic high HAS No connect HHWIL Logic high 2 32 DSP Read/Write Chip select Data strobe A Data/address Interrupt Ready HCNTL[1:0] HR/W HCS HDS1 HDS2 HD[15:0] HINT...
Page 14 - Multiplexed Mode; HPI Configuration and Data Flow; deassertion of HRDY until HPIRST is cleared.
Read/Write Chip select Data strobe A Data Interrupt Ready HCNTL[1:0] HR/W HCS HDS1 HDS2 HD[15:0] HINT HRDY HPI DSP Host HAS HHWIL Logic high Logic high Address or I/O HD[31:16] No connect 2 16 16 HPI Operation www.ti.com Figure 5. Example of Host-DSP Signal Connections When the HAS Signal is Tied Hi...
Page 15 - As illustrated in; Figure 6. HPI Strobe and Select Logic; Table 3; Table 3. Options for Connecting Host and HPI Data Strobe Pins
HDS1 HDS2 HCS HRDY InternalHSTRB InternalHRDY www.ti.com HPI Operation If the host wants to read data from the DSP internal/external memory, the HPI DMA logic reads thememory address from HPIAR and retrieves the data from the addressed memory location. When the datahas been placed in HPID, the HPI d...
Page 16 - Table 4; Table 5. Cycle Types Selectable With the HCNTL and HR/W Signals
HPI Operation www.ti.com 3.4 HCNTL[1:0] and HR/W: Indicating the Cycle Type The cycle type consists of:• The access type selected by the host by driving the appropriate levels on the HCNTL[1:0] pins of theHPI. Table 4 describes the four available access types. • The transfer direction that the host ...
Page 17 - and; HAS: Forcing the HPI to Latch Control Information Early; Figure 2
www.ti.com HPI Operation 3.5 HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed Mode In the 16-bit multiplexed mode, each host cycle consists of two consecutive halfword transfers. For eachtransfer, the host must specify the cycle type with HCNTL[1:0] and HR/W, and the host must...
Page 18 - Figure 7. 16-Bit Multiplexed Mode Host Read Cycle Using HAS
Data 2 Data 1 HCS HAS HSTRB HR/W HCNTL[1:0] HD[15:0] HRDY A HHWIL Internal HPI latches control information Host latches data HPI latches control information Host latches data HPI Operation www.ti.com Figure 7. 16-Bit Multiplexed Mode Host Read Cycle Using HAS A Depending on the type of write operati...
Page 19 - Figure 8. 16-Bit Multiplexed Mode Host Write Cycle Using HAS
HCS HAS HSTRB HR/W HCNTL[1:0] HRDY A HHWIL Data 1 Data 2 HD[15:0] Internal HPI latches control information HPI latches data HPI latches control information HPI latches data www.ti.com HPI Operation Figure 8. 16-Bit Multiplexed Mode Host Write Cycle Using HAS A Depending on the type of write operatio...
Page 20 - Performing a Multiplexed Access Without HAS; Figure 3; Figure 9. 16-Bit Multiplexed Mode Host Read Cycle With HAS Tied High
Data 2 Data 1 HCS HSTRB HR/W HCNTL[1:0] HD[15:0] HRDY A HHWIL Internal HPI latches control information Host latches data HPI latches control information Host latches data HPI Operation www.ti.com 3.7 Performing a Multiplexed Access Without HAS The HAS signal is not required when the host processor h...
Page 22 - Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode; has the HAS signal tied high, this; Section 4; Section 6
Data 1 HCS HSTRB HR/W HCNTL[1:0] HD[15:0] HRDY HHWIL Internal Valid 00 Valid HPI Operation www.ti.com 3.8 Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode In 16-bit multiplexed mode, the lower 16 bits of the HPIC registers are duplicated on the upper 16 bitsduring HPIC host accesses. Theref...
Page 23 - HRDY Behavior During 16-Bit Multiplexed Read Operations
1st halfword 00 or 10 00 or 10 2nd halfword Internal HD[15:0] HRDY HHWIL HR/W HCNTL[1:0] HCS HSTRB HCS HCNTL[1:0] HR/W HHWIL Internal HSTRB HD[15:0] HRDY 1st halfword 2nd halfword 1st halfword 2nd halfword 11 11 10 10 HPIA write HPID read HCS Internal HRDY HD[15:0] HR/W HCNTL[1:0] HHWIL 10 10 01 01 ...
Page 24 - HRDY Behavior During 16-Bit Multiplexed Write Operations; HPIC write cycle does not cause HRDY to go high.
1st halfword 2nd halfword 00 00 Internal HD[15:0] HRDY HHWIL HR/W HCNTL[1:0] HCS HSTRB 10 10 11 11 1st halfword 2nd halfword 2nd halfword 1st halfword Internal HSTRB HD[15:0] HRDY HHWIL HR/W HCNTL[1:0] HCS HPIA write HPID write 10 10 01 01 01 1st halfword 2nd halfword 1st halfword 2nd halfword 1st h...
Page 25 - HRDY Behavior During 32-Bit Multiplexed Read Operations; access for 32-bit multiplexed HPI operation.
10 10 01 01 01 1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword Internal HSTRB HD[15:0] HRDY HHWIL HR/W HCNTL[1:0] HCS HPIA write HPID+ writes 00 or 10 HCNTL[1:0] HD[31:0] HRDY HR/W Internal HSTRB HCS www.ti.com HPI Operation Figure 18. HRDY Behavior During a Data Write Operation in ...
Page 26 - HRDY Behavior During 32-Bit Multiplexed Write Operations; an HPIC write access does not cause HRDY to become active.
11 10 HPIA Write HPID Read HCNTL[1:0] HD[31:0] HRDY HR/W Internal HSTRB HCS 10 01 01 01 HPIA Write HPID+ Reads HD[31:0] HRDY HCS A HCNTL[1:0] HR/W Internal HSTRB HPI Operation www.ti.com Figure 20. HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write Cycle Fo...
Page 29 - Software Handshaking Using the HPI Ready (HRDY) Bit; Polling the HRDY Bit
www.ti.com Software Handshaking Using the HPI Ready (HRDY) Bit 4 Software Handshaking Using the HPI Ready (HRDY) Bit In addition to the HRDY output signal, the HPI contains an HRDY bit in the control register (HPIC). This bitis useful for software polling when the host does not have an input pin to ...
Page 30 - Interrupts Between the Host and the CPU; and detailed following the figure.
DSPINT=0 DSPINT=1 CPU writes 1to DSPINT bit Interrupt pending Host writes 0 to DSPINT bit No interrupt/ interrupt cleared Host writes 0 or 1 to DSPINT bit CPU writes 0to DSPINT bit CPU writes 0 or 1to DSPINT bit Host writes 1 to DSPINT bit (interrupt generated to CPU) (A) Interrupts Between the Host...
Page 32 - FIFOs and Bursting; Figure 28. FIFOs in the HPI; Read Bursting
Write FIFO control logic Host write pointer HPI DMAread pointer Write FIFO Host writes Read FIFO reads Host control logic Read FIFO Host read pointer HPI DMAwrite pointer HPI DMA logic Switched central Burst writes reads Burst resource DSP internal/external memory FIFOs and Bursting www.ti.com 6 FIF...
Page 33 - Write Bursting
www.ti.com FIFOs and Bursting If the host initiates an HPID read cycle with autoincrementing, the HPI DMA logic performs two 4-wordburst operations to fill the read FIFO. The host is initially held off by the deassertion of the HRDY signaluntil data is available to be read from the read FIFO. Once d...
Page 34 - FIFO Flush Conditions; Read FIFO flush conditions:; FIFO Behavior When a Hardware Reset or Software Reset Occurs
FIFOs and Bursting www.ti.com 6.3 FIFO Flush Conditions When specific conditions occur within the HPI, the read or write FIFO must be flushed to prevent thereading of stale data from the FIFOs. When a read FIFO flush condition occurs, all current host accessesand direct memory accesses (DMAs) to the...
Page 35 - Emulation and Reset Considerations; Emulation Modes; When the DSP is reset:
www.ti.com Emulation and Reset Considerations 7 Emulation and Reset Considerations 7.1 Emulation Modes The FREE and SOFT bits of the power and emulation management register (PWREMU_MGMT)determine the response of the HPI to an emulation suspend condition. If FREE = 1, the HPI is notaffected, and the ...
Page 36 - HPI Registers; Introduction; Table 6
HPI Registers www.ti.com 8 HPI Registers 8.1 Introduction Table 6 lists the memory-mapped registers for the Host Port Interface (HPI). See the device-specific data manual for the memory address of these registers. Table 6. Host Port Interface (HPI) Registers Offset Acronym Register Description See 0...
Page 37 - The power management and emulation register is shown in
www.ti.com HPI Registers 8.2 Power and Emulation Management Register (PWREMU_MGMT) The power management and emulation register is shown in Figure 29 and described in Table 7 . Figure 29. Power and Emulation Management Register (PWREMU_MGMT) 31-16 Reserved R-0 15-2 1 0 Reserved SOFT FREE R-0 R/W-0 R/...
Page 38 - Host Port Interface Control Register (HPIC); Table 8; Figure 30. Host Access Permissions
HPI Registers www.ti.com 8.3 Host Port Interface Control Register (HPIC) The HPIC register stores control and status bits used to configure and operate the HPI peripheral. The bitpositions of the HPIC register and their functions are illustrated in Table 8 . In 16-bit multiplexed mode, the lower 16 ...
Page 40 - Host Port Interface Address Registers (HPIAW and HPIAR)
HPI Registers www.ti.com 8.4 Host Port Interface Address Registers (HPIAW and HPIAR) There are two 32-bit HPIA registers: HPIAW for write operations and HPIAR for read operations. The HPIcan be configured such that HPIAW and HPIAR act as a single 32-bit HPIA (single-HPIA mode) or as twoseparate 32-b...
Page 41 - As shown in
www.ti.com HPI Registers 8.5 Data Register (HPID) The 32-bit register HPID provides the data path between the host and the HPI DMA logic. During a hostwrite cycle, the host fills HPID with 32 bits, and then the HPI DMA logic transfers the 32-bit value to theinternal memory of the DSP. During a host ...
Page 42 - Appendix A Revision History
www.ti.com Appendix A Revision History This revision history highlights the technical changes made to the document in this revision. Table 11. TMS320C6457 HPI Revision History See Additions/Modifications/Deletions Table 6 Modified table 42 Revision History SPRUGK7A – March 2009 – Revised July 2010 C...
Page 43 - IMPORTANT NOTICE
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...
