Texas Instruments TMS320C6201 - Manual

Table of Contents:

• Page 2 – Contents; Introduction
• Page 3 – Documentation Support
• Page 4 – Quality and Reliability Conditions; TMX Definition
• Page 5 – Revision Identification; Cxx–YMLLLLS; DSP; Table 1. Lot Trace Number Names
• Page 6 – Table 2. Timing Requirements for Interrupt Response Cycles
• Page 8 – Issues When Pausing at a Block Boundary; If pausing the DMA channel in software, do the following to restart:
• Page 9 – The following conditions cause DMA to freeze:
• Page 10 – This occurs when the following is true:
• Page 11 – Cache During Emulation With Extremely Slow External Memory; B is currently located in cache
• Page 12 – EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz; Figure 4. Write Example – Desired Behavior
• Page 13 – EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued); is reduced by; Figure 6. Read Example – Desired Behavior
• Page 14 – Alternate Workaround:; CPU: L2-unit Long Instructions Corrupted During Interrupt; This bug will not affect:; Resolution; Revision 3.1 of silicon will correct this problem.
• Page 19 – Leave RBTR8 set to the default of 0.
• Page 20 – Law Companding Value; -Law/A-Law companding hardware produces an incorrectly expanded; False Cache Hit – Extremely Rare; EMIF: HOLD Feature Improvement on Revision 3; If NOHOLD is set and a HOLD request comes in, the C62x
• Page 21 – EMIF: HOLD Request Causes Problems With SDRAM Refresh; still owns the; DMA Priority Ignored by PBUS
• Page 23 – PMEMC: Branch from External to Internal; CPU is executing from external memory; DMA: DMA Data Block Corrupted After Start Zero Transfer Count; Make sure the transfer count is not near zero when starting the DMA.
• Page 24 – Program Fetch: Cache Modes Not Functional; Use internal program memory in mapped mode.; Reinitialization
• Page 25 – Sequenced Wrong; A load and store are in the same execute packet and either; EMIF: Reserved Fields Have Incorrect Values
• Page 26 – McBSP New Block Interrupt Does Not Occur for Start of Block 0; LDW
• Page 28 – EMIF: Data Setup Times; Increase the refresh period.; To access documentation on the web site:; Highest Performance DSP Platform” and click on “TMS320C62x DSP
• Page 29 – IMPORTANT NOTICE