Page 3 - Data Manual; Advanced RF Cellular Telephone Interface Circuit
TCM4300 Data Manual Advanced RF Cellular Telephone Interface Circuit (ARCTIC ) SLWS010F October 1996 Printed on Recycled Paper
Page 4 - IMPORTANT NOTICE; Copyright
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue anysemiconductor product or service without notice, and advises its customers to obtain the latestversion of relevant information to verify, before placing orders, that the information being ...
Page 5 - Contents; Introduction
iii Contents Section Title Page 1 Introduction 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6 - Principles of Operation
iv 3.9 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-Bit Write Cycle) 3–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) 3–10 . . . . . . . . . 3.11 Switching Charact...
Page 7 - List of Illustrations
v List of Illustrations Figure Title Page 3–1 MCLKOUT Timing Diagram 3–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Microcontroller Interface Timing Requirements(Mitsubishi Configuration Read Cycle, MTS [1:0] = 10) 3–2 . . . . . . . . . . . . . . . ...
Page 8 - List of Tables; DD
vi List of Tables Table Title Page 4–1 TCM4300 Receive Channel Control Signals 4–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 RXIP, RXIN, RXQP, and RXQN Inputs (AV DD = 3 V, 4.5 V, 5 V) 4–2 . . . . . . . . . . . . . . 4–3 Receive (RX) Channel Frequency Response (FM Input in An...
Page 9 - Introduction; Features
1–1 1 Introduction Texas Instruments (TI ) TCM4300 IS-54B advanced RF cellular telephone interface circuit (ARCTIC ) provides a baseband interface between the digital signal processor (DSP), the microcontroller, and the RFmodulator/demodulator in a dual-mode IS-54B cellular telephone. See the TC...
Page 10 - TCM4300 Functional Block Diagram
1–2 1.2 TCM4300 Functional Block Diagram TXQP TXQN RSSI BAT A/D OUT1 FMRXEN IQRXEN TXEN SCEN SYNOL TXONIND SYNCLK SYNDTA SYNLE [2:0] LCDCONTR D/A TXIP TXIN FM RXQP RXQN A/D RXIP RXIN A/D PWRCONT AFC AGC PAEN MCCLKCSCLKCMCLK MCLKIN XTAL MCLKOUT CINTDINT DWBDINT MWBDFINT REFCAP VHR Vref RBIAS VCM RSOU...
Page 11 - Pin Assignments
1–3 1.3 Pin Assignments 12345678910111213141516171819202122232425 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75747372717069686766656463626160595857565554535251 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 DSPA0DSPA1 DSPA3 DSPRWDSPSTRBLMC...
Page 12 - Terminal Functions
1–4 1.4 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AFC 11 O Automatic frequency control. The AFC DAC output provides the means to adjustsystem temperature-compensated reference oscillator (TCXO). AGC 10 O Automatic gain control. The AGC digital-to-analog converter (DAC) out...
Page 16 - Electrical Specifications; Dissipation Rating Table
2–1 2 Electrical Specifications This section lists the electrical specifications, the absolute maximum ratings, the recommended operatingconditions and operating characteristics for the TCM4300 Advanced RF Cellular Telephone InterfaceCircuit. 2.1 Absolute Maximum Ratings Over Operating Free-Air Temp...
Page 17 - Recommended Operating Conditions; Power Consumption
2–2 2.3 Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage, DVDD 3 5.5 V High-level input voltage, VIH Digital 0.7 DVDD DVDD+0.3 V Low-level input voltage, VIL Digital 0 0.3 DVDD V High-level output voltage, VOH Digital 0.7 DVDD DVDD V Low-level output voltage, VOL Digital 0 0.5 V High...
Page 18 - Terminal Impedance
2–3 2.4.3 Terminal Impedance FUNCTION MIN TYP† MAX UNIT Receive channel input impedance (single ended), RXIP/N and RXQP/N 40 70 k Ω Transmit channel output impedance (single ended), TXIP/N and TXQP/N 40 50 100 Ω FM input impedance, WBD 25 200 k Ω MCLKOUT impedance MCLKOUT at 3.3 V 240 Ω MCLKOUT impe...
Page 24 - Parameter Measurement Information; MCLKOUT Timing Requirements (see Figure 3–1 and Note 1); Figure 3–1. MCLKOUT Timing Diagram
3–1 3 Parameter Measurement Information This section contains the timing waveforms and parameter values for MCLKOUT and severalmicrocontroller interface configurations possible when using the TCM4300. The timing parameters arecontained in Section 3.1 through Section 3.11. The timing waveforms are sh...
Page 25 - Figure 3–2. Microcontroller Interface Timing Requirements
3–2 3.2 TCM4300 to Microcontroller Interface Timing Requirements (MitsubishiRead Cycle) (see Figure 3–2 and Note 2) PARAMETER ALTERNATE SYMBOL MIN MAX UNIT tsu(R/W) Setup time, read/write MCRW stable before falling edge ofstrobe MCDS TRW(SU) 0 ns th(R/W) Hold time, read/write MCRW stable after risin...
Page 26 - Figure 3–3. Microcontroller Interface Timing Requirements
3–3 3.3 TCM4300 to Microcontroller Interface Timing Requirements (MitsubishiWrite Cycle) (see Figure 3–3 and Note 2) PARAMETER ALTERNATE SYMBOL MIN MAX UNIT tsu(R/W) Setup time, read/write MCRW stable before falling edge ofstrobe MCDS TRW(SU) 0 ns th(R/W) Hold time, read/write MCRW stable after risi...
Page 27 - Figure 3–4. Microcontroller Interface Timing Requirements
3–4 3.4 TCM4300 to Microcontroller Interface Timing Requirements (Intel ReadCycle) (see Figure 3–4 and Note 3) PARAMETER ALTERNATE SYMBOL MIN MAX UNIT tsu(RA) Setup time, read address MCA stable before falling edge ofstrobe MCDS TRA(SU) 0 ns th(RA) Hold time, read address MCA stable after rising edg...
Page 28 - Figure 3–5. Microcontroller Interface Timing Requirements
3–5 3.5 TCM4300 to Microcontroller Interface Timing Requirements (Intel WriteCycle) (see Figure 3–5 and Note 3) PARAMETER ALTERNATE SYMBOL MIN MAX UNIT tsu(WA) Setup time, write address MCA stable before falling edgeof strobe MCRW TWA(SU) 0 ns th(WA) Hold time, write address MCA stable after rising ...
Page 29 - Figure 3–6. Microcontroller Interface Timing Requirements
3–6 3.6 TCM4300 to Microcontroller Interface Timing Requirements (Motorola16-Bit Read Cycle) (see Figure 3–6 and Note 4) PARAMETER ALTERNATE SYMBOL MIN MAX UNIT tsu(R/W) Setup time, read/write MCRW stable before falling edge ofstrobe MCDS TRW(SU) 0 ns th(R/W) Hold time, read/write MCRW stable after ...
Page 30 - Figure 3–7. Microcontroller Interface Timing Requirements
3–7 3.7 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 16-Bit Write Cycle) (see Figure 3–7 and Note 4) PARAMETER ALTERNATE SYMBOL MIN MAX UNIT tsu(R/W) Setup time, read/write MCRW stable before falling edge ofstrobe MCDS TRW(SU) 0 ns th(R/W) Hold time, read/write MCRW stable afte...
Page 31 - Figure 3–8. Microcontroller Interface Timing Requirements
3–8 3.8 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-BitRead Cycle) (see Figure 3–8 and Note 5) PARAMETER ALTERNATE SYMBOL MIN MAX UNIT tsu(R/W) Setup time, read/write MCRW stable before rising edge ofstrobe MCDS TRW(SU) 0 ns th(R/W) Hold time, read/write MCRW stable after fa...
Page 32 - Figure 3–9. Microcontroller Interface Timing Requirements
3–9 3.9 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-BitWrite Cycle) (see Figure 3–9 and Note 5) PARAMETER ALTERNATE SYMBOL MIN MAX UNIT tsu(R/W) Setup time, read/write MCRW stable before rising edge ofstrobe MCDS TRW(SU) 0 ns th(R/W) Hold time, read/write MCRW stable after f...
Page 36 - Principles of Operation; This section describes the operation of the TCM4300 in detail.; Data Transfer; Table 4–1. TCM4300 Receive Channel Control Signals
4–1 4 Principles of Operation This section describes the operation of the TCM4300 in detail. NOTE: Timing diagrams and associated tables are contained in Section 3 of this datamanual. 4.1 Data Transfer The interface to both the system digital signal processor and microcontroller is in the form of 2s...
Page 38 - Transmit Section; /4 DQPSK data samples. These samples are then filtered by a digital
4–3 Table 4–3. Receive (RX) Channel Frequency Response (FM Input in Analog Mode) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT F 2 5 V k k 0 kHz to 6 kHz (see Note 1) ± 0.5 dB Frequency response 2.5 V peak-to-peak 20 kHz to 30 kHz (see Note 2) – 18 dB q y p p p 34 kHz to 46 kHz (see Note 3) – 48 Peak-t...
Page 39 - Modulation error percentage
4–4 square-root raised-cosine (SQRC) shaping filter with a roll-off rate of α = 0.35 and converted to sampled analog form by two 9-bit digital-to-analog converters (DACs). The output of the DAC is then filtered by acontinuous-time resistance-capacitance (RC) filter. The TCM4300 generates a power amp...
Page 42 - Transmit I And Q Output Level; should approximate the; Wide-Band Data Demodulator
4–7 D Q CLK Dibit In TXGO D Q CLK SINT BST Offset Delay Channel Delay (15.5 SINT Periods) TXI, TXQ BST Offset Delay PAEN Delay PAEN Delay = 0, 1/4, 1/2, 3/4 Transmit Channel Delay + d(T/8)Occurs from last symbol (2 SINT periods)before TXGO goes low PAEN Delay + d(T/8)TXGO high: 9.5 SINT periods + d(...
Page 43 - Table 4–9. Bits in Control Register WBDCtrl; Wide-band Data Interrupts; s, 8 bits are placed in the WBD register, which is accessible
4–8 Table 4–8. Typical Bit-Error-Rate Performance (WBD_BW = 000) PARAMETER TEST CONDITIONS MIN MAX UNIT PARAMETER MEAN CNR MIN MAX UNIT Bi – 5 0.4 dB Bi 0 0.279 dB Bi 5 0.143 dB Bit error rate 10 0.056 dB 15 0.0192 20 0.00623 25 0.00199 The WBDD is controlled by the bits in the control register WBDC...
Page 44 - Wide-band Data Demodulator General Information; Figure 4–3. WBD Manchester-Coded Data Stream
4–9 At the same time, the interrupts DWBDINT and MWBDFINT are asserted. The interrupt rate is 800 µ s (8 bits/10 kHz). These interrupts are individually cleared when the WBD register is read by thecorresponding processor. They can also be cleared by their respective processor by writing a 1 to theco...
Page 45 - Auxiliary DACs, LCD Contrast Converter; s after the
4–10 4.9 Auxiliary DACs, LCD Contrast Converter Auxiliary DACs generate AFC, AGC and power control signals for the RF system. These three D/Aconverters are updated when the corresponding data is received from the DSP. In fewer than 5 µ s after the corresponding registers are written to, the output h...
Page 46 - Timing And Clock Generation
4–11 4.9 Auxiliary DACs, LCD Contrast Converter (continued) Table 4–12. Auxiliary D /A Converters Slope (LCDCONTR) AUXFS[1:0] SETTING SLOPE NOMINAL LSB VALUE (V) NOMINAL OUTPUT VOLT- AGE FOR DIGITAL CODE = 8 (MIDRANGE) (V) NOMINAL OUTPUT VOLTAGE FOR DIGITAL CODE = 16† (MAX VALUE) (V) 00 2.5/16 0.156...
Page 47 - Figure 4–4. Codec Master and Sample Clock Timing; Clock Generation; MCLKIN; Microcontroller Clock
4–12 CMCLK CSCLK Codec Master Clock 2.048 MHz Codec Sample Clock 8 kHz Figure 4–4. Codec Master and Sample Clock Timing 4.11.1 Clock Generation There are three options for generating the master clock. A fundamental crystal or a third-overtone crystalwith a frequency of 38.88 MHz can be connected bet...
Page 48 - Phase-Adjustment Strategy
4–13 4.11.5 Phase-Adjustment Strategy For an IS-54 system in the digital mode, receiver sample timing must be phase adjusted to synchronize theA/D conversions to optimum sampling points of the received symbols, and to synchronize the mobile unittiming to the base station timing. This is done by temp...
Page 50 - Frequency Synthesizer Interface; The polarity of the clock (rising or falling edge)
4–15 4.12 Frequency Synthesizer Interface The synthesizer interface provides a means of programming three synthesizers. The synthesizer-sideoutputs are a data line, a clock line, and three latch enable lines that separately strobe data into eachsynthesizer. The control inputs are registers mapped in...
Page 51 - Figure 4–6. Synthesizer Interface Circuit Block Diagram
4–16 D E D E D E SEL 0 SEL 1 SEL 2 S R A B A A = B A = B B A B ≤ A B Clock Circuit HIGHVAL DMUX LOWVAL NUMCLKS 5 BIT CNT [0 . . . 31] MUX 32 32-Bit Data Register 8 Control Registers 5 5 5 3 Ready and Timing Logic SYNRDY To MStatCtrl Register CLKPOL NUMCLKS LOWVAL HIGHVAL SEL[2:0] MSB/LSB FIRST SYNDT...
Page 53 - Figure 4–8. Example Synthesizer Output; Power Control Port; Table 4-15. External Power Control Signals
4–18 Up to 31 data bits plus a latch enable (SYNLE0,1,2) can be programmed in one programming cycle. Whendata greater than or equal to 32 bits must be programmed, TI recommends using two or more programmingcycles with data in each cycle and a latch enable in the final programming cycle. Two or more ...
Page 54 - Figure 4–9. Internal and External Power Control Logic
4–19 In addition to allowing control of power to external functional modules, these power control bits combinedwith other control bits are used to control internal TCM4300 functions. This control system is shown inFigure 4–9. Transmitter Control Circuits MStatCtrl DStatCtrl WBD Ctrl WBD_ON SCEN FMRX...
Page 55 - Figure 4–10. Microcontroller-DSP Data Buffers
4–20 In the analog mode, (MODE bit set low), PAEN is high whenever TXEN is active and SYNOL is low. TheSYNOL input can be used as an indication to the TCM4300 that the external synthesizers are out of lock.The PAEN signal is gated by SYNOL to prevent off-channel transmissions. The TXEN, IQRXEN, FMVO...
Page 56 - Microcontroller Register Map; Table 4–16. Microcontroller Register Map
4–21 4.15 Microcontroller Register Map The microcontroller can access 17 locations within the TCM4300. The register locations are 8 bits wide asshown in Table 4–16 and Table 4–17. Table 4–16. Microcontroller Register Map ADDR NAME D7 D6 D5 D4 D3 D2 D1 D0 00h WBDCtrl WBD_LCKD WBD_ON WBD_BW Reserved 0...
Page 57 - Table 4–17. Microcontroller Register Definitions
4–22 Table 4–17. Microcontroller Register Definitions ADDR NAME CATEGORY R/W 00h WBDCtrl Wide-band data W 00h WBD Wide-band data R 01h FIFO FIFO A(B) microcontroller to DSP (DSP to microcontroller) W/(R) 02h MIntCtrl Interrupt/control status R/W 03h SynData0 S h i i f W 04h SynData1 S h i i f W 05h ...
Page 58 - Table 4–18. WBDCtrl Register; Microcontroller Status and Control Registers
4–23 Table 4–18. WBDCtrl Register BIT R / W NAME FUNCTION RESET VALUE 9 R / W WBD_LCKD Wide-band data lock data. WBD_LCKD determines whether edgedetector is locked (1) or unlocked (0). 0 8 R / W WBD_ON Wide-band data on. WBD_ON turns the WBDD module on/off (1/0). 0 7 – 5 R / W WBD_BW[2:0] Wide-band ...
Page 59 - Table 4–19. MStatCtrl Register Bits
4–24 Table 4–19. MStatCtrl Register Bits BIT R / W NAME FUNCTION RESET VALUE 7 R SYNOL Synthesizer out of lock. SYNOL is equal to the level applied to SYNOLinput pin. SYNOL can be used as an input for an externally generatedstatus signal to prevent transmission when external synthesizers areout of l...
Page 60 - DSP Register Map; Table 4–20. DSP Register Map; Table 4–21. DSP Register Definitions
4–25 4.19 DSP Register Map The register map accessible to the DSP port is shown in Table 4–20 and Table 4–21. There are 14 systemaddressable locations. Note that the write address of FIFO B is the same as the read address of FIFO A.Figure 4-11 details the connection of TCM4300 to an example DSP. Tab...
Page 61 - Figure 4–11. DSP Interface; Base Station Offset Register; The delay in the TCM4300 TX channels is increased by the amount:
4–26 D[15:6] A[3:0] IS R/W STRB INT 1 INT 3 INT 4 DSPD[9:0] DSPA[3:0] DSPCSL DSPRW DSPSTRBL SINT CINT BDINT DSP TCM4300 10 4 Figure 4–11. DSP Interface 4.20 Wide-Band Data Registers Bit 9 of the wide-band data register is the most recently received bit as shown below. WBD 9 – 2 1 – 0 WBD WB Data Res...
Page 62 - DSP Status and Control Registers; Table 4–22. DStatCtrl Register Bits
4–27 4.22 DSP Status and Control Registers DIntCtrl, Clear and Send Bits: The bit names in the DIntCtrl register indicate the action to be taken whena 1 is written to the respective bit. When these bits are being read, a 1 indicates that the correspondinginterrupt is pending. A 0 indicates that the ...
Page 63 - Internal Reset State; Table 4–23. Power-On Reset Register Initialization
4–28 4.23 Reset A low on RSINL causes the TCM4300 internal registers to assume their reset values. The power-on resetcircuit also causes internal reset. However, the logic level at RSINL has no effect on reset outputs RSOUTHand RSOUTL. The effects of resetting the TCM4300 are described in the follow...
Page 64 - Microcontroller Interface; Table 4–24. Microcontroller Interface Configuration; The internal chip select is asserted when MCCSH = 1 and MCCSL = 0.; Intel Microcontroller Mode Of Operation; Table 4–25. Microcontroller Interface Connections for Intel Mode
4–29 4.24 Microcontroller Interface The microcontroller interface of the TCM4300 is a general purpose bus interface (see Table 4–24) whichensures compatibility with a wide range of microcontrollers, including the Mitsubshi M37700 series and mostIntel and Motorola series. The interface consists of a ...
Page 65 - Mitsubishi Microcontroller Mode of Operation; Motorola Microcontroller Mode of Operation
4–30 4.24.2 Mitsubishi Microcontroller Mode of Operation When the microcontroller type select MTS1 and MTS0 inputs are held high and low, respectively, theTCM4300 microcontroller interface is configured in Mitsubishi mode. In this mode, the interface has a singleread/write control (R / W) signal, an...
Page 68 - Mechanical Data; PLASTIC QUAD FLATPACK
5–1 5 Mechanical Data 5.1 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 4040149 / A 03/95 50 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 51 25 75 1 12,00 TYP 0,17 76 100 SQ SQ 15,80 16,20 13,80 1,35 1,45 1,60 MAX 14,20 0 ° – ā 7 ° Seating Plane 0,08 0,50 M 0,08 NOTES: A. All linear dimensions are i...
