Page 2 - IMPORTANT NOTICE
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being r...
Page 3 - Introduction; Description
1−1 1 Introduction 1.1 Description The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digitalparametric equalization, dynamic range compression, and loudness contour. Additionally, this device provideshigh-quality, soft digital volume, bass, and treble...
Page 4 - Functional Block Diagram
1−2 • Two I 2 C-selectable, single-ended analog input stereo channels • Equalization bypass mode • Single 3.3-V power supply • Power down without reloading the coefficients • Sampling rates of 32 kHz, 44.1 kHz, or 48 kHz • Master clock frequency of 256 f S or 512 f S • Can have crystal input to repl...
Page 6 - Terminal Assignments; Terminal Functions
1−4 1.4 Terminal Assignments Figure 1−2 shows the terminal locations on the package outline, along with the signal name assigned to eachterminal. 14 15 NCAV DD NCGPI5GPI4GPI3GPI2GPI1GPI0ALLPASSSDOUT1SDOUT0 36 35 34 33 32 31 30 29 28 27 26 25 16 1 2 3 4 5 6 7 8 9 10 11 12 LINA V RFILT AV SS(REF) AV S...
Page 9 - Audio Data Formats; Serial Interface Formats; Table 2−1. Serial Interface Options
2−1 2 Audio Data Formats 2.1 Serial Interface Formats The TAS3002 device works in master or slave mode. In the master mode, terminal 21 (IFM/S) is tied high. This activates the master clock (MCLK) circuitry. A crystal canbe connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, T...
Page 10 - Digital Output Modes; Left channel is transmitted when LRCLK is high.
2−2 2.2 Digital Output Modes The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3. 2.2.1 MSB-First, Right-Justified, Serial-Interface Format The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Fi...
Page 11 - The normal output mode for the I; S Serial-Interface Format
2−3 2.2.2 I 2 S Serial-Interface Format The normal output mode for the I 2 S serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−2 shows the following characteristics of this protocol: • Left channel is transmitted when LRCLK is low. • SDIN is sampled with the rising edge of SCLK. • SDOU...
Page 13 - Switching Characteristics; S Serial Protocols
2−5 2.3 Switching Characteristics PARAMETER MIN TYP MAX UNIT tc(SCLK) SCLK cycle time 325.5 ns td(SLR) SCLK rising to LRCLK edge 20 ns td(SDOUT) SDOUT valid from SCLK falling edge (see Note 1) (1/256 fS) + 10 ns tsu(SDIN) SDIN setup before SCLK rising edge 20 ns th(SDIN) SDIN hold after SCLK rising ...
Page 15 - Analog Input/Output; Analog Input; Figure 3−1. Analog Input to the TAS3002 Device; Analog Output; Direct Analog Output; The full scale analog output from the TAS3002 device is 0.707 V; . It is referenced to VCOM which is approximately
3−1 3 Analog Input/Output The TAS3002 device contains a stereo 24-bit ADC with two single-ended inputs per channel. Selection of the A orB analog input is accomplished by setting a bit in the analog control register (ACR) by an I 2 C command. Additionally, the TAS3002 device has a stereo 24-bit digi...
Page 16 - Figure 3−2. VCOM Decoupling Network; Analog Output With Gain; , the output level can be increased by; (when it has a gain of; Figure 3−3. Analog Output With External Amplifier
3−2 AOUTR 10 µ F 24-Bit DAC AOUTL VCOM + 0.1 µ F AGND Analog Output (Adjust Capacitors for Desired Low Frequency Response) Figure 3−2. VCOM Decoupling Network 3.2.2 Analog Output With Gain Because the maximum analog output from the TAS3002 device is 0.707 V rms , the output level can be increased by...
Page 17 - Reference Voltage Filter; Figure 3−4 shows the TAS3002 reference voltage filter.; Figure 3−4. TAS3002 Reference Voltage Filter
3−3 3.2.3 Reference Voltage Filter Figure 3−4 shows the TAS3002 reference voltage filter. 0.1 µ F 15 µ F + 0.1 µ F 1 µ F + 0.1 µ F 4 2 3 45 44 VREFP AV SS AV SS(REF) V RFIL T V REFM TAS3002 Figure 3−4. TAS3002 Reference Voltage Filter
Page 19 - Audio Control/Enhancement Functions; Soft Volume Update; C interface in 4.16 format—4 bits for the; Software Soft Mute
4−1 4 Audio Control/Enhancement Functions 4.1 Soft Volume Update The TAS3002 device implements a TI proprietary soft volume update. This feature allows a smooth andpleasant-sounding change from one volume level to another over the entire range of volume control (18 dB to mute). The volume is adjusta...
Page 20 - The gain values for treble control can be found in Section NO TAG.
4−2 SDIN2_L 7 Biquad Filters Tone Soft Volume DRCE SDIN1_L ADC_L SDOUT1 7 Biquad Filters Tone Soft Volume DRCE SDIN2_R SDIN1_R ADC_R SDOUT2 1/2 L + R_SUM Right Channel Mix CoefficientsI2C Register Address 07h SDIN1 ^ SDIN2 ^ ADC = (3) 24-Bit Right Mix Coefficient Left Channel Mix CoefficientsI2C Reg...
Page 21 - Bass Control; The gain values for bass control can be found in Section NO TAG.; Figure 4−2. De-Emphasis Mode Frequency Response
4−3 4.6 Bass Control The bass gain level can be adjusted within the range of 15 dB to − 15 dB with 0.5-dB step resolution. The level changesare accomplished by downloading bass codes (shown in NO TAG) into the bass frequency control register.Alternatively, a limited range of bass control is availabl...
Page 22 - An I; Table 4−1. Analog Control Register Description
4−4 4.8 Analog Control Register (40h) The analog control register (ACR) allows control of de-emphasis, selection of the analog input channel to the ADC,and analog power down. An I 2 C master is required to write the appropriate command into the ACR. The ACR subaddress is 40h. Bit 7 6 5 4 3 2 1 0 Typ...
Page 23 - Dynamic Loudness Contour; Figure 4−3 is a block diagram of this circuit.; Figure 4−3. Dynamic Loudness Contour Block Diagram; Loudness Biquads; Loudness Gain; C. Their subaddresses; Loudness Contour Operation; See Section NO TAG for programming instructions.
4−5 4.9 Dynamic Loudness Contour The necessity for applying loudness compensation to playback systems to compensate for the fact that the earperceives bass and treble less audibly at low levels than at high ones has been established since the first data waspublished by Fletcher and Munson in 1933. T...
Page 24 - Figure 4−4. TAS3002 Digital Signal Processing Block Diagram; AllPass Function; In AllPass mode, the bass and treble controls are still functional.
4−6 4.10 Dynamic Range Compression/Expansion (DRCE) The TAS3002 device provides the user with the ability to manage the dynamic range of the audio system. The DRCEreceives data, and affects scaling after the volume/loudness block. As shown in Figure 4−4, the DRCE is applied afterthe volume/loudness ...
Page 25 - C with the address 01h.; Table 4−2. Main Control Register 1 Description; C with the address 43h.; Table 4−3. Main Control Register 2 Description
4−7 4.12 Main Control Register 1 (01h) The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2(MCR2). The MCR1 register contains the bits associated with load speed, SCLK frequency, serial-port mode, andserial-port word length. It is accesse...
Page 27 - Filter Processor; Biquad Block; Figure 5−1. Biquad Cascade Configuration; Filter Coefficients; C port and loaded into the biquad memory; Biquad Structure; is fixed at value 1 and is not downloadable.
5−1 5 Filter Processor 5.1 Biquad Block The biquad block consists of seven digital biquad filters per channel organized in a cascade structure, as shown inFigure 5−1. Each of these biquad filters has five downloadable 24-bit (4.20) coefficients. Each stereo channel hasindependent coefficients. Biqua...
Page 29 - C Serial Control Interface; Introduction; Control parameters for the TAS3002 device can be loaded from an I; C Protocol; Figure 6−1. Typical I
6−1 6 I 2 C Serial Control Interface 6.1 Introduction Control parameters for the TAS3002 device can be loaded from an I 2 C serial EEPROM by using the TAS3002 master interface mode. If no EEPROM is found, the TAS3002 device becomes a slave device and loads from another I 2 C master interface. Inform...
Page 30 - Table 6−1 lists the definitions used by the I; C Protocol Definitions; Operation; C addresses (two read; C Address Byte Table; Write Cycle Example
6−2 Table 6−1 lists the definitions used by the I 2 C protocol. Table 6−1. I 2 C Protocol Definitions DEFINITION DESCRIPTION Transmitter The device that sends data Receiver The device that receives data Master The device that initiates a transfer, generates clock signals, and terminates the transfer...
Page 31 - C Readback Example; C Wait States
6−3 6.3.2 TAS3002 I 2 C Readback Example The TAS3002 saves in a stack or first-in first-out (FIFO) buffer the last 7 bytes that were sent to it. When an I 2 C read command is sent to the device (LSB=high), it answers by popping the first byte off the stack. The TAS3002 thenexpects either a Send Ack ...
Page 32 - SMBus Operation; Block Write Protocol
6−4 Table 6−3 gives typical values of the wait states that can be expected with the various functions of the part: Table 6−3. I 2 C Wait States SYSTEM SAMPLING FREQUENCY 32 kHz 44.1 kHz 48 kHz Comment Volume 62 ms 49 ms 41 ms Not dependent on size of change Bass 231 ms 167 ms 153 ms 0 to −18 dB Treb...
Page 33 - Wait States
6−5 6.4.3 Wait States If separate I 2 C/SMBus commands are sent too frequently, the TAS3002 device can generate a bus wait state. This happens when the device is busy while performing smoothing operations and changing volume, bass, and treble.The wait occurs after the bus acknowledge on the first da...
Page 35 - Microcontroller Operation; General Description; Reset
7−1 7 Microcontroller Operation The TAS3002 device contains an internal microcontroller programmed by Texas Instruments to performhousekeeping and interface functions. Additionally, it handles I 2 C communication and general purpose input functions. 7.1 General Description The microcontroller uses a...
Page 36 - Reset Circuit; Fast Load Mode
7−2 • Clears all the registers in the circuits • Purges the codec • Selects analog input A (RINA and LINA) and sets the input A active indicator (INPA) low • Initializes the equalization parameters to AllPass filters • Sets the digital audio interface to the I 2 S 18-bit mode • Sets the bass/treble ...
Page 37 - Codec Reset; Set the serial audio input clocks to 0
7−3 Bass and treble cannot download in this mode. Mixer1 and Mixer2 registers can download in this mode or normalmode (FL bit = 0). Once the download is complete, the fast load bit must be cleared by writing a 0 into bit 7 of main control register 1(MCR1). This puts the TAS3002 device into normal mo...
Page 38 - Power-Down Timing Sequence; Test Mode; GPI Interface
7−4 7.3.1 Power-Down Timing Sequence PWR_DN Power-Down Mode RESET MCLK SCLK LRCLK SDATA 1 ms Normal Operation Figure 7−2. Power-Down Timing Sequence In power-down mode, the TAS3002 device typically consumes less than 1 mA. 7.4 Test Mode Terminal 9 (TEST) is tied low in normal operation. This functio...
Page 39 - Table 7−1. GPI Terminal Programming; C to a TAS3001 device mapped; GPI Architecture
7−5 Table 7−1. GPI Terminal Programming GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 VOL_UP, +1 dB x VOL_DN, −1 dB x BASS_UP, +1 dB x BASS_DN, −1 dB x TREB_UP, +1 dB x TREB_DN, −1 dB x Shift 1 x x Mute x EQ1 x EQ2 x EQ3 x EQ4 x EQ5 x Shift 2 x x NOTE: x = Logic low Initially (after reset), the TAS3002 GPI is set t...
Page 40 - Figure 7−3. Internal Interface Flow Chart
7−6 Start Power Up Initialize Default EEPROM Restore Volume and MCR Slave Write Initialize TAS3002 TAS3001 GPI Power Down Load Parameters and Coefficients to DSP Volume/Bass/Treble Up/Down Echo to TAS3001 Switch BQ Set Save Volume, Mute Save PWR_DN Stop PLL Stop DRC_OFF DRC Figure 7−3. Internal Inte...
Page 41 - External EEPROM Memory Maps
7−7 7.7 External EEPROM Memory Maps Table 7−2 through Table 7−5 show the 512-byte and 2048-byte EEPROM memory maps. Table 7−2. 512-Byte EEPROM Memory Map 2.0 Channels ADDRESS BYTE NUMBER FUNCTION 000h 1 Signature (2Ah) 001h 1 ID byte = 0000 0000 002h 1 MCR 003h−00Bh 9 Mixer left gain 00Ch−014h 9 Mix...
Page 45 - Electrical Characteristics; Absolute Maximum Ratings Over Operating Temperature Ranges
8−1 8 Electrical Characteristics 8.1 Absolute Maximum Ratings Over Operating Temperature Ranges † Supply voltage range: AV DD − 0.3 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DV DD − 0.3 V to 3.6 V . . . . . . . . . . . . . ...
Page 46 - ADC Digital Filter; S mode; Figure 8−1. ADC Digital Filter Characteristics; Figure 8−2. ADC Digital Filter Stop-Band Characteristics
8−2 8.4 ADC Digital Filter T A = 25 ° C, AV DD = 3.3 V, DV DD = 3.3 V, f S = 48 kHz, 20-bit I 2 S mode All terms characterized by frequency are scaled with the chosen sampling frequency, f S . See Figure 8−1 through Figure 8−4 for performance curves of the ADC digital filter. PARAMETER TEST CONDITIO...
Page 47 - Figure 8−3. ADC Digital Filter Pass-Band Characteristics; Figure 8−4. ADC High-Pass Filter Characteristics
8−3 0.002 −0.002 Amplitude − dB 0.004 0.006 0.008 0 0 f − Frequency − Hz 0.1 fs 0.2 fs 0.3 fs 0.4 fs 0.5 fs Figure 8−3. ADC Digital Filter Pass-Band Characteristics −0.4 −1 Amplitude − dB −0.2 0 0.2 −0.6 −0.8 0 f − Frequency − Hz 1 fs 2 fs 3 fs 4 fs Figure 8−4. ADC High-Pass Filter Characteristics 8...
Page 48 - Input Multiplexer; DAC Interpolation Filter; Figure 8−5. DAC Filter Overall Frequency Characteristics; Figure 8−6. DAC Digital Filter Pass-Band Ripple Characteristics
8−4 8.6 Input Multiplexer T A = 25 ° C, AV DD = 3.3 V, DV DD = 3.3 V, f S = 48 kHz, 20-bit I 2 S mode PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input impedance 20 k Ω Crosstalk 85 dB Full-scale input voltage range 1.7 VPP 8.7 DAC Interpolation Filter T A = 25 ° C, AV DD = 3.3 V, DV DD = 3.3 V, f S ...
Page 49 - sine wave at 1 kHz; DAC Output Performance Data
8−5 8.8 Digital-to-Analog Converter T A = 25 ° C, AV DD = 3.3 V, DV DD = 3.3 V, f S = 48 kHz, input = 0 dB-f S sine wave at 1 kHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SNR (EIAJ) A weighted 94 99 dB Dynamic range −60 dB, 1 kHz 92 96 dB Signal to (noise + distortion) ratio 0 dB, 1 kHz, 20 Hz to ...
Page 50 - C Serial Port Timing Characteristics; C Bus Timing
8−6 8.10 I 2 C Serial Port Timing Characteristics MIN MAX UNIT f(SCL) SCL clock frequency 0 100 kHz t(buf) Bus free time between start and stop 4.7 µ s t(low) Low period of SCL clock 4.7 µ s t(high) High period of SCL clock 4.0 µ s th(sta) Hold time repeated start 4.0 µ s tsu(sta) Setup time repeate...
Page 51 - System Diagrams; Figure 9−1. Stereo Application
9−1 9 System Diagrams Figure 9−1 and Figure 9−2 show the TAS3002 stereo and 2.1-channel applications, respectively. TAS3002 Master RESET Analog In +3.3 VDD Analog Out SPDIF or USB I2S EEPROM I2C Clock Select Logic B-T-V-EQ Switches NOTE: Items such as the PLL network and power supplies are omitted f...
Page 53 - 0 Mechanical Information; PLASTIC QUAD FLATPACK
10−1 10 Mechanical Information The TAS3002 device is packaged in a 48-terminal PFB package. The following illustration shows the mechanicaldimensions for the PFB package. PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176 / B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 24 2...
