Page 2 - IMPORTANT NOTICE
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being r...
Page 3 - Preface; Read This First; About This Manual; This document contains the following chapters:; Information About Cautions and Warnings; This book may contain cautions and warnings.; This is an example of a caution statement.
Information About Cautions and Warnings iii Read This First Preface Read This First About This Manual This user’s guide describes techniques for designing synchronous buckconverters using TI’s SLVP1111–114 evaluation modules (EVM) and TPS56xxripple regulator controllers. How to Use This Manual This ...
Page 4 - Related Documentation From Texas Instruments; TPS56xx data sheet (literature number SLVS177A); FCC Warning; TI is a trademark of Texas Instruments Incorporated.
Trademarks iv Related Documentation From Texas Instruments Synchronous Buck Converter Design Using TPS56xx Controllers inSLVP10x EVMs User’s Guide (literature number SLVU007). TPS56xx data sheet (literature number SLVS177A) Designer’s Notebook The TPS56xx Family of Power Supply Controllers (literatu...
Page 5 - Contents; Introduction; Test Results
Running Title—Attribute Reference v Chapter Title—Attribute Reference Contents 1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Synchronous Buck Regulator Operation 1-2 . . . . . . . . . ....
Page 6 - Figures
Running Title—Attribute Reference vi Figures 1–1 Simplified Synchronous Buck Converter Schematic 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Simplified Hysteretic Controlled Output Voltage Waveform 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 SLVP111–114 EV...
Page 7 - Tables
Running Title—Attribute Reference vii Contents 3–27 SLVP113 Measured Start-Up (V IN ) Waveforms 3-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–28 SLVP113 Measured Load Transient Waveforms 3-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29 SLVP...
Page 9 - Topic; Chapter 1
1-1 Introduction Introduction The SLVP111/112/113/114 evaluation modules (EVMs) have been designedand tested using the TPS56xx hysteretic controllers. These boards aresynchronous dc-dc buck converters with fixed output voltages of 3.3 V, 2.5 V,1.8 V and 1.5 V respectively. They use only surface moun...
Page 10 - Synchronous Buck Regulator Operation; Figure 1–1. Simplified Synchronous Buck Converter Schematic
Synchronous Buck Regulator Operation 1-2 1.1 Synchronous Buck Regulator Operation The synchronous buck converter is a variation of the traditional buckconverter. The main switching device is usually a power MOSFET and isdriven in the same manner as in a traditional buck converter. The freewheelingre...
Page 11 - Hysteretic Control Operation
Hysteretic Control Operation 1-3 Introduction 1.2 Hysteretic Control Operation Hysteretic control, also called bang-bang control or ripple regulator control,maintains the output voltage within the hysteresis band centered about theinternal reference voltage. Figure 1–2 shows a simplified example of ...
Page 12 - Design Strategy; , but the height is significantly; Table 1–1 summarizes the four EVM converter modules.; Table 1–1. Summary of EVM Converter Modules
Design Strategy 1-4 1.3 Design Strategy The SLVP111–114 evaluation modules (EVMs) are optimized for 5-V maininput voltage and 6-A output current. The EVMs need an additional low current12-V (30 mA max) input voltage for the controller. TI’s application report,Providing a DSP Power Solution from 5 V ...
Page 13 - Design Specification Summary; Table 1–2. EVM Converter Operating Specifications; Specification
Design Specification Summary 1-5 Introduction 1.4 Design Specification Summary This section summarizes the design requirements of the EVM converters.Although every attempt was made to accurately describe the performance ofthe EVM converters and the TPS56xx controllers, in case of conflicts, theTPS56...
Page 14 - Table 1–2. EVM Converter Operating Specifications (Continued)
Design Specification Summary 1-6 Table 1–2. EVM Converter Operating Specifications (Continued) Specification Min Typ Max Units Output ripple || SLVP111 (3.3 V)SLVP112 (2.5 V)SLVP113 (1.8 V)SLVP114 (1.5 V) 66503630 mV p–pmV p–pmV p–pmV p–p Efficiency, 6 A load SLVP111 (3.3 V)SLVP112 (2.5 V)SLVP113 (1...
Page 15 - Schematic; Figure 1–3. SLVP111–114 EVM Converter Schematic Diagram
Schematic 1-7 Introduction 1.5 Schematic Figure 1–3 shows the EVM converter schematic diagram. The schematicdiagrams for the other EVM converters are identical except for the controllerIC used. Figure 1–3. SLVP111–114 EVM Converter Schematic Diagram IOUT AGND2 OCP VHYST VREFB VSENSE ANAGND SLOWST BI...
Page 16 - Bill of Materials; Table 1–3 lists materials required for the SLVP111–114 EVMs.; Ref Des
Bill of Materials 1-8 1.6 Bill of Materials Table 1–3 lists materials required for the SLVP111–114 EVMs. Table 1–3. SLVP111–114 EVMs Bill of Materials Ref Des Part Number Description MFG C1 10TPA33M Capacitor, POSCAP, 33 µ F, 10 V, 20% Sanyo C2 6TPB150M Capacitor, POSCAP, 150 µ F, 6.3 V, 20% Sanyo C...
Page 18 - Board Layout; Figure 1–4. Top Assembly; Figure 1–6. Top Layer
Board Layout 1-10 1.7 Board Layout Figures 1–4 through 1–7 show the board layouts for the SLVP111–114evaluation modules. Figure 1–4. Top Assembly Top Assembly Figure 1–5. Bottom Assembly (Top View) Bottom Assembly (Top View) Figure 1–6. Top Layer Top Layer
Page 21 - Design Procedure; at a nominal; TPS56xx Functions; Chapter 2
2-1 Design Procedure Design Procedure The SLVP111–114 are dc-dc synchronous buck converter evaluation modules(EVMs) that provide a regulated output voltage at up to 6 A with a power inputvoltage range of 4.5 V to 6 V. A low power 12-V, 20-mA source is also requiredto power the TPS56xx controller. Th...
Page 23 - Figure 2–1. TPS56xx Functional Block Diagram; Undervoltage Lockout; The V; undervoltage lockout circuit disables the controller while V; is below
TPS56xx Functions 2-3 Design Procedure Figure 2–1. TPS56xx Functional Block Diagram INHIBIT OCP SLOWST IOUT BIAS DRV BOOT HIGHDR BOOTLO LOWDR DRVGND HISENSE IOUTLO LOSENSE PWRGD ANAGND CC V VREFB AGND2 VSENSE VHYST LODRV LOHIB _ + 2 V 10 V UVLO VCC 22 3 8 2 5 4 6 11 10 15 7 28 20 21 19 1 9 14 16 17 ...
Page 24 - F from zero volts
TPS56xx Functions 2-4 2.1.2 Inhibit The inhibit circuit is a comparator with a 2.1-V start voltage and a 100-mVhysteresis. When inhibit is low, the output drivers are low and the slowstartcapacitor is discharged. When inhibit is above the start threshold, the shortacross the slowstart capacitor is r...
Page 25 - Hysteresis Setting
TPS56xx Functions 2-5 Design Procedure R VREFB + 3.3 V 165 m A + 20 k W This value is used to determine the values of R10 and R14 that set thehysteresis level. The equations above can be used to derive a simplified relationship for theslowstart time as shown: t SLOWSTART + 5 C SLOWSTART R VREFB V O ...
Page 27 - Noise Suppression; Hysteretic regulators, by nature, have a fast response time to V; Figure 2–2. Block Diagram Showing Noise Suppression Circuits; Overcurrent Protection
TPS56xx Functions 2-7 Design Procedure 2.1.5 Noise Suppression Hysteretic regulators, by nature, have a fast response time to V O transients and are thus inherently noise sensitive due to the very high bandwidth of thecontroller. Noise suppression circuits were added to the TPS56xx to improvethe noi...
Page 28 - F capacitor, C6, which is connected from IOUTLO; Sensing Circuit
TPS56xx Functions 2-8 Figure 1–3). This arrangement improves efficiency over solutions having aseparate current sensing resistor. The drain of the high-side MOSFET isconnected to HISENSE (pin 19). The source of the high-side MOSFET isconnected to LOSENSE (pin 20). When the high-side MOSFET is on, aT...
Page 30 - Overvoltage Protection; If V; Power Good
TPS56xx Functions 2-10 An alternate current sensing scheme is to insert a current sense resistor inseries with the drain of Q1. Higher accuracy may be obtained at the expenseof lower efficiency. 2.1.7 Overvoltage Protection If V O exceeds Vref by 15%, a fault latch is set and the output gate drivers...
Page 31 - Figure 2–4. Gate Driver Block Diagram; at T
TPS56xx Functions 2-11 Design Procedure Figure 2–4. Gate Driver Block Diagram Level Shifter/ Predriver M1 45 Ω M2 5 Ω BOOT HIGHDR C4 BOOTLO Highside Driver Predriver M3 45 Ω M4 5 Ω LOWDR DRVGND Lowside Driver L2 Vphase C2 VO Vin C1 L1 C3 DRV 8 V Drive Regulator Adaptive Deadtime Control LOWDR VREF V...
Page 32 - Figure 2–5. I–V Characteristic Curve for Low-Side Gate Drivers
TPS56xx Functions 2-12 Figure 2–5. I–V Characteristic Curve for Low-Side Gate Drivers Driver Output Voltage – 1 V/div Driver Sink Current – 0.5 A/div The high-side gate driver is a bootstrap configuration with an internallyintegrated Schottky bootstrap diode. The voltage rating of the BOOT pin toDRV...
Page 33 - analog ground
TPS56xx Functions 2-13 Design Procedure LOHIB (pin 11) is an inhibit input for the low-side MOSFET driver. This inputhas to be logic low before the low-side MOSFET is allowed to be turned on,i.e., a logic high on LOHIB prevents the low-side MOSFET driver from turningon the low-side MOSFET. For norma...
Page 34 - External Component Selection; Duty Cycle Estimate; For an initial estimate for V; Input Capacitance; A RMS; The input capacitance for this design uses three 150-; Output Filter Design
External Component Selection 2-14 2.2 External Component Selection This section shows the procedure used in designing and selecting the powerstage components to meet the performance parameters shown in Table 1–2for the example circuit shown in Figure 1–3. 2.2.1 Duty Cycle Estimate An estimate of the...
Page 35 - Output Capacitance
External Component Selection 2-15 Design Procedure performance in response to fast load transients encountered when supplyingpower to current- and next-generation microprocessors. A secondaryconsideration is the switching frequency resulting from the output filtercomponent values. This section discu...
Page 36 - Where; Output Inductance
External Component Selection 2-16 for the particular application. In addition, the capacitor(s) must have an ampleripple current rating to handle the applied ripple current. This ripple current isdependent on the ripple current in the output inductance that is calculated inthe next section. The RMS ...
Page 37 - Switching Frequency Analysis; Output Ripple
External Component Selection 2-17 Design Procedure V L + L I TRAN t å L v V L I TRAN t Where: V L = the voltage applied across the output inductor, I TRAN = the magnitude of the load step, and ∆ t = the desired response time. For a load step from light load to heavy load, the voltage applied across ...
Page 38 - Figure 2–6. Output Ripple Voltage Detail; F ceramic capacitor in parallel with the; Switching Frequency Equation; is the inductor resistance
External Component Selection 2-18 Figure 2–6. Output Ripple Voltage Detail (a) Current waveform through output capacitor (b) Voltage waveform across ideal capacitor with initial value atbeginning of high-side MOSFET on-time V C + I t2 2 Co D Ts – I t 2 Co High-side MOSFET ON High-side MOSFET OFF V C...
Page 39 - Assume that delays for both
External Component Selection 2-19 Design Procedure Peak to peak value of the inductor current ∆ I is given by the following equation: I + V I – Io ǒ R DS(on) ) R L Ǔ –V O L D Ts (1) Where: V I =the input voltage V O = the output voltage Ts = the switching period D + V O ) Io ǒ R DS(on) ) R L Ǔ V I i...
Page 40 - Power MOSFET Selection; and; The total switching time,
External Component Selection 2-20 of power losses and additional voltage drops through non-ideal components.Equation (4) should be sufficiently accurate for the first frequency estimate atthe beginning of a design. 2.2.5 Power MOSFET Selection The TPS56xx is designed to drive N-channel power MOSFETs...
Page 41 - Test Summary; Chapter 3
3-1 Test Results Test Results This chapter shows the test setups used, and the test results obtained, indesigning the SLVP111–114 EVMS. Topic Page 3.1 Test Summary 3–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Test Setup 3–5 . . . . . . . . ....
Page 42 - Static Line and Load Regulation; The output voltage peak to peak ripple is less than; Efficiency and Power Losses; Evaluation Board; Output Start-Up and Overshoot
Test Summary 3-2 3.1 Test Summary The detailed test results and waveforms are presented in Figures 3–2 to 3–10for the SLVP111, Figures 3–11 to 3–19 for the SLVP112, Figures 3–20 to 3–28for the SLVP113 and Figures 3–29 to 3–37 for the SLVP114. The following aresummarized results. 3.1.1 Static Line an...
Page 43 - Frequency Variation; Designing Fast Response Synchronous Buck Converters; Load Current Transient Response; controller responds to a; Features
Test Summary 3-3 Test Results in a linear fashion. There is no discernable overshoot in the waveforms. In thisapplication, output voltage rise time is set to approximately 9 mS with anexternal capacitor. Although the EVMs have been tested with a very short Vccrise time, (see Figures 3–26 and 3–35) i...
Page 44 - Conclusion; Synchronous
Test Summary 3-4 3.1.8 Conclusion The test results of the SLVP111/112/113/114 EVMs demonstrate theadvantages of TPS56xx controllers to meet stringent supply requirements topower supplies, especially for powering DSPs and microprocessors. Thepower system designer has a good solution to optimize syste...
Page 45 - Test Setup
Test Setup 3-5 Test Results 3.2 Test Setup Follow these steps for initial power up of the SLVP112: 1) Connect an electronic load from Vout to PwrGND (J1-15, -16, -17, -18 to J1-11, -12, -13, -14) adjusted to draw approximately1 A at 2.5 V. The exact current is not critical; any nominal currentis suf...
Page 46 - Figure 3–1. Test Setup; V Power Supply
Test Setup 3-6 Figure 3–1. Test Setup 5V Power Supply + – Load + – 12-V Power Supply + –
Page 47 - Figure 3–2. SLVP111 Measured Load Regulation; SLVP111 MEASURED LOAD REGULATION; Figure 3–3. SLVP111Measured Efficiency; SLVP111 MEASURED EFFICIENCY
Test Results 3-7 Test Results 3.3 Test Results Figures 3–2 to 3–102 show test results for the SLVP111. Figure 3–2. SLVP111 Measured Load Regulation 3.295 3.29 3.285 0 1 2 3 4 5 6 – V 3.3 SLVP111 MEASURED LOAD REGULATION 3.305 V O IO – A Vin = 5.5 V Vin = 5 V Vin = 4.5 V Figure 3–3. SLVP111Measured E...
Page 48 - Figure 3–4. SLVP111Measured Power Dissipation; SLVP111 MEASURED POWER DISSIPATION; Figure 3–5. SLVP111Measured Switching Frequency; SLVP111 MEASURED SWITCHING FREQUENCY
Test Results 3-8 Figure 3–4. SLVP111Measured Power Dissipation 1.5 1 0.5 0 0 1 2 3 4 5 6 Ploss – W 2 SLVP111 MEASURED POWER DISSIPATION 2.5 Vin = 4.5 V Vin = 5 V Vin = 5.5 V IO – A Figure 3–5. SLVP111Measured Switching Frequency Vin = 4.5 V Vin = 5 V Vin = 5.5 V 125 100 75 50 0 1 2 3 4 5 6 Frequency...
Page 49 - Figure 3–6. SLVP111 Measured Switching Waveforms
Test Results 3-9 Test Results Figure 3–6. SLVP111 Measured Switching Waveforms C3 Pk–Pk50.8 mV C3 Frequency130.088 kHzLow SignalAmplitude C4 Max5.20 V C4 + Duty70.4% VDS Q22 V/div VO 20 mV/div 2.5 µ s/div Figure 3–7. SLVP111Measured Start-Up (INHIBIT) Waveforms C3 Pk–Pk3.36 V C3 Rise7.500 msLow Sign...
Page 51 - Figure 3–10. SLVP111 Measured Load Transient Waveforms; Figure 3–11. SLVP112 Measured Load Regulation; SLVP112 MEASURED LOAD REGULATION
Test Results 3-11 Test Results Figure 3–10. SLVP111 Measured Load Transient Waveforms C3 Pk–Pk208 mV C2 High6.5 V VO 100 mV/div 6.5 A IO 5 A/div 2.5 µ s/div Figure 3–11. SLVP112 Measured Load Regulation 2.5 2.495 0 1 2 3 4 5 6 2.505 SLVP112 MEASURED LOAD REGULATION 2.51 IO – A – V V O Vin = 5.5 V Vi...
Page 52 - Figure 3–13. SLVP112 Measured Power Dissipation
Test Results 3-12 Figure 3–12. SLVP112 Measured Efficiency SLVP111 MEASURED EFFICIENCY Vin = 5.5 V Vin = 4.5 V Vin = 5 V 84 82 80 78 1 2 3 4 5 6 Eficiency – % 86 88 90 IO – A Figure 3–13. SLVP112 Measured Power Dissipation 0 1 2 3 4 5 6 IO – A Vin = 5.5 V Vin = 4.5 V 1.5 1 0.5 0 Ploss – W 2 SLVP111 ...
Page 53 - Figure 3–14. SLVP112 Measured Switching Frequency; SLVP112 MEASURED SWITCHING FREQUENCY; Figure 3–15. SLVP112 Measured Switching Waveforms
Test Results 3-13 Test Results Figure 3–14. SLVP112 Measured Switching Frequency 225 200 175 150 0 1 2 3 4 5 6 Frequency – kHz 250 275 SLVP112 MEASURED SWITCHING FREQUENCY 300 Vin = 5.5 V Vin = 4.5 V Vin = 5 V IO – A Figure 3–15. SLVP112 Measured Switching Waveforms C3 Pk–Pk43.2 mV C3 Frequency218.8...
Page 55 - Figure 3–19. SLVP112 Measured Load Transient Waveforms
Test Results 3-15 Test Results Figure 3–18. SLVP112 Measured Start-Up (V IN ) Waveforms C3 Pk–Pk2.60 V C3 Rise7.635 ms C3 + Over3.2% VO 1 V/div VIN (5 V)1 V/div 2.5 ms/div Figure 3–19. SLVP112 Measured Load Transient Waveforms C3 Pk–Pk200 mV C2 High7.00 V VO 100 mV/div IO 2 A/div 5 A 25 µ s/div
Page 56 - Figure 3–20. SLVP113 Measured Load Regulation; SLVP113 MEASURED LOAD REGULATION; SLVP113 MEASURED EFFICIENCY
Test Results 3-16 Figure 3–20. SLVP113 Measured Load Regulation Vin = 5.5 V Vin = 4.5 V Vin = 5 V 1.8 1.7975 1.795 0 1 2 3 4 5 6 1.8025 SLVP113 MEASURED LOAD REGULATION 1.805 IO – A – V V O Figure 3–21. SLVP113 Measured Efficiency 80 78 76 72 1 2 3 4 5 6 Efficiency – % 82 86 SLVP113 MEASURED EFFICIE...
Page 57 - Figure 3–22. SLVP113 Measured Power Dissipation; SLVP113 MEASURED POWER DISSIPATION; Figure 3–23. SLVP113 Measured Switching Frequency; SLVP113 MEASURED SWITCHING FREQUENCY
Test Results 3-17 Test Results Figure 3–22. SLVP113 Measured Power Dissipation 0 1 2 3 4 5 6 IO – A Vin = 5.5 V Vin = 4.5 V Ploss – W SLVP113 MEASURED POWER DISSIPATION Vin = 5 V 1.5 1 0.5 0 2 2.5 Figure 3–23. SLVP113 Measured Switching Frequency 0 1 2 3 4 5 6 Frequency – kHz SLVP113 MEASURED SWITCH...
Page 58 - Figure 3–24. SLVP113 Measured Switching Waveforms
Test Results 3-18 Figure 3–24. SLVP113 Measured Switching Waveforms C3 Pk–Pk34.8 mV C3 Frequency285.52 kHzLow SignalAmplitude C5 Max5.80 V VO 20 mV/div VDS Q22 V/div C4 + Duty40.4% 1 µ s/div Figure 3–25. SLVP113 Measured Start-Up (INHIBIT) Waveforms C3 Pk–Pk1.88 V C3 Rise7.360 msLow SignalAmplitude ...
Page 60 - Figure 3–28. SLVP113 Measured Load Transient Waveforms; Figure 3–29. SLVP114 Measured Load Regulation; SLVP114 MEASURED LOAD REGULATION
Test Results 3-20 Figure 3–28. SLVP113 Measured Load Transient Waveforms C3 Pk–Pk112 mV C2 High3.64 V VO 100 mV/div IO 5 A/div 3.6 A 25 µ s/div Figure 3–29. SLVP114 Measured Load Regulation Vin = 5.5 V Vin = 4.5 V Vin = 5 V 1.496 1.494 1.492 1.49 0 1 2 3 4 5 6 1.497 1.499 SLVP114 MEASURED LOAD REGUL...
Page 61 - SLVP114 MEASURED EFFICIENCY; Figure 3–31. SLVP114 Measured Power Dissipation; SLVP114 MEASURED POWER DISSIPATION
Test Results 3-21 Test Results Figure 3–30. SLVP114 Measured Efficiency Vin = 5.5 V Vin = 4.5 V IO – A Vin = 5 V 77 73 69 65 1 2 3 4 5 6 Efficiency – % 81 83 SLVP114 MEASURED EFFICIENCY 85 79 75 71 67 Figure 3–31. SLVP114 Measured Power Dissipation Vin = 5.5 V Vin = 4.5 V IO – A Vin = 5 V 1 0.5 0 0 ...
Page 62 - Figure 3–32. SLVP114 Measured Switching Frequency; SLVP114 MEASURED SWITCHING FREQUENCY; Figure 3–33. SLVP114 Measured Switching Waveforms
Test Results 3-22 Figure 3–32. SLVP114 Measured Switching Frequency Frequency – kHz Vin = 5.5 V Vin = 4.5 V Vin = 5 V IO – A 325 300 250 200 0 1 2 3 4 5 6 350 375 SLVP114 MEASURED SWITCHING FREQUENCY 400 275 225 Figure 3–33. SLVP114 Measured Switching Waveforms C3 Pk–Pk30.8 mV C3 Frequency337.82 kHz...
Page 64 - Figure 3–37. SLVP114 Measured Load Transient Waveforms
Test Results 3-24 Figure 3–36. SLVP114 Measured Start-Up (V IN ) Waveforms C3 Pk–Pk1.56 V C3 Rise7.07 msLow SignalAmplitude C3 + Over2.7% VO 1 V/div VIN (5 V)1 V/div 2.5 ms/div Figure 3–37. SLVP114 Measured Load Transient Waveforms C3 Pk–Pk108 mV C2 High3.08 V VO 50 mV/div IO 2 A/div 3 A 25 µ s/div
