Page 3 - Preface; Read This First; About This Manual; special typeface; bold
Notational Conventions iii Preface Read This First About This Manual This manual is intended to assist the designer who is attempting to implementa solution using the PCI4450 or PCI4451. Much, but not all, of the informationcontained herein can also be found elsewhere. However, the smaller size ofth...
Page 4 - LALK
Contents iv enter from items that the system displays (such as prompts, commandoutput, error messages, etc.). Here is a sample program listing: 0011 0005 0001 .field 1, 2 0012 0005 0003 .field 3, 4 0013 0005 0006 .field 6, 3 0014 0006 .even Here is an example of a system prompt and a command that yo...
Page 5 - Related Documentation From Texas Instruments; PCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet, SCPS046; PCI4451 GFN/GJG PC Card and OHCI Controller Data Manual, SCPS054; PHY Layout Recommendations Application Report, SLLA020A; FCC Warning; MicroStar BGA is a trademark of Texas Instruments.
Trademarks v This syntax shows that .byte must have at least one value parameter, butyou have the option of supplying additional value parameters, separatedby commas. Related Documentation From Texas Instruments PCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet, SCPS046 PCI4451 GFN/GJG PC Card ...
Page 7 - Contents
Contents vii Contents 1 PCI445X Device 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 System Features Selection 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....
Page 8 - Global Reset Only Bits, PME Context Bits; Global Reset Only Bits/PME Context Bits; PME and RI Behavior
Contents viii A Global Reset Only Bits, PME Context Bits A-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1 Global Reset Only Bits/PME Context Bits A-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B PME and RI Behavior B-1 . . . ....
Page 9 - Figures
Contents ix Figures 1–1 Typical System Architecture 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Serialized Interrupt Signal 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10 - Tables
Contents x Tables 1–1 Registers and Bits Loadable Through Serial EEPROM 1-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 PC Card Interface Pullup Register List 1-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 PCI Bus Interface Pullup Regist...
Page 11 - Topic; Chapter 1
1-1 PCI445X Device This implementation guide assists platform hardware developers designingwith the PCI445X dual socket PC card and 1394 open host controller interface(OHCI) link layer controller (LLC). The PCI445X designation refers to anydevice in the PCI445X family, for example, the PCI4450 or PC...
Page 12 - Figure 1–1. Typical System Architecture
1-2 Figure 1–1 illustrates a platform using the PCI445X device along with theTSB41LV03 3-port PHY, which provides the necessary interface to implementa 3-port IEEE1394 node. Figure 1–1. Typical System Architecture TSB41LV03A PHY CPU Memory North Bridge PCI Bus Graphics Controller South Bridge Sound ...
Page 13 - Package Types; MicroStar BGA; PME and RI Signaling
System Features Selection 1-3 PCI445X Device 1.1 System Features Selection This section explains selectable system features. Feature selection is requiredfor GPIO and MFUNC terminal assignments and PCI445X registerinitialization. Detailed system implementation methods are described in thefollowing s...
Page 14 - must be added on SDA and SCL when using an; PCI and ISA Style Interrupt; The PCI445X device provides three modes of interrupt signaling:; Socket Power Switches; CLKRUN
System Features Selection 1-4 automatically assigned on the dedicated SDA and SCL terminals. A pullupresistor (typically 10 k Ω) must be added on SDA and SCL when using an EEPROM. The value of the pullup resistor can vary for different EEPROMs.Refer to the EEPROM data sheet or contact the manufactur...
Page 15 - 1 MFUNC7–MFUNC0 Terminal Assignments; Serialized interrupt signaling is described below.; Figure 1–2. Serialized Interrupt Signal; Refer to the; Serialized IRQ Support for PCI Systems specification,
System Features Selection 1-5 PCI445X Device 1.1.10 Socket Activity LEDs Socket activity signals can be assigned on MFUNC4 (slot 1), MFUNC3 (slot 2),MFUNC5 (OHCI_LED), MFUNC6 (OHCI_LED), and MFUNC7 (OHCI_LED). 1.1.11 MFUNC7–MFUNC0 Terminal Assignments After selecting required functions for the syste...
Page 17 - Socket power can be protected from software control in the D3; Protection
System Features Selection 1-7 PCI445X Device CCLK can be slowed down rather than stopped by CCLKRUN. If CCLKRUNis set, the CLKCTRLEN (CardBus socket 20h, bit 16) and CLKCTR (CardBussocket 20h, bit 0) bits are both set to 1. The clock is slowed down to 1/16. Inthis mode the PCI clock is not allowed t...
Page 18 - System Implementation; Clamping Rails; IDSEL
System Implementation 1-8 1.2 System Implementation This section describes signal connection for each interface, PCI bus, PC cardinterface, I 2 C interface, P 2 C interface, ZV interface, interrupt interface (parallel and serial), miscellaneous signals, and the PHY-Link interface. It also explainspu...
Page 19 - Implementation Note: System Generation of IDSEL in the PCI; PCI Mobile Design Guide; PME
System Implementation 1-9 PCI445X Device IDSEL, there is no alternative. If another AD line is to be used for IDSEL,then the system designer must leave the pullup off LATCH and useMFUNC7 to route IDSEL. Also, if AD23 is used, then the resistive couplingshould not be used.Refer to the Implementation ...
Page 20 - PC Card Interface; Damping resistor on CCLK terminal; resistor is recommended (see; CD line filtering; for each of the power supply terminals: V; Socket power supply; and V; C) Interface for EEPROM
System Implementation 1-10 1.2.3 PC Card Interface The PC Card interface has two modes: the 16-bit interface mode and theCardBus 32-bit interface mode. Damping resistor on CCLK terminal A series-damping resistor is recommended on the CCLK signal. Thedamping resistor is system dependent. If line impe...
Page 21 - Table 1–1. Registers and Bits Loadable Through Serial EEPROM
System Implementation 1-11 PCI445X Device Table 1–1. Registers and Bits Loadable Through Serial EEPROM Register Offset Register Bits Loaded FromEEPROM The following are configuration registers for the OHCI function (function 2) PCI register (2Ch) PCI subsystem ID 15–0 PCI register (2Dh) PCI vendor I...
Page 22 - Sample PCI445X EEPROM Data File
System Implementation 1-12 1.3 Sample PCI445X EEPROM Data File Following is an example EEPROM data file used with the PCI445X device: ;PCI4450 default EEPROM Data File ;Register 0xXX Binary Description ;–––––––– –––– –––––– ––––––––––– 00 0x43 ;01000011 PCI max_lat (lower 4 bits)/PCI min gnt (lower ...
Page 24 - C Interface for TPS22X6 Power Switch; C interface requires only; Figure 1–4. TPS22X6 Power Switch Interface
System Implementation 1-14 1.3.1 P 2 C Interface for TPS22X6 Power Switch The interface between the PCI445X device and TPS22X6 power switch isserialized to reduce the number of signal lines. The P 2 C interface requires only three lines to control the switch. As a PCI445X default, the CLOCK signal i...
Page 25 - Interrupt Signaling Interface; Serialized Interrupt Interface; Miscellaneous Signals; SUSPEND
System Implementation 1-15 PCI445X Device If the third ZV source is not implemented, ZVPCLK and ZVSTAT are notrequired. To support ZV audio, an audio codec device is required for L and Rsound decoding. 1.3.3 Interrupt Signaling Interface Serialized Interrupt Interface The serialized interrupt (ISA a...
Page 26 - Figure 1–6. Distributed DMA Signal Connection; Requirement of Pullup/Pulldown Resistors; Table 1–2. PC Card Interface Pullup Resistor List
System Implementation 1-16 Figure 1–6. Distributed DMA Signal Connection PCGNT PCREQ PCI445X South Bridge (ex., PIIX4) 1.3.5 Requirement of Pullup/Pulldown Resistors Note: The PCI445X device has integrated pullup resistors and does not requireexternal pullups. Table 1–2. PC Card Interface Pullup Res...
Page 27 - Table 1–3. PCI Bus Interface Pullup Resistor List; Table 1–4. Miscellaneous Terminals Pullup Resistor List; Note: Removing clamping voltage makes all the clamped signals low.
System Implementation 1-17 PCI445X Device Table 1–3. PCI Bus Interface Pullup Resistor List PCI Signal Pull-Up Voltage FRAME V CCP TRDY V CCP IRDY V CCP DEVSEL V CCP STOP V CCP SERR V CCP PERR V CCP LOCK V CCP INTA INTB INTC V CCP CLKRUN V CCP PRST V CCP G_RST V CCP PME System dependent The pullup/p...
Page 28 - Table 1–5. Required Pullup/Pulldown Resistors
System Implementation 1-18 Table 1–5. Required Pullup/Pulldown Resistors Signal Resistor RecommendedValue ( Ω ) Condition LPS Pulldown (Default) 1.0 k Required Note: All pullup/pulldown resistor value recommendations are provided as guidelines only. The best value for an individualdesign varies depe...
Page 29 - BIOS Considerations; Initialization; PCI Standard Registers Initialization; PCI Local Bus Interface
System Implementation 1-19 PCI445X Device 1.4 BIOS Considerations 1.4.1 Initialization This section explains which registers require initialization, but does notdiscuss detailed information about the registers themselves. Refer to thecorresponding specifications. Reference white paper:http://www.mic...
Page 30 - If the system does not support V; PCI TI Proprietary Registers Initialization; GPIO3–GPIO0 control registers (PCI offset 88h; System Sleeping State Consideration
System Implementation 1-20 against unexpected overwriting. The values are system and vendordependent. PC Card 16-bit I/F legacy mode base address register (PCI offset 44h:32-bit) Set to 0000 03E1h (16-bit mode) and set to 0000 0001 (CardBus mode) inresponse to a disable call. Power management capabi...
Page 31 - ) Troubleshooting tips for sleep/resume issues; System hung up during resume; Docking System Consideration; C interface using an
System Implementation 1-21 PCI445X Device 2) Register save/restore Register content is not preserved in the sleeping state (it depends on thesystem implementation). Therefore, BIOS should restore the registercontent. Under Windows98, most of the register content is saved andrestored by the pci.vxd a...
Page 32 - Important Information; Serialized IRQ Data Stream
Important Information 1-22 1.5 Important Information This section clarifies important system implementation. 1.5.1 G_RST Clamping Rail G_RST is clamped to V CCP , so removing V CCP causes assertion of G_RST. Figure 1–7. G_RST and V CCP Relationship V CCP G_RST V CCP = 0 V CCP removed G_RST All other...
Page 33 - Appendix A
Global Reset Only Bits/PME Context Bits A-1 Global Reset Only Bits, PME Context Bits Global Reset Only Bits, PME Context Bits Topic Page A.1 Global Reset Only Bits/PME Context Bits A-2 Appendix A
Page 34 - A.1 Global Reset Only Bits/PME Context Bits; Table A–1. Global Reset Only Cleared Bits
Global Reset Only Bits/PME Context Bits A-2 A.1 Global Reset Only Bits/PME Context Bits Table A–1. Global Reset Only Cleared Bits Register Name Space Offset Bit Subsystem IDs PCI 40h 31–0 PC card 16-bit legacy mode base address PCI 44h 31–1 System control PCI 80h 31–29, 27–24, 22–14, 6–3,1–0 Multime...
Page 35 - Table A–2. PME Context Bits; Both G_RST and PRST can be gated by asserting the SUSPEND signal.
Global Reset Only Bits/PME Context Bits A-3 Global Reset Only Bits, PME Context Bits Table A–2. PME Context Bits Register Name Space Offset Bit Bridge control PCI 3Eh 6 Power management capabilities PCI A2h 15 Power management control/status PCI A4h 15, 8 ExCA power control ExCA 802h, 842h 4, 3, 1, ...
Page 37 - Appendix B
B-1 PME and RI Behavior PME and RI Behavior This appendix clarifies PME and RI signal behavior. These signals areimportant to support the wake-up event from a PC Card (CardBus and 16-bitcards.) Topic Page B.1 PME and RI Behavior B-2 Appendix B
Page 38 - B.1 PME and RI Behavior; Table B–1.CardBus CTSCHG and Wake-Up Signals Truth Table
B-2 B.1 PME and RI Behavior Table B–1.CardBus CTSCHG and Wake-Up Signals Truth Table RINGEN RIMUX RIENB PME_EN PME_STAT RI_OUT/PME MFUNC7 0 0 0 0 Latched ––– ––– 0 0 0 1 Latched Latched CSTSCHG ––– 0 0 1 0 Latched ––– ––– 0 0 1 1 Latched ––– ––– 0 1 0 0 Latched ––– ––– 0 1 0 1 Latched Latched CSTSCH...
Page 39 - Appendix C
PCI445X Buffer Types C-1 PCI445X Buffer Types PCI445X Buffer Types Topic Page C.1 PCI445X Buffer Types C-2 Appendix C
Page 40 - Table C–1. PCI445X Terminal Function Assignment and Buffer Types
PCI445X Buffer Types C-2 C.1 PCI445X Buffer Types Table C–1. PCI445X Terminal Function Assignment and Buffer Types Signal Name Terminal Type Signal Name Terminal Type A_CAD0 B8 TS A_CAD28 N2 TS A_CAD1 A7 TS A_CAD29 N3 TS A_CAD2 C8 TS A_CAD30 P1 TS A_CAD3 A6 TS A_CAD31 D9 TS A_CAD4 B7 TS A_CAUDIO M1 ...
Page 45 - Table C–2. Buffer Type Abbreviations
PCI445X Buffer Types C-7 PCI445X Buffer Types Table C–2. Buffer Type Abbreviations Buffer Type Description I/O Standard input/output I Standard input only O Standard output only OD Open drain P Power, GND, or clamp rail STS Sustained 3-state bidirectional. An active-low signal must be driven high fo...
