Texas Instruments MSP50C614 - Manual

Information About Cautions and Warnings v Read This First Unless the list is enclosed in square brackets, you must choose one itemfrom the list. - Some directives can have a varying number of parameters. For example,the .byte directive can have up to 100 parameters. The syntax for this di-rective is...

Contents vii Contents 1 Introduction to the MSP50C614 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features of the C614 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Contents viii 3.1.1 General-Purpose I/O Ports 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Dedicated Input Port F 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Dedicated Output Port G 3-5 ....

Contents ix Contents 4.4.8 Class 8 Instructions: Logic and Bit 4-41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.9 Class 9 Instructions: Miscellaneous 4-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Bit, Byte, Word and String Addressing 4...

Contents x 5.9.10 String Functions 5-45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.11 Constant Functions 5-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Implementation Details...

Contents xi Contents B.3.5 Host Write Sequence B-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.6 Host Read Sequence B-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.7 Interrupts B-7 . . . ....

Figures xii Figures 1–1 Functional Block Diagram for the C614 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Oscillator and PLL Connection 1-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 RESET Ci...

Tables xiv Tables 1–1 Signal and Pad Descriptions for the C614 1-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 MSP50C614 100-Pin PJM Plastic Package Pinout Description 1-11 . . . . . . . . . . . . . . . . . . . . . 2–1 Signed and Unsigned Integer Representation...

Notes, Cautions, and Warnings xvi Notes, Cautions, and Warnings MSP50C605 and MSP50C604 1-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGA Package 1-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

1-1 Introduction to the MSP50C614 The MSP50C614 (C614) is a low cost, mixed signal controller, that combinesa speech synthesizer, general-purpose I/O, onboard ROM, and directspeaker-drive in a single package. The computational unit utilizes a powerfulnew DSP which gives the C614 unprecedented speed ...

Functional Description 1-5 Introduction to the MSP50C614 1.4 Functional Description The device consists of a micro-DSP core, embedded program and datamemory, and a self-contained clock generation system. General-purpose pe-riphery is comprised of 64 bits of partially configurable I/O. The core proce...

C605 and C604 (Preliminary Information) 1-7 Introduction to the MSP50C614 Figure 1–1. Functional Block Diagram for the C614 SCANIN SYNC PLL OSCOUT OSCIN RESET DACM DACP PGMPULSE TEST SCANCLK SCANOUT Serial Comm. OTP Program Emulation Break Point (C614 only) (P614 only) DAC 0x30 32 Ohm PDM Initializa...

C605 and C604 (Preliminary Information) 1-8 Figure 1–2. Oscillator and PLL Connection MSP50P614 MSP50C614 OSCIN OSCOUT PLL C(PLL) = 3300 pF† 22 pF† 22 pF† 10 M Ω † 10 M Ω † 32.768 kHz† † Keep these components as close as possible to the OSCIN, OSCOUT, and PLL pins. a) Crystal Oscillator Operation Co...

C605 and C604 (Preliminary Information) 1-9 Introduction to the MSP50C614 Figure 1–3. RESET Circuit Reset Switch 1 µ F (20%) Inside the MSP50P614 MSP50C614 VDD VSS 100 k Ω IN914 5 V VPP To Pin 1 of Optional (Scanport)Connector RESET 1 k Ω † To Pin 2 of optional (scan port) connector† IN914‡ (MSP50P6...

Terminal Assignments and Signal Descriptions 1-10 1.6 Terminal Assignments and Signal Descriptions Table 1–1. Signal and Pad Descriptions for the C614 SIGNAL PAD NUMBER I/O DESCRIPTION Input/Output Ports PA0 – PA7 75 → 68 I/O Port A general-purpose I/O (1 Byte) PB0 – PB7 85 → 78 I/O Port B general-p...

Terminal Assignments and Signal Descriptions 1-13 Introduction to the MSP50C614 For software development and prototyping, a windowed ceramic 120-pin gridarray packaged P614 is available. The P614’s PGA package is shown inFigure 1–5 and Table 1–3: Figure 1–5. 120 Pin Grid Array Package for the Develo...

2-1 MSP50C614 Architecture A detailed description of MSP50C614 architecture is included in this chapter.After reading this chapter, the reader will have in-depth knowledge of internalblocks, memory organization, interrupt system, timers, clock control mecha-nism, and various low power modes. Topic P...

2-2 2.1 Architecture Overview The core processor in the C614 is a medium performance mixed signal pro-cessor with enhanced microcontroller features and a limited DSP instructionset. In addition to its basic multiply/accumulate structure for DSP routines, thecore provides for a very efficient handlin...

2-3 MSP50C614 Architecture Figure 2–1. MSP50C614 Core Processor Block Diagram Multiplier (MR)† Shift Value (SV)† 17 x 17 Multiplier Product High (PH)† 16 bit ALU MUX 32 Accumulators (AC0–AC31)† Column Exchange Loop (R4) Index (R5) Page (R6) Stack (R7) R0 R1 R2 R3 Arithmetic Unit MUX MUX Data Memory ...

Computation Unit 2-5 MSP50C614 Architecture 2.2 Computation Unit The computational unit (CU) is comprised of a (17-bit by 17-bit) Booth’salgorithm multiplier and a 16-bit arithmetic logic unit (ALU). The block diagramof the CU is shown in Figure 2–2. The multiplier block is served by 4 systemregiste...

Computation Unit 2-7 MSP50C614 Architecture Figure 2–3. Overview of the Multiplier Unit Operation MULTIPLIER UNIT INPUTS Multiplicand 16-bit - latched in a write-only registerfrom one of the following sources ... Data MemoryAccumulator Offset Accumulator X Multiplier - writeable and readable by Data...

Computation Unit 2-8 The all-zero values are necessary for data transfers and unitary operations.All-zeros also serve as default values for the registers, which helps to minimizeresidual power consumption. The databus path through ALU-A is used to inputmemory values (RAM) and constant values (progra...

Computation Unit 2-9 MSP50C614 Architecture Figure 2–4. Overview of the Arithmetic Logic Unit ALU INPUTS ALU-A 16-bit - selects between ... all 0’sOffset Accumulator Register Data Memory ALU-B 16-bit - selects between ... (PH) (PL) ARITHMETIC LOGIC UNIT performs arithmetic, comparison, and logic ALU...

Computation Unit 2-10 When writing an accumulator-referenced instruction, therefore, the workingaccumulator address is stored in one of AP0 to AP3. The C614 instruction setprovides a two-bit field for all accumulator referenced instructions. The two-bitfield serves as a reference to the accumulator ...

Data Memory Address Unit 2-11 MSP50C614 Architecture For some instructions, the 5-bit string processor can also preincrement orpredecrement the AP pointer-value by +1 or –1, before being used by theaccumulator register block. This utility can be effectively used to minimizesoftware overhead in manip...

Data Memory Address Unit 2-12 Figure 2–6. Data Memory Address Unit R3 R2 R1 R0 R7 R6 R5 R4 InternalDatabus Arithmetic Block RAM Address Internal Program Bus Register Addressing Mode STACK PAGE INDEX LOOP 2.3.1 RAM Configuration The data memory block (RAM) is physically organized into 17-bit parallel...

Data Memory Address Unit 2-13 MSP50C614 Architecture There are two-byte instructions, for example MOVB, which cause the proces-sor to read or write data in a byte (8-bit) format. (The B appearing at the endof MOVB designates it as an instruction, which uses byte-addressable argu-ments.) The byte-add...

Program Counter Unit 2-14 2.4 Program Counter Unit The program counter unit provides addressing for program memory (onboardROM). It includes a 16-bit arithmetic block for incrementing and loadingaddresses. It also consists of the program counter (PC), the data pointer (DP),a buffer register, a code ...

Memory Organization: RAM and ROM 2-15 MSP50C614 Architecture 2.6 Memory Organization: RAM and ROM Data memory (RAM) and program memory (ROM) are each restricted tointernal blocks on the C614. The program memory is read-only and limited to32K, 17-bit words. The lower 2048 of these words is reserved f...

Memory Organization: RAM and ROM 2-17 MSP50C614 Architecture When writing to any of the locations in the I/O address map, therefore, thebit-masking need only extend as far as width of location. Within a 16-bitaccumulator, the desired bits (width of location) should be right-justified. Thewrite opera...

Memory Organization: RAM and ROM 2-18 Table 2–2. Summary of C614’s Peripheral Communications Ports (Continued) I/O Map Address Width of Location Allowable Access Control Register Name Abbreviation State after RESET LOW Section for Reference 0x3A 16 bits read & write TIMER1 period PRD1 0x0000 2 8...

Memory Organization: RAM and ROM 2-19 MSP50C614 Architecture 3.1.5, Internal and External Interrupts, for more information regarding the specific conditions for each interrupt-trigger event. The branch operation,however, is also contingent on whether the interrupt service has been enabled.This is do...

Interrupt Logic 2-22 When the device is powered up, the hardware initialization circuit reads thevalue stored in the block protection word. The value is then loaded to an inter-nal register and the security state of the ROM is identified. Until this occurs,execution of any instructions is suspended....

Interrupt Logic 2-23 MSP50C614 Architecture the RESET low, assuming there is no interruption in power. For a fulldescription of the interrupt-trigger events, refer to Section 3.1.5, Internal and External Interrupts. (8-bit wide location) 07 06 05 04 03 02 01 00 ← INT number IFR Interrupt Flag regist...

Interrupt Logic 2-24 Note: Setting a Bit in the IFR Using the OUT Instruction Setting a bit within the IFR using the OUT instruction is a valid way of obtain-ing a software interrupt. An IFR bit may also be cleared, using OUT, at anytime. Assuming the global interrupt enable is set and the specific ...

Interrupt Logic 2-25 MSP50C614 Architecture Figure 2–8 provides an overview of the interrupt control sequence. INT0 is thehighest priority interrupt, and INT7 is the lowest priority interrupt. Figure 2–8. Interrupt Initialization Sequence INTD instruction CLEAR INTE instruction SET Global Interrupt ...

Timer Registers 2-26 In addition to being individually enabled, all interrupts must be GLOBALLYenabled before any one can be serviced. Whenever interrupts are globallydisabled, the interrupt flag register may still receive updates on pending triggerevents. Those trigger events, however, are not serv...

Timer Registers 2-27 MSP50C614 Architecture (16-bit wide location) 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRD1 register † address 0x3A P P P P P P P P P P P P P P P P TIMER1 Period TIM1 register † address 0x3B T T T T T T T T T T T T T T T T TIMER1 Count-Down Triggers INT1 on underflow PRD2...

Timer Registers 2-28 Selection between the timer-source options is made using two control bits inthe interrupt/general control register (IntGenCtrl). The IntGenCtrl is a 16-bitport-addressed register at 0x38. Clearing bit 8 selects 1/2 MC as the sourcefor TIMER1. Setting bit 8 selects the reference ...

Clock Control 2-29 MSP50C614 Architecture 2.9 Clock Control 2.9.1 Oscillator Options The C614 has two oscillator options available. Either option may be enabledusing the appropriate control bits in the clock speed control register(ClkSpdCtrl). The ClkSpdCtrl is described in Section 2.9.3, Clock Spee...

Clock Control 2-30 The maximum required CPU clock frequency for the C614 is 8 MHz over theentire V DD range. This rate applies to the speed of the core processor. Higher CPU clock frequencies may be achieved, but these are not qualified over thecomplete range of supply voltages in the guaranteed spe...

Clock Control 2-31 MSP50C614 Architecture Note: ClkSpdCtrl Bits 8 and 9 When bit 8 is set in the ClkSpdCtrl register, the crystal oscillator bit (bit 9) be-comes the least significant bit of the 6-bit resistor trim value. Thus, bits 15–11and 9 make up the 6-bit resistor trim value. For example, if t...

Clock Control 2-32 Bit 10 in the ClkSpdCtrl is idle state clock control. The level of deep-sleepgenerated by the IDLE instruction is partially controlled by this bit. When thisbit is cleared (default setting), the CPU Clock is stopped during the sleep, butthe MC remains running. When the idle state ...

Execution Timing 2-33 MSP50C614 Architecture However, the general specification of the adjustment can be useful in certaincircumstances. For example, the adjustment can be used to obtain a program-matic increase or decrease in the speed of the RTO reference. The default val-ue for the adjustment, af...

Reduced Power Modes 2-34 Figure 2–10. Instruction Execution and Timing N N+1 N+2 N+3 N+4 N+5 N+6 N+7 FETCH CLOCK N–1 N N+1 N+2 N+3 N+4 N+5 DECODE N–2 N–1 N N+1 N+2 N+3 N+4 N+5 EXEC N–1 N N+1 N+2 N+3 N+4 N+5 DATA ADD N N+1 N+2 N+3 N+4 N+5 N+6 N+7 PC ADD 2.11 Reduced Power Modes The power consumption ...

Reduced Power Modes 2-35 MSP50C614 Architecture The deepest sleep achievable on the C614, for example, is a mode where allof the previously listed subsytems are stopped. In this state, the device drawsless than 10 µ A of current and obtains the greatest power savings. It may be awakened from this st...

Reduced Power Modes 2-36 The power consumed during sleep when the RTO oscillator is left running isgreater than the power consumed during sleep when the CRO oscillator is leftrunning. If the idle state clock control is clear, then the PLL circuitry, active during sleep,will attempt to regulate the M...

Reduced Power Modes 2-37 MSP50C614 Architecture Table 2–3. Programmable Bits Needed to Control Reduced Power Modes → deeper sleep … relatively less power → Control Bit Label forControl Bit LIGHT MID DEEP Idle state clock control bit 10 ClkSpdCtrl register (0x3D) A 0 1 1 Enable reference oscillator...

Reduced Power Modes 2-38 Table 2–4. Status of Circuitry When in Reduced Power Modes (Refer to Table 2–3) → deeper sleep … relatively less power → Component Determined by Controls LIGHT MID DEEP CPU clock (processor core) E stopped stopped stopped PLL clock circuitry A, E running stopped stopped Ma...

Reduced Power Modes 2-40 In order to wake the device using a programmable interrupt, the interrupt maskregister must have the respective bit set to enable interrupt service (see Sec-tion 2.7, Interrupt Logic). In some cases, the ARM bit must also be set, in order for the interrupts to be visible dur...

3-1 Peripheral Functions This chapter describes in detail the MSP50C614 peripheral function, i.e., I/Ocontrol ports, general purpose I/O ports, interrupt control registers, compara-tor and digital-to-analog (DAC) control mechanisms. Topic Page 3.1 I/O . . . 3–2 . . . . . . . . . . . . . . . . . . . ...

I/O 3-2 3.1 I/O The C614 has 64 input-output pins. Forty of these are software configurable aseither inputs or outputs. Eight are dedicated inputs, and the remaining sixteenare dedicated outputs. 3.1.1 General-Purpose I/O Ports The forty configurable input/output pins are organized in 5 ports, A,B,C...

I/O 3-4 3.1.2 Dedicated Input Port F Port F is an 8-bit wide input-only port. The data presented to the input pin canbe read by referring to the appropriate bit in the F port data register, address0x28. This is done using the IN instruction, with the 0x28 address as anargument. The state of the F po...

I/O 3-5 Peripheral Functions 3.1.3 Dedicated Output Port G Port G is a 16-bit wide output-only port. The output drivers have a Totem-Poleconfiguration. The data driven by the output pin can be controlled by settingor clearing the appropriate bit in the G port Data register, address 0x2C. Thisis done...

I/O 3-7 Peripheral Functions Registers). INT1 and INT2 are high-priority, internal interrupts triggered by theunderflow conditions on TIMER1 and TIMER2, respectively. Please refer toSection 2.8, Timer Registers, for a full description of the TIMER controls and their underflow conditions. When proper...

Digital-to-Analog Converter (DAC) 3-9 Peripheral Functions DAC Control registerAddress 0x34 (4-bit wide location)03 02 01 00 Set DAC resolution to 8 bits:Set DAC resolution to 9 bits:Set DAC resolution to 10 bits: DM E 0 0DM E 0 1DM E 1 0 DM : Drive Mode selection (0 = C3x style : 1 = C5x style) E :...

Digital-to-Analog Converter (DAC) 3-10 style. Their selection is made at bit 3 of the DAC control register (0x34). TheC3x style is selected by clearing bit 3, and the C5x style is selected by settingbit 3. The default value of the selection is zero which yields the C3x style. The overflow bits appea...

Digital-to-Analog Converter (DAC) 3-11 Peripheral Functions For a given sampling rate and DAC resolution, the CPU clock rate may beincreased, if necessary, through the use of over-sampling. In the previousexample, an original sampling rate of 8 kHz and a PDM rate of 4 MHz wasused. A 2-times over-sam...

Comparator 3-15 Peripheral Functions bit is automatically CLEARed again if an INT6 event occurs at the same timethat the associated mask bit is SET (IntGenCtrl, address 0x38, bit 6). The latterindicates that the program vectoring associated with INT6 is enabled. (The flagbit is SET when the INT even...

Comparator 3-16 The comparator, along with all of its associated functions, is enabled by settingbit 15 of the interrupt/general control register (IntGenCtrl, address 0x38). Thedefault value of the register is zero: comparator disabled. Note: IntGenCtrl Register Bit 15 At the time that bit 15 in the...

Interrupt/General Control Register 3-17 Peripheral Functions 3.4 Interrupt/General Control Register The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped registerlocated at address 0x38. The primary component in the IntGenCtrl is the 8-bitinterrupt mask register (IMR). The service ...

Interrupt/General Control Register 3-18 The upper four bits in the IntGenCtrl have independent functions. Bit 12 is theenable bit for the pull-up resistors on input port F. Setting this bit engages all8 F-port pins with at least 100-k Ω pull-ups (see Section 3.1.2, Dedicated Input Port F) Bit 13 is ...

Hardware Initialization States 3-19 Peripheral Functions 3.5 Hardware Initialization States The RESET pin is configured at all times as an external interrupt. It providesfor a hardware initialization of the C614. When the RESET pin is held low, thedevice assumes a deep sleep state and various contro...

Hardware Initialization States 3-20 Note: Internal RAM State after Reset The RESET low will not change the state of the internal RAM, assuming thereis no interruption in power. This applies also to the interrupt flag register. Thesame applies to the states of the accumulators in the computational un...

Hardware Initialization States 3-21 Peripheral Functions Note: Stack Pointer Initialization The software stack pointer (R7) must be initialized by the programmer, sothat it points to some legitimate address in data memory (RAM). This mustbe done prior to any CALL or C CC instruction. If this is not ...

4-1 Assembly Language Instructions This chapter describes in detail about MSP50P614/MSP50C614 assemblylanguage. Instruction classes, addressing modes, instruction encoding andexplanation of each instruction is described. Topic Page 4.1 Introduction 4–2 . . . . . . . . . . . . . . . . . . . . . . . ....

Introduction 4-2 4.1 Introduction In this chapter each MSP50P614/MSP50C614 class of instructions isexplained in detail with examples and restrictions. Most instructions canindividually address bits, bytes, words or strings of words or bytes. Usableprogram memory is 30K by 17-bit wide and the entire ...

System Registers 4-4 It is recommended to avoid using the TOS register altogether in applicationsand leave its operation to development tools only. 4.2.6 Product High Register (PH) This register holds the upper 16 bits of the 32 bit result of a multiplication,multiply-accumulate, or shift operation....

System Registers 4-5 Assembly Language Instructions During accumulator read operations, both A n and offset An~ are fetched. Depending on the instruction, either or both registers may be used. In addition,some write operations allow either register to be selected. The accumulator block can also be u...

System Registers 4-6 value of the STACK register should be stored before use and restored afteruse. This register must point to the beginning of the stack in the RESETinitialization routine before any CALL instruction or maskable interrupts can beused. CALL instructions increment R7 by 2., RET instr...

Instruction Syntax and Addressing Modes 4-8 4.3 Instruction Syntax and Addressing Modes MSP50P614/MSP50C614 instructions can perform multiple operations perinstruction. Many instructions may have multiple source arguments. They canpremodify register values and can have only one destination. The addr...

Instruction Syntax and Addressing Modes 4-9 Assembly Language Instructions 4.3.2 Addressing Modes The addressing modes on the MSP50P614/MSP50C614 are immediate, di-rect, indirect with post modification, and three relative modes. The relativemodes are: - Relative to the INDEX or R5 register. The effe...

Instruction Syntax and Addressing Modes 4-10 Table 4–3. Rx Bit Description R x Operation 0 0 0 R0 0 0 1 R1 0 1 0 R2 0 1 1 R3 1 0 0 R4 or LOOP 1 0 1 R5 or INDEX 1 1 0 R6 or PAGE 1 1 1 R7 or STACK Table 4–4. Addressing Mode Bits and {adrs} Field Description Relative Repeat addressing mode encoding, ad...

Instruction Syntax and Addressing Modes 4-11 Assembly Language Instructions Table 4–5. MSP50P614/MSP50C614 Addressing Modes Summary ADDRESSING SYNTAX OPERATION Direct name [dest,] [src,] *dma16 [*2] [, next A]name *dma16 [*2] [,src] [, next A] Second word operand ( dma16) used directly as memory add...

Instruction Syntax and Addressing Modes 4-13 Assembly Language Instructions 4.3.3 Immediate Addressing The address of the memory location is encoded in the instruction word or theword following the opcode is the immediate value. Single word instructionstake one clock cycle and double word instructio...

Instruction Syntax and Addressing Modes 4-14 4.3.4 Direct Addressing Direct addressing always requires two instruction words. The second wordoperand is used directly as the memory address. The memory operand maybe a label or an expression. Syntax: name [dest,] [src,] *dma16 [* 2] [, next A]name *dma...

Instruction Syntax and Addressing Modes 4-15 Assembly Language Instructions 4.3.5 Indirect Addressing Indirect addressing uses one of 8 registers (R0...R7) to point memoryaddresses. The selected register can be post-modified. Modifications includeincrements, decrements, or increments by the value in...

Instruction Syntax and Addressing Modes 4-16 Example 4.3.12 MOV *R5++R5, A0~, ++A Refer to the initial processor state in Table 4–8 before execution of thisinstruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ isAC19. The contents of AC19 are stored in the data memory location in R5. ...

Instruction Syntax and Addressing Modes 4-17 Assembly Language Instructions Address + Rx (x = 0 – 7) Index Register (R5) Operand Example 4.3.17 AND A0, *R3+R5 Refer to the initial processor state in Table 4–8 before execution of this instruc-tion. A0 is accumulator AC2. The contents of the data memo...

Instruction Syntax and Addressing Modes 4-18 Example 4.3.20 MOV A3, *R6+0x10 Refer to the initial processor state in Table 4–8 before execution of this instruc-tion. Load A3 (AC29) with the contents of byte address, R6+0x10. The valueof R6 is unchanged. Final result, AC29=0x0112. Example 4.3.21 ADD ...

Instruction Syntax and Addressing Modes 4-19 Assembly Language Instructions 4.3.7 Flag Addressing This addressing mode addresses only the 17 th bit (the flag/tag bit) located in data memory. This addressing applies to Class 8a instructions as explainedin section 4.4. Using flag addressing, the flag ...

Instruction Syntax and Addressing Modes 4-20 4.3.8 Tag/Flag Bits The words TAG and flag may be used interchangeably in this manual. TheTAG bit is the 17 th bit of a word of data memory. There are 640 words of RAM, each 17 bits wide, on the C614. Therefore, there are 640 TAG bits on the C614.When an ...

Instruction Syntax and Addressing Modes 4-21 Assembly Language Instructions However, xFLAG instructions use {flagadrs} addressing modes. This includesglobal (dma6) and relative (R6 + 6–bit offset). Both take only one clock cycle. Possible sources of confusion: Consider the following code, ram0 equ 0...

Instruction Classification 4-22 4.4 Instruction Classification The machine level instruction set is divided into a number of classes. Theclasses are primarily divided according to field references associated withmemory, hardware registers, and control fields. The following descriptionsgive class-enc...

Instruction Classification 4-23 Assembly Language Instructions Table 4–11. Symbols and Explanation (Continued) Symbol Explanation next A Accumulator control bits as described in Table 4–6. [ next A] The preincrement (++A) or predecrement (– –A) operation on accumulator pointers A n or An~. Not NOT c...

Instruction Classification 4-25 Assembly Language Instructions Table 4–12. Classes and Opcode Definition Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class 1a 0 0 C1a ~A~ next A A n am R x pm Class 1b 0 1 C1b s A n am R x pm Class 2a 1 0 1 0 C2a A n imm8 Class 2b 1 1 1 0 0 next A A n C2b 0 0 1 A~ ~A...

Instruction Classification 4-26 Class 1a provides the four basic instructions of load, store, add, and subtractbetween accumulator and data memory. Either the accumulator or the offsetaccumulator (A~ bit dependent) can be stored in memory with the MOVinstruction. The MOV instruction can load the acc...

Instruction Classification 4-27 Assembly Language Instructions Table 4–15. Class 1b Instruction Description C1b Mnemonic Description 0 0 0 0 OR A n, {adrs} ORS A n, {adrs} Logical OR the contents of the data memory location in { adrs} and the selected accumulator. Result(s) stored inaccumulator(s). ...

Instruction Classification 4-28 Table 4–15. Class 1b Instruction Description (Continued) C1b Mnemonic Description 1 0 1 1 MULAPL A n, {adrs} MULAPLS A n, {adrs} Multiply the MR register by the addressing mode { adrs} and add the lower 16 bits of the product to the accumulator. Latch theupper 16 bits...

Instruction Classification 4-29 Assembly Language Instructions constants. Long constants (16 bits) and long string constants differ in that ref-erences are made to constants in the second word of the two-word instructionword. References made to a single 16 bit integer constant are immediate. Thatis,...

Instruction Classification 4-30 Table 4–18. Class 2b Instruction Description C2b Mnemonic Description 0 0 0 ADD A n[~], An[~], imm16 [, next A] ADDS A n[~], An[~], pma16 Add long constant to accumulator (or offset accumulator ifA~=1) and store result to accumulator (~A=0) or offsetaccumulator (~A=1)...

Instruction Classification 4-31 Assembly Language Instructions between the accumulator and the MR, SV, or PH register. As with all accumula-tor referenced instructions, string operations are possible as well as premodi-fication of one of 4 indirectly referenced accumulator pointer registers (AP). Ta...

Instruction Classification 4-34 Table 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 1 1 1 1 0 MUL A n[~] [, next A] MULS A n[~] Multiply MR register by accumulator (A~=1) or offsetaccumulator (A~=0) and latch the rounded upper 16 bits ofthe resulting product into the PH r...

Instruction Classification 4-36 4.4.5 Class 5 Instructions: Memory Reference Class 5 instructions provide transfer to and from data memory and all registersexcept accumulators and R x which are included in classes 1 and 4. The registers referenced for both read and write operations are the multiplie...

Instruction Classification 4-38 Table 4–27. Class 5 Instruction Description (Continued) C5 Mnemonic Description 1 1 1 1 0 RPT { adrs} 8 Load repeat counter with lower 8 bits of data memory location referred byaddressing mode { adrs}. Interrupts are queued during execution. 1 1 1 1 1 MOV STAT, { adrs...

Instruction Classification 4-39 Assembly Language Instructions Table 4–30. Class 6b Instruction Description C6b Mnemonic Description 0 IN A n[~], port6 INS A n[~], port6 Transfer the port’s 16 bit value to an accumulator. Port addresses 0–63are valid. ALU status is modified. 1 OUT port6, An[~] OUTS ...

Instruction Classification 4-40 Table 4–31. Class 7 Instruction Encoding and Description Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VCALL vector8 1 1 1 1 1 1 1 0 1 vector8 J cc 1 0 0 0 0 0 Not cc R x pm JMP *A n 1 0 0 0 1 0 x A n x C cc 1 0 0 0 0 1 Not cc x CALL *An 1 0 0 0 1 1 x A n x cc cc names...

Instruction Classification 4-41 Assembly Language Instructions Table 4–31. Class 7 Instruction Encoding and Description (Continued) cc cc names Description cc cc name Not cc name 1 0 1 0 1 Unconditional 1 0 1 1 0 Not assigned 1 0 1 1 1 Not assigned 1 1 0 0 0 XZ XNZ Conditional on XSF 1 1 0 0 1 XS XN...

Instruction Classification 4-42 Table 4–33. Class 8a Instruction Description C8a Mnemonic Description 0 0 0 MOV TF n, {flagadrs} Load flag bit (17 th bit) from data memory referred by flag addressing mode { flagadrs} to either TF1 or TF2 in status register. Load with inverted value if Not =1. 0 1 0 ...

Instruction Classification 4-43 Assembly Language Instructions Table 4–35. Class 9a Instruction Encoding Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class 9a 1 1 1 0 1 0 0 A n C9a 0 R x 1 1 Class 9b 1 1 1 1 1 1 0 C9a imm8 Class 9c 1 1 1 1 1 0 1 AP n 0 C9c x imm5 Class 9d 1 1 1 1 1 1 1 1 0 C9d 0 0 0...

Bit, Byte, Word and String Addressing 4-44 Table 4–38. Class 9c Instruction Description C9c Mnemonic Description 0 MOV AP n, imm6 Load the accumulator pointer (AP) with a five bit constant. 1 ADD AP n, imm5 Add a five bit constant imm5 to the referenced accumulator pointer(AP). Table 4–39. Class 9d ...

Bit, Byte, Word and String Addressing 4-45 Assembly Language Instructions is a string of bytes. The length of the byte string is stored in the string register(STR). To define the length of a string, the STR register should hold the lengthof the string minus 2. For example, if the length of a byte st...

Bit, Byte, Word and String Addressing 4-46 Flag address: The flag (or TAG) address uses linear addressing from 0 to thesize of data memory in 17 bit wide words (0 to 639 for MSP50P614/MSP50C614). Only the 17 th bit is accessible. When a word memory location is read, the corresponding flag for that l...

Bit, Byte, Word and String Addressing 4-47 Assembly Language Instructions Figure 4–4. Data Memory Example Absolute Word Memory Location Data Memory Location (even) = 2 * (Absolute word memory location) MS Byte LS Byte Data Memory Location (odd) 0x0000 0x0000 0x12 0x34 0x0001 0x0001 0x0002 0x56 0x78 ...

MSP50P614/MSP50C614 Computational Modes 4-49 Assembly Language Instructions Example 4.5.10 MOV STR, 0 SFLAG *0x00032 MOVS A0, *0x0031 * 2 RFLAG *0x00032 MOVS A0, *0x0031 * 2 Refer to Figure 4–4 for this example. This example is to illustrate the effect ofthe tag/flag bit when used with a string inst...

MSP50P614/MSP50C614 Computational Modes 4-50 Table 4–41. MSP50P614/MSP50C614 Computational Modes ComputationalMode SettingInstruction Resetting Instruction Function Sign extension SXM RXM STAT.XM = 1 produces sign extension on data as it ispassed into accumulators. This mode copies the 16 th bit of ...

MSP50P614/MSP50C614 Computational Modes 4-51 Assembly Language Instructions Example 4.6.2 SXM MOV STR, 2–2 ; string length=2 MOV MR, 0x8000 MOV A0, 0x8000, ++A ; load MS Byte MOV A0, 0x0000, ––A ; load LS Byte MULTPLS A0, A0 This example illustrates the sign extension mode on a string duringmultipli...

Hardware Loop Instructions 4-53 Assembly Language Instructions high word of the result is stored in the PH register and is 0x3FFF. The low wordis stored in A0~ as 0x0001. If the two numbers are considered as Q15 fraction-al numbers (all bits are to the right of the decimal point), then the result wi...

Hardware Loop Instructions 4-54 the execution of a string instruction, interrupts are queued. Queued interrupts are serviced according to their priority after the string operation is complete. In addition to repeat and string instructions, the combination of repeated stringinstructions has a very us...

String Instructions 4-55 Assembly Language Instructions 4.8 String Instructions Class 1, 2, 3, and 6 instructions can have string modes. During the executionof string instruction, STR register value plus 2 is assumed as string length. Anaccumulator string is a group of consecutive accumulators spann...

String Instructions 4-56 A1 string is 0x233EFBCA1223 and *0x200 = 0x9086EE3412AC. STR =3–2=1, defines a string length of 3. Final result, A1~ string =0x233EFBCA1223 + 0x9086EE3412AC = 0xB3C5E9FE24CF, AC5=0x24CF,AC6=0xE9FE, AC7=0xB3C5, STR=2 (unchanged). Notice that this instructionhas accumulated a ...

Lookup Instructions 4-57 Assembly Language Instructions 4.9 Lookup Instructions Table lookup instructions transfer data from program memory (ROM) to datamemory or accumulators. These instructions are useful for reading permanentROM data into the user program for manipulation. For example, lookup tab...

Lookup Instructions 4-58 Lookup instructions make use of the data pointer (DP) internally. The DPstores the address of the program memory location, loads the value to thedestination, and increments it automatically after every load. Thus, the valueof the DP is always the last used program memory add...

Input/Output Instructions 4-59 Assembly Language Instructions 4.10 Input/Output Instructions The MSP50P614/MSP50C614 processor communicates with other on-chiplogic as well as external hardware through a parallel I/O interface. Up to 40 I/Oports are addressable with instructions that provide bidirect...

Special Filter Instructions 4-61 Assembly Language Instructions theory requires). The second to last RAM location in the circular buffer is tagged using an STAG instruction. Below is an example of how to set up circu-lar buffering with FIR or COR. When using the FIR or COR instruction with circular ...

Special Filter Instructions 4-62 After the FIR or COR instruction executes, the new startOfBuff will be the last location in the circular buffer. After another FIR/COR instruction, the new startOfBuff will be the second to last location in the circular buffer, and so on. The second detail is the STA...

Special Filter Instructions 4-63 Assembly Language Instructions mov A0,*nextSample ;Replace last sample with newest sample mov *R0,A0 ; and update the start of the mov *startOfBuff,R0 ; circular buffer to here (R0) First, the overflow mode must be reset. Next, R5 must be loaded with the wrap around ...

Special Filter Instructions 4-64 Any combination of registers different from the above will yield incorrectresults with the FIR/COR instruction. Use R5 to wrap around R0 0x010 0x0100 0x0106 0x0102 x[k] x[k–1] x[k–2] x[k–3] tag After FIR/COR execution The STAT register is saved in the filterSTAT_tag ...

Special Filter Instructions 4-65 Assembly Language Instructions Important note about setting the STAT register It is very important to consider the initial value of the filterSTAT_tag variable.Failure to set up the filterSTAT_tag variable can cause incorrect results in FIR/COR operations. Overflow m...

Legend 4-70 4.13 Legend All instructions of the MSP50P614/MSP50C614 use the following syntax: name [dest] [, src] [, src1] [, mod] name Name of the instruction. Instruction names are shown in bold letter through out the text. dest Destination of the data to be stored after the execution of the instr...

Legend 4-73 Assembly Language Instructions Table 4–45. Auto Increment and Decrement Operation next A b9 b8 No modification 0 0 Auto increment ++A 0 1 Auto Decrement – –A 1 0 Table 4–46. Addressing Mode Bits and adrs Field Description String† Addressing Mode Encoding Relative Addressing Clocks Words ...

Individual Instruction Descriptions 4-74 4.14 Individual Instruction Descriptions In this section, individual instructions are discussed in detail. Use theconditionals in Section 4.12 and the legend in Section 4.13 to help withindividual instruction descriptions. Each instruction is discussed in det...

Individual Instruction Descriptions 4-75 Assembly Language Instructions 4.14.1 ADD Add word Syntax [ label] name dest, src [, src1] [,mod] Clock, clk Words, w With RPT, clk Class ADD A n[~], An, {adrs} [, next A] Table 4–46 Table 4–46 Table 4–46 1a ADD A n[~], An[~], imm16 [, next A] 2 2 N/R 2b ADD ...

Individual Instruction Descriptions 4-76 Description Syntax Description ADD dest, src ADD src with dest and store the result to dest. ADD dest, src, src1 [,mod] ADD src1 with src and store the result to dest. Premodify the mod before execution. (if provided) See Also ADDB, ADDS, SUB, SUBB, SUBS Exam...

Individual Instruction Descriptions 4-77 Assembly Language Instructions 4.14.2 ADDB ADD BYTE Syntax [ label] name dest, src Clock, clk Words, w With RPT, clk Class ADDB A n, imm8 1 1 N/R 2a ADDB R x, imm8 1 1 N/R 4b Execution dest ⇐ dest + src PC ⇐ PC + 1 Flags Affected dest is An: OF, SF, ZF, CF ar...

Individual Instruction Descriptions 4-78 4.14.3 ADDS Add String Syntax [ label] name dest, src, src1 Clock, clk Words, w With RPT, clk Class ADDS A n[~], An, {adrs} Table 4–46 Table 4–46 Table 4–46 1a ADDS A n[~], An[~], pma16 n S +4 2 N/R 2b ADDS A n[~], An~, An n S +2 1 n R +2 3 ADDS † A n[~], An[...

Individual Instruction Descriptions 4-80 4.14.4 AND Bitwise AND Syntax [label] name dest, src [, src1] [, mod] Clock, clk Word, w With RPT, clk Class AND A n, {adrs} Table 4–46 Table 4–46 1b AND A n[~], An[~], imm16 [, next A] 2 2 N/R 2b AND A n[~], An~, An [, next A] 1 1 n R +3 3 AND TF n, [!]{flag...

Individual Instruction Descriptions 4-81 Assembly Language Instructions See Also ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XORS Example 4.14.4.1 AND A3, *R4— – And word at address in R4 to A3, store result in A3. Decrement value in R4 by 2 (word mode) after theAND operation. Example 4.14.4.2 AND A0~, A0,...

Individual Instruction Descriptions 4-82 4.14.5 ANDB Bitwise AND Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class ANDB A n, imm8 1 1 N/R 2a Execution dest ⇐ dest AND src byte PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions 16 15 14 13 12 11 ...

Individual Instruction Descriptions 4-83 Assembly Language Instructions 4.14.6 ANDS Bitwise AND String Syntax [label] name dest, src [, src1] Clock, clk Word, w With RPT, clk Class ANDS A n, {adrs} Table 4–46 Table 4–46 1b ANDS A n[~], An[~], pma16 n R +4 1 N/R 2b ANDS A n[~], An~, An n R +3 1 n R +...

Individual Instruction Descriptions 4-84 4.14.7 BEGLOOP Begin Loop Syntax [label] name Clock, clk Word, w With RPT, clk Class BEGLOOP † 1 1 N/R 9d † Loop must end with ENDLOOP. Execution Save next instruction address (PC + 1)( mask interrupts) PC ⇐ PC + 1 Flags Affected none Opcode Instructions 16 1...

Individual Instruction Descriptions 4-85 Assembly Language Instructions 4.14.8 CALL Unconditional Subroutine Call Syntax [label] name address Clock, clk Word, w With RPT, clk Class CALL pma16 2 2 N/R 7c CALL *A n 2 1 N/R 7c Execution *R7 ⇐ TOS TOS ⇐ PC + 2 PC ⇐ pma16 or *An R7 ⇐ R7 + 2 Flags Affecte...

Individual Instruction Descriptions 4-86 4.14.9 C cc Conditional Subroutine Call Syntax [label] name address Clock, clk Word, w With RPT, clk Class C cc † pma16 2 2 N/R 7c † Cannot immediately follow a CALL instruction with a return instruction. If true If Not true [ label] [ label] [ label] [ label...

Individual Instruction Descriptions 4-87 Assembly Language Instructions Table 4–48. Names for cc cc cc names Description cc cc name Not cc name p True condition ( Not true condition) 0 0 0 0 0 Z NZ Conditional on ZF=1 ( Not condition ZF=0) 0 0 0 0 1 S NS Conditional on SF=1 ( Not condition SF=0) 0 0...

Individual Instruction Descriptions 4-88 Description If cc condition in Table 4–48 is true, PC + 2 is pushed onto the stack and the second word operand is loaded into the PC. If the condition is false, executiondefaults to a NOP. A C cc instruction cannot be followed by a return (RET) instruction. N...

Individual Instruction Descriptions 4-90 4.14.10 CMP Compare Two Words [label] name src, src1 [, mod] Clock, clk Word, w With RPT, clk Class CMP A n, {adrs} Table 4–46 Table 4–46 1b CMP A n[~], imm16 [, next A] 2 2 N/R 2b CMPCMP A n, An~ [, next A] A n~, An [, next A] 1 1 n R +3 3 CMP † R x, imm16 2...

Individual Instruction Descriptions 4-91 Assembly Language Instructions Example 4.14.10.3 CMP R2, 0xfe20 Compare value at R2 to immediate value 0xfe20 and change the STAT flags accordingly. Example 4.14.10.4 CMP R0, R5 Compare value at R0 to R5 and change the STAT flags accordingly.

Individual Instruction Descriptions 4-92 4.14.11 CMPB Compare Two Bytes Syntax [label] name src, src1 Clock, clk Word, w With RPT, clk Class CMPB A n, imm8 1 1 N/R 2a CMPB R x, imm8 1 1 N/R 4b Execution status flags set by src – src1 byte PC ⇐ PC + 1 Flags Affected src is An: OF, SF, ZF, CF are set ...

Individual Instruction Descriptions 4-93 Assembly Language Instructions 4.14.12 CMPS Compare Two Strings Syntax [ label] name src, src1 Clock, clk Word, w With RPT, clk Class CMPS A n, {adrs} Table 4–46 Table 4–46 1b CMPS A n[~], pma16 n S +4 2 N/R 2b CMPSCMPS A n, An~ A n~, An n S +3 1 n R +3 3 Exe...

Individual Instruction Descriptions 4-94 4.14.13 COR Correlation Filter Function Syntax [ label] name dest, src Clock, clk Word, w With RPT, clk Class COR A n, *Rx 3 1 3(n R +2) 9a Execution With RPT N–2:( mask interrupts) RPT counter = N–2MR = h[0] = first filter coefficient x = sample data pointed...

Individual Instruction Descriptions 4-95 Assembly Language Instructions 4.14.14 CORK Correlation Filter Function Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class CORK A n, *Rx 3 1 3(n R +2) 9a Execution With RPT N–2:( mask interrupts) RPT counter = N–2MR = h[0] = first filter coe...

Individual Instruction Descriptions 4-96 4.14.15 ENDLOOP End Loop Syntax [label] name # Clock, clk Word, w With RPT, clk Class ENDLOOP [ n] 1 1 N/R 9d Execution If (R4 ≥ 0) decrement R4 by n (1 or 2) PC ⇐ first address after BEGLOOP else NOP PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 ...

Individual Instruction Descriptions 4-97 Assembly Language Instructions 4.14.16 EXTSGN Sign Extend Word Syntax [label] name dest [, mod] Clock, clk Word, w With RPT, clk Class EXTSGN A n[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified] new most significant word of dest ⇐ STAT.SF ...

Individual Instruction Descriptions 4-98 4.14.17 EXTSGNS Sign Extend String Syntax [label] name dest Clock, clk Word, w With RPT, clk Class EXTSGNS A n[~] n R +3 1 n R +3 3 Execution new most significant word of dest ⇐ STAT.SF PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 ...

Individual Instruction Descriptions 4-99 Assembly Language Instructions MOV AP1, 3 ; Point to loc corresponding to ; extended word in acc MOVS A0, *R0 ; R0 POINTS TO VALUE IN MEMORY EXTSGN A1 ; not string version as above Alternatively, the following code can do the same thing but requires more code...

Individual Instruction Descriptions 4-100 4.14.18 FIR FIR Filter Function (Coefficients in RAM) Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class FIR A n, *Rx 2 1 2(n R +2) 9a Execution With RPT N–2:( mask interrupts) RPT counter = N–2MR = h[0] = first filter coefficient x = sampl...

Individual Instruction Descriptions 4-103 Assembly Language Instructions 4.14.20 IDLE Halt Processor Syntax [label] name Clock, clk Word, w With RPT, clk Class IDLE 1 1 N/R 9d Execution Stop processor clocksPC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Individual Instruction Descriptions 4-105 Assembly Language Instructions 4.14.22 INS Input From Port Into String Syntax [label] name src, src1 Clock, clk Word, w With RPT, clk Class INS A n[~], port6 n S +2 1 n R +2 6b Execution dest ⇐ content of port6 PC ⇐ PC + 1 Flags Affected dest is An: OF, SF, ...

Individual Instruction Descriptions 4-106 4.14.23 INTD Interrupt Disable Syntax [label] name Clock, clk Word, w With RPT, clk Class INTD 1 1 N/R 9d Execution STAT.IM ⇐ 0 (IM is STAT bit 4) PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTD 1 1 1 1 1 1 1...

Individual Instruction Descriptions 4-107 Assembly Language Instructions 4.14.24 INTE Interrupt Enable Syntax [label] name Clock, clk Word, w With RPT, clk Class INTE 1 1 N/R 9d Execution STAT.IM ⇐ 1 (IM is STAT bit 4) PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 ...

Individual Instruction Descriptions 4-108 4.14.25 IRET Return From Interrupt Syntax [label] name Clock, clk Word, w With RPT, clk Class IRET 2 1 N/R 5 Execution PC ⇐ TOS R7 ⇐ R7 – 2 TOS ⇐ *R7 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRET 1 1 0 1 1 1 1 0 1 0 1 ...

Individual Instruction Descriptions 4-112 Syntax Description AlternateInstruction JRNLZP pma16 [, Rmod] Conditional jump on R x ≥ 0 after post-mod JRZP pma16 [, Rmod] Conditional jump on R x = 0 after post-mod JRNZP pma16 [, Rmod] Conditional jump on R x ≠ 0 after post-mod JS pma16 [, Rmod] Conditio...

Individual Instruction Descriptions 4-113 Assembly Language Instructions 4.14.27 JMP Unconditional Jump Syntax [label] name dest [, mod] Clock, clk Word, w With RPT, clk Class JMP pma16 2 2 N/R 7b JMP pma16, Rx++ 2 2 N/R 7b JMP pma16, Rx– – 2 2 N/R 7b JMP pma16, Rx++R5 2 2 N/R 7b JMP *A n 2 1 N/R 7b...

Individual Instruction Descriptions 4-114 4.14.28 MOV Move Data Word From Source to Destination Syntax [label] name dest, src, [, next A] Clock, clk Word, w With RPT, clk Class MOV { adrs}, An[~] [, next A] Table 4–46 Table 4–46 1a MOV A n[~], {adrs} [, next A] Table 4–46 Table 4–46 1a MOV { adrs}, ...

Individual Instruction Descriptions 4-117 Assembly Language Instructions Description Copy value of src to dest. Premodification of accumulator pointers is allowed with some operand types. Syntax Description MOV A n[~], {adrs} [, next A] Move data memory word to A n[~] † MOV { adrs}, An[~] [, next A]...

Individual Instruction Descriptions 4-118 Syntax Description MOV STR, imm8 Move immediate byte to String Register (STR) MOV AP n, imm5 Move immediate 5-bit value to AP n register † Accumulator condition flags are modified to reflect the value loaded into either An or An~.‡ Signed multiplier mode res...

Individual Instruction Descriptions 4-119 Assembly Language Instructions Example 4.14.28.13 MOV R1, 0x0200 * 2 Load immediate word memory address 0x0200 to R1. Example 4.14.28.14 MOV R7, (0x0280 – 32) * 2 Load R7 (stack register) with the starting value of stack, i.e., 0x0260. Example 4.14.28.15 MOV...

Individual Instruction Descriptions 4-120 4.14.29 MOVAPH Move With Adding PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVAPH A n, MR, {adrs} Table 4–46 Table 4–46 1b Execution A n ⇐ A n + PH MR ⇐ contents of { adrs} PC ⇐ PC + w Flags Affected TAG, OF, SF, ZF, CF are...

Individual Instruction Descriptions 4-121 Assembly Language Instructions 4.14.30 MOVAPHS Move With Adding PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVAPHS A n, MR, {adrs} Table 4–46 Table 4–46 1b Execution A n ⇐ A n + PH MR ⇐ contents of { adrs} PC ⇐ PC + w Flags...

Individual Instruction Descriptions 4-122 4.14.31 MOVB Move Byte From Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVB A n, {adrs} Table 4–46 Table 4–46 1b MOVB { adrs}, An Table 4–46 Table 4–46 1b MOVB A n, imm8 1 1 N/R 2a MOVB MR, imm8 1 1 N/R 2a MOVB...

Individual Instruction Descriptions 4-123 Assembly Language Instructions Example 4.14.29.2 MOVB *R2, A0 Copy lower 8 bits of accumulator A0 to the data memory byte pointed by R2. Example 4.14.29.3 MOVB A0, 0xf2 Load accumulator A0 with value of 0xf2. Example 4.14.29.4 MOVB MR, 34 Load MR register wi...

Individual Instruction Descriptions 4-125 Assembly Language Instructions 4.14.33 MOVS Move String from Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVS A n[~], {adrs} Table 4–46 Table 4–46 1a MOVS { adrs}, An[~] Table 4–46 Table 4–46 1a MOVS { adrs}, *A...

Individual Instruction Descriptions 4-127 Assembly Language Instructions 4.14.34 MOVSPH Move With Subtract from PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVSPH A n, MR, {adrs} Table 4–46 Table 4–46 1b Execution A n ⇐ A n – PH MR ⇐ contents of { adrs} PC ⇐ PC + w ...

Individual Instruction Descriptions 4-128 4.14.35 MOVSPHS Move String With Subtract From PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVSPHS A n, MR, {adrs} Table 4–46 Table 4–46 1b Execution A n ⇐ A n (second word) – PH MR ⇐ contents of { adrs} PC ⇐ PC + w Flags Af...

Individual Instruction Descriptions 4-129 Assembly Language Instructions 4.14.36 MOVT Move Tag From Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVT { adrs}, TFn Table 4–46 Table 4–46 5 Execution dest ⇐ src PC ⇐ PC + w Flags Affected None Opcode Instruc...

Individual Instruction Descriptions 4-130 4.14.37 MOVU Move Data Unsigned Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class MOVU MR, A n[~] [, next A] 1 1 n R +3 3 MOVU MR, { adrs} Table 4–46 Table 4–46 5 Execution [premodify AP if mod specified] dest ⇐ src PC ⇐ PC + w Fla...

Individual Instruction Descriptions 4-132 4.14.38 MUL Multiply (Rounded) Syntax [label] name src [, mod] Clock, clk Word, w With RPT, clk Class MUL A n[~] [, next A] 1 1 n R +3 3 MUL { adrs} Table 4–46 Table 4–46 5 Execution [premodify AP if mod specified] PH,PL ⇐ MR * src PC ⇐ PC + w Flags Affected...

Individual Instruction Descriptions 4-133 Assembly Language Instructions 4.14.39 MULS Multiply String With No Data Transfer Syntax [label] name src Clock, clk Word, w With RPT, clk Class MULS A n [~] n S +3 1 n R +3 3 Execution PH,PL ⇐ MR * src string PC ⇐ PC + 1 Flags Affected None Opcode Instructi...

Individual Instruction Descriptions 4-134 4.14.40 MULAPL Multiply and Accumulate Result Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class MULAPL A n, {adrs} Table 4–46 Table 4–46 1b MULAPL A n[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified] PH,P...

Individual Instruction Descriptions 4-135 Assembly Language Instructions 4.14.41 MULAPLS Multiply String and Accumulate Result Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class MULAPLS A n, {adrs} Table 4–46 Table 4–46 1b MULAPLS A n[~], An[~] n S +3 1 n R +3 3 Execution P...

Individual Instruction Descriptions 4-136 4.14.42 MULSPL Multiply and Subtract PL From Accumulator Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class MULSPL A n, {adrs} Table 4–46 Table 4–46 1b MULSPL A n[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod spec...

Individual Instruction Descriptions 4-138 4.14.44 MULTPL Multiply and Transfer PL to Accumulator Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class MULTPL A n, {adrs} Table 4–46 Table 4–46 1b MULTPL A n[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specif...

Individual Instruction Descriptions 4-139 Assembly Language Instructions 4.14.45 MULTPLS Multiply String and Transfer PL to Acumulator Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MULTPLS A n, {adrs} Table 4–46 Table 4–46 1b MULTPLS A n[~], An[~] n S +3 1 n R +3 3 Execution P...

Individual Instruction Descriptions 4-140 4.14.46 NEGAC Two’s Complement Negation of Accumulator Syntax [label] name dest, src [,mod] Clock, clk Word, w With RPT, clk Class NEGAC A n[~], An[~] [, next A] n S +3 1 n R +3 3 Execution [premodify AP if mod specified] dest ⇐ – src PC ⇐ PC + 1 Flags Affec...

Individual Instruction Descriptions 4-141 Assembly Language Instructions 4.14.47 NEGACS Two’s Complement Negation of Accumulator String Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class NEGACS A n[~], An[~] n S +3 1 n R +3 3 Execution dest ⇐ – src PC ⇐ PC + 1 Flags Affected OF, SF...

Individual Instruction Descriptions 4-142 4.14.48 NOP No Operation Syntax [label] name Clock, clk Word, w With RPT, clk Class NOP 1 1 n R +3 9d Execution PC ⇐ PC + 1 (No operation) Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ...

Individual Instruction Descriptions 4-143 Assembly Language Instructions 4.14.49 NOTAC One’s Complement Negation of Accumulator Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class NOTAC A n[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified] dest ⇐ NO...

Individual Instruction Descriptions 4-144 4.14.50 NOTACS One’s Complement Negation of Accumulator String Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class NOTACS A n[~], An[~] n S +2 1 n R +2 3 Execution dest ⇐ NOT src PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly ...

Individual Instruction Descriptions 4-147 Assembly Language Instructions 4.14.52 ORB Bitwise OR Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class ORB A n, imm8 1 1 N/R 2a Execution dest ⇐ dest OR src PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instruc...

Individual Instruction Descriptions 4-149 Assembly Language Instructions 4.14.54 OUT Output to Port Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class OUT port4, {adrs} Table 4–46 n R +3 6a OUT port6, An[~] Table 4–46 n R +3 6a Execution port4 or port6 ⇐ src PC ⇐ PC + w Flags Affec...

Individual Instruction Descriptions 4-151 Assembly Language Instructions 4.14.56 RET Return From Subroutine (CALL, C cc) Syntax [label] name Clock, clk Word, w With RPT, clk Class RET 1 1 N/R 5 Execution PC ⇐ TOS R7 ⇐ R7 – 2 TOS ⇐ *R7 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 ...

Individual Instruction Descriptions 4-153 Assembly Language Instructions 4.14.58 RFM Reset Fractional Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class RFM 1 1 N/R 9d Execution STAT.FM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM ...

Individual Instruction Descriptions 4-154 4.14.59 ROVM Reset Overflow Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class ROVM 1 1 N/R 9d Execution STAT.OM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0...

Individual Instruction Descriptions 4-156 4.14.61 RTAG Reset Tag Syntax [label] name dest Clock, clk Word, w With RPT, clk Class RTAG { adrs} Table 4–46 Table 4–46 5 Execution memory tag bit at { adrs} data memory location ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 ...

Individual Instruction Descriptions 4-157 Assembly Language Instructions 4.14.62 RXM Reset Extended Sign Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class RXM 1 1 N/R 9d Execution STAT.XM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R...

Individual Instruction Descriptions 4-158 4.14.63 SFLAG Set Memory Flag Syntax [label] name dest Clock, clk Word, w With RPT, clk Class SFLAG { flagadrs} 1 1 N/R 8a Execution memory flag bit at { flagadrs} data memory location ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11...

Individual Instruction Descriptions 4-159 Assembly Language Instructions 4.14.64 SFM Set Fractional Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SFM 1 1 N/R 9d Execution STAT.FM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 ...

Individual Instruction Descriptions 4-160 4.14.65 SHL Shift Left Syntax [label] name dest [, mod] Clock, clk Word, w With RPT, clk Class SHL A n[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified] PH, PL ⇐ src << SV PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly...

Individual Instruction Descriptions 4-161 Assembly Language Instructions 4.14.66 SHLAC Shift Left Accumulator Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class SHLAC A n[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified] dest ⇐ src << 1 PC ⇐ ...

Individual Instruction Descriptions 4-162 4.14.67 SHLACS Shift Left Accumulator String Individually Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SHLACS A n[~], An[~] n S +2 1 n R +2 3 Execution dest ⇐ src << 1 PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingl...

Individual Instruction Descriptions 4-163 Assembly Language Instructions 4.14.68 SHLAPL Shift Left with Accumulate Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class SHLAPL A n, {adrs} Table 4–46 Table 4–46 1b SHLAPL A n[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodif...

Individual Instruction Descriptions 4-164 4.14.69 SHLAPLS Shift Left String With Accumulate Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SHLAPLS A n, {adrs} Table 4–46 Table 4–46 1b SHLAPLS A n[~], An[~] n S +3 1 n R +3 3 Execution PH, PL ⇐ src << SV dest ⇐ dest + PL PC...

Individual Instruction Descriptions 4-165 Assembly Language Instructions 4.14.70 SHLS Shift Left Accumulator String to Product Syntax [label] name dest Clock, clk Word, w With RPT, clk Class SHLS A n[~] n S +3 1 n R +3 3 Execution PH, PL ⇐ src << SV PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF ar...

Individual Instruction Descriptions 4-166 4.14.71 SHLSPL Shift Left With Subtract PL Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class SHLSPL A n, {adrs} Table 4–46 Table 4–46 1b SHLSPL A n[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified] PH, PL ...

Individual Instruction Descriptions 4-168 4.14.73 SHLTPL Shift Left and Transfer PL to Accumulator Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class SHLTPL A n, {adrs} Table 4–46 Table 4–46 1b SHLTPL A n[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod spec...

Individual Instruction Descriptions 4-170 4.14.75 SHRAC Shift Accumulator Right Syntax [label] name dest, src, [, mod] Clock, clk Word, w With RPT, clk Class SHRAC A n[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified] dest ⇐ src >> 1 PC ⇐ PC + 1 Flags Affected OF, SF,...

Individual Instruction Descriptions 4-171 Assembly Language Instructions 4.14.76 SHRACS Shift Accumulator String Right Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SHRACS A n[~], An[~] n S +3 1 n R +3 3 Execution dest ⇐ src >> 1 PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF...

Individual Instruction Descriptions 4-172 4.14.77 SOVM Set Overflow Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SOVM 1 1 N/R 9d Execution STAT.OM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOVM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 ...

Individual Instruction Descriptions 4-173 Assembly Language Instructions 4.14.78 STAG Set Tag Syntax [label] name dest Clock, clk Word, w With RPT, clk Class STAG { adrs} Table 4–46 Table 4–46 5 Execution memory tag bit at address adrs ⇐ 1 PC ⇐ PC + w Flags Affected None Opcode Instructions 16 15 14...

Individual Instruction Descriptions 4-174 4.14.79 SUB Subtract Syntax [label] name dest, src, src1, [next A]] Clock, clk Word, w With RPT, clk Class SUB A n[~], An, {adrs} [, next A] Table 4–46 Table 4–46 1a SUB A n[~], An[~], imm16 [, next A] 2 2 N/R 2b SUB A n[~], An[~], PH [, next A] 1 1 n R +3 3...

Individual Instruction Descriptions 4-176 4.14.80 SUBB Subtract Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SUBB A n, imm8 1 1 N/R 2a SUBB R x, imm8 1 1 N/R 4b Execution dest ⇐ dest – imm8 PC ⇐ PC + 1 Flags Affected dest is An: OF, SF, ZF, CF are set accordingly dest is...

Individual Instruction Descriptions 4-177 Assembly Language Instructions 4.14.81 SUBS Subtract Accumulataor String Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class SUBS A n[~], An, {adrs} Table 4–46 Table 4–46 1a SUBS A n[~], An[~], pma16 n s +4 2 N/R 32b SUBS A n[~], An, A...

Individual Instruction Descriptions 4-180 4.14.83 VCALL Vectored Call Syntax [label] name dest Clock, clk Word, w With RPT, clk Class VCALL vector8 2 1 N/R 7a Execution Push PC + 1PC ⇐ *(0x7F00 + vector8) R7 ⇐ R7 + 2 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VC...

Individual Instruction Descriptions 4-183 Assembly Language Instructions 4.14.85 XORB Logical XOR Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class XORB A n, imm8 1 1 N/R 2a Execution A n ⇐ A n XOR imm8 (for two operands) PC ⇐ PC + 1 Flags Affected dest is An: OF, SF, ZF, CF ...

Individual Instruction Descriptions 4-185 Assembly Language Instructions 4.14.87 ZAC Zero Accumulator Syntax [label] name dest [, mod] Clock, clk Word, w With RPT, clk Class ZAC A n[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified] dest ⇐ 0 PC ⇐ PC + 1 Flags Affected ZF = 1 Instru...

Individual Instruction Descriptions 4-186 4.14.88 ZACS Zero Accumulator String Syntax [label] name dest Clock, clk Word, w With RPT, clk Class ZAC A n n S +3 1 n R +3 3 Execution dest ⇐ 0 PC ⇐ PC + 1 Flags Affected ZF = 1 Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ZACS A n[~] 1 1 1 0 0 1 ...

Instruction Set Encoding 4-187 Assembly Language Instructions 4.15 Instruction Set Encoding Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADD A n[~], An, {adrs} [, next A] 1 1 1 0 ~A next A A n adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] ADD A n[~], An[~], imm16 ...

Instruction Set Encoding 4-188 Instructions 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CMP A n, {adrs} 0 1 0 1 1 0 0 A n adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] CMP A n[~], imm16 [, next A] 1 1 1 0 0 next A A n 0 1 1 0 0 1 A~ ~A x imm16 CMP A n, An~ [, next A] 1 1 1 0 ...

Instruction Set Summary 4-196 4.16 Instruction Set Summary Use the legend in Section 4.13 and the following table to obtain a summary ofeach instruction and its format. For detail about the instruction refer to thedetail description of the instruction. name dest [, src] [, src1] [,mod] Clock, clk Wo...

5-1 Code Development Tools For code development purposes, the programmable MSP50P614 is used.The MSP50C6xx code development tool is used to compile, link, and debugassembly language programs. This tool can also be used to program anMSP50P614. A reduced function C compiler, (called C– –) is also avai...

Introduction 5-2 5.1 Introduction The MSP50C6xx development tools gain access to the core controller via aserial scan interface called the Scanport. The basic elements needed to do de-velopment with the MSP50C6xx devices are listed below in Section 5.3. TheMSP50C6xx software development tool is incl...

MSP50C6xx Software Development Tool 5-3 Code Development Tools the reset circuit and the reset pin, and connecting the scanport reset signaldirectly to the reset pin. See the recommended reset circuit shown inFigure 1–3. It is also recommended that all production boards be built with the scanportint...

Requirements 5-4 5.3 Requirements The requirements for a complete MSP50C6xx development system are asfollows: PC Requirements: - Intel i486  or Pentium  class processor - Microsoft Windows  3.11, Windows 95  , or Windows 98  operating system - 16-MB memory - 8-MB hard disk space - Parallel port...

Hardware Installation 5-5 Code Development Tools 5.4 Hardware Installation The following steps are used to set up the hardware (see Figure 5–2): 1) Connect the 18 V power supply to the MSPSI and connect the mains pins to a 120 V, 60 Hz ac source. 2) Connect one end of the IEEE1284 parallel cable to ...

Software Installation 5-6 Figure 5–3. 10-Pin IDC Connector (top view looking at the board) IDC2X5M RESET VPP SCANCLK PGMPULSE SYNC GND N/C SCANIN VDD SCANOUT 1 3 5 7 9 2 4 6 8 10 PINOUT DETAILS 10-PIN HEADER (3M PART# 2510–60024B) LAYOUT DETAILS 0.1 I 0.800 I 0.1 I IDC2X5M HOLE DIA 0.038 I PAD DIA 0...

Software Installation 5-7 Code Development Tools Figure 5–5. Setup Window Step 2: After setup runs the InstallShield (see Figure 5–4), the setup window pops up (see Figure 5–5). Step 3: Press the Next > button to continue with installation or press Cancel to exit installation.

Software Installation 5-8 Figure 5–6. Exit Setup Dialog Step 4: If you press Cancel, you can return to setup by pressing Resume but- ton. You can exit setup by pressing Exit Setup button (Figure 5–6). Figure 5–7. User Information Dialog

Software Installation 5-9 Code Development Tools Step 5: If you continue with setup, you will be brought to User Information dialog. Enter your Name and Company Name in the two respective fields. To get into this screen, you must press yes to the licensescreen and press next to the Information dialo...

Software Installation 5-10 Figure 5–9. Select Program Folder Dialog Step 9: Enter a new folder name in Select Program Folder dialog. Step 10: Press Next > to continue with installation.

Software Installation 5-11 Code Development Tools Figure 5–10. Copying Files Step 11: The program starts installation. When the installation is complete, an icon is also created on the desktop.

Software Installation 5-12 Figure 5–11. Setup Complete Dialog Step 12: The Setup Complete dialog message is displayed when setup is completed. Press the Finish button to complete the installation.

Software Emulator 5-13 Code Development Tools 5.6 Software Emulator Run the EMUC6xx.exe program which will be in the installation directory or on your desktop (icon). Your scanport interface and the target board must beconnected and turned on before the emulator can be successfully used. If theopeni...

Software Emulator 5-14 Figure 5–13. Project Menu Figure 5–14. Project Open Dialog

Software Emulator 5-15 Code Development Tools Figure 5–15. File Menu Options 5.6.2 Projects The emulator can only work from project files created within the emulator itself.These files have the extension .rpj , and are not compatible with the .rpj files used in the old simulator. In other words, eve...

Software Emulator 5-16 ( pfe32.exe ) and an error dialog. The user can modify the source code and save the changes, before restarting the building action. 5.6.3 Description of Windows Once a new project is created or an old project is opened, the following sevenwindows pops open (Figure 5–16). Figur...

Software Emulator 5-17 Code Development Tools Figure 5–17. RAM Window RAM Window : Displays 16-bit data memory hex values. The left most columnis the address. Data memory is always addressable as bytes by MSP50C614instructions. Each value displayed in this window is actually two consecutivebyte data...

Software Emulator 5-18 Watch Window : Watch window displays the data memory location and datato be watched. It mirrors the value displayed in the RAM window. The Watchwindow is provided as a help to display locations that may not be visible in theRAM window without scrolling. See Ram Window above to...

Software Emulator 5-19 Code Development Tools being run in emulation mode. STK field is the depth of the stack. The emulatorkeeps track of number of calls and returns and changes this variableaccordingly. CUR field is the current subroutine name. In C–– programs itbecomes very handy to display local...

Software Emulator 5-20 background is the line reached by a search command (by PC, line number orlabel). Search position can also be set by double clicking on it in the programwindow. The line (if any) contain the hardware breakpoint is displayed in greenbackground. To set a hardware breakpoint, just...

Software Emulator 5-21 Code Development Tools variable value and its address in RAM are then displayed (Figure 5–21).Variables appearing on a gray background either are not defined, or are notactive at this time. The user can also use the Inspect option in the Debug menuto insert a variable in the I...

Software Emulator 5-22 modified (i.e, by double clicking on a value and typing its new hexadecimalvalue over the existing value). Values of read only registers cannot bemodified. Figure 5–23. I/O Ports Window Project Window : All source files making up the project are displayed in thiswindow. Only a...

Software Emulator 5-23 Code Development Tools Step Over : This menu option, (key equivalent: F8), allows the user to step over a call instruction in the program window. Note that the program windowdoes not need to have the focus to execute a Step instruction. If the Step Overinstruction leads into a...

Software Emulator 5-24 Fast Run : This menu option, (key equivalent: CTRL+F9), allows the user toexecute a portion of the program window, until a breakpoint is encountered.The windows are not refreshed until the program stops, so that the executionspeed is maximized. If no breakpoint is encountered,...

Software Emulator 5-25 Code Development Tools Figure 5–25. EPROM Programming Dialog

Software Emulator 5-26 Trace Mode : This menu option launches the Trace Mode Dialog(Figure 5–25), that allows that user to run the chip in trace mode, i.e., running an internal program on the chip while monitoring its execution on the scanport. Figure 5–26. Trace Mode Optional Trace Mode startprogra...

Software Emulator 5-27 Code Development Tools Stop Internal : This menu option halts execution of an internal program. Itprovides an internal picture of the chip at the time the internal programexecution was halted. Note that due to the asynchronous nature of this halt,one erroneous instruction may ...

Software Emulator 5-28 Init RAM : Initializes the data memory values to zero including tag bits. Init Registers : Initializes all the system registers (excluding accumulators)to zero except PC which is initialized to start vector. Init Accumulators : Initializes all the accumulators to zero. Init Al...

Software Emulator 5-29 Code Development Tools Figure 5–28. Options Menu Figure 5–29. Miscellaneous Dialog List of directories separated bysemicolons that the C–– compiler willsearch for include files enclosed in anglebrackets (<>) before searching currentdirectory. Heap start address for C–– c...

Software Emulator 5-30 Figure 5–30. Windows Menu Options 5.6.7 Emulator Online Help System The emulator has an online help which is launched when the Help menu option is left clicked with a mouse. The help window (Figure 5–30) is context sensitiveand graphical in nature. Any topic selected by pointi...

Software Emulator 5-31 Code Development Tools Figure 5–31. Context Sensitive Help System

Software Emulator 5-32 5.6.8 Known Differences, Incompatibilities, Restrictions - Include statements in assembly language files must enclose the file namein double quotes. - REF/DEF statements in assembly language files should be replaced withEXTERNAL/GLOBAL statements, but the old REF/DEF are still...

Assembler 5-33 Code Development Tools 5.7 Assembler The MSP50P614/MSP50C614 assembler is implemented as a Windows DLL(Dynamic Linked Library). 5.7.1 Assembler DLL The current name of the DLL file is asm6xx.dll . It can be invoked from any Windows program, provided that the user included the file cal...

Assembler 5-34 5.7.2 Assembler Directives Assembler directives are texts which have special meaning to the assembler.Some of these directives are extremely helpful during conditional compiling,debugging, adding additional features to existing codes, multiple hardwaredevelopment, code release etc. Ot...

Assembler 5-35 Code Development Tools symbol is any alphanumeric text starting with an alphabetic character, anumber, or an expression. Examples: SYM1 EQU (12 * 256) SYM2 EQU SYM1 * (32 / 4) SYM3 EQU SYM1 * SYM2 – *0x200 From the above example SYM1, SYM2 and SYM3 are symbols for some ex-pression. Th...

Assembler 5-36 Example: #IF expression; do something here#ELSE; do other things here#ENDIF #IFDEF symbol: Start of a conditional assembly structure. If symbol has beendefined (either with a #DEFINE directive or an EQU directive) then the linesfollowing this directive are assembled until a #ELSE or a...

Assembler 5-37 Code Development Tools BYTE expression[,expression]: Introduces one or more data items, of BYTEsize (8 bits) . The bytes are placed in the program memory in the order in whichthey are declared. CHIP_TYPE chip_name: This directive is here for compatibility with futurechips in the same ...

Linker 5-38 should be declared there as EXTERNAL (or REF). Note that this technique canalso be used to make constants defined with the EQU statement available toother files. INCLUDE filename: This directive is used to insert another file in the current assembly file. The name of the file to be inclu...

C– – Compiler 5-39 Code Development Tools The syntax of the call is: extern int FAR PASCAL LINK_MAIN (LPSTR source_file,LPSTRexe_file); ..... ierr=LINK_MAIN (source_file,exe_file); Where: - source_file is the project file name, which contains the names of the files to be linked. - exe_file is the na...

C– – Compiler 5-40 short ram_size; /* ram size for the chip */ short verbose; /* refers to assembly code output */ short c_code; /* if non zero, c code is included as */ /* assembly language comments */ short optimize; /* should always be non zero */ char dir_list; /* string of include directories s...

C– – Compiler 5-41 Code Development Tools 5.9.2 Variable Types Type Name Mnemonic Range Size in Bytes Example Integer int [–32768,32767] 2 int i,j; Character char [0,255] 1 char c,d; Array of integer int Not Applicable Not Applicable int array[12]; Array of characters char Not Applicable forced to e...

C– – Compiler 5-42 5.9.4 C– – Directives C– – has a limited number of directives and some additional directives notfound in ANSI C compilers. The following directives are recognized by thecompiler. 5.9.4.1 #define This directive is used to introduce 2 types of macros, in typical C fashion: Without A...

C– – Compiler 5-44 5.9.5 Include Files There are currently two include files supplied with C– –, cmm_func.h , which contains function prototypes for the C– –functions and cmm_macr.h which contains some predefined macros. Both files are listed below: /********************************/ /* Prototypes f...

C– – Compiler 5-45 Code Development Tools 5.9.6 Function Prototypes and Declarations As mentioned above,C– – function prototypes and declarations MUST be preceded with thekeyword cmm_func . Also, since all functions return through accumulator A0, all functions are oftype integer, so that the functio...

C– – Compiler 5-46 Table 5–1. String Functions add_string(int *result,int *str1,int *str2,int lg) adds strings str1 and str2, of length lg (+2), and puts the result in string result sub_string(int *result,int *str1,int *str2,int lg) subtracts strings str2 from str1, of length lg (+2), and puts the r...

C– – Compiler 5-47 Code Development Tools Also note that the user has to supply the length of the input string and the lengthof the output string in the string multiply operations: the result of multiplying astring by an integer can be one word longer than the input string. Unpredictableresults may ...

Implementation Details 5-48 5.10 Implementation Details This section is C– – specific. 5.10.1 Comparisons We use the CMP instruction for both signed and unsigned comparisons. Thetwo integers a and b to be compared are in A0 and A0~. CMP A0,A0~ : A0 contains a, A0~ contains b A0 A0~ ACO AZ ANEG 5 0 1...

Implementation Details 5-49 Code Development Tools - Unsigned comparison of a and b. (a is in A0, b is in A0~) Assembly Test Condition _ult a < b AULT _ule a <= b !AUGT _uge a >= b !AULT _ugt a > b AUGT The small number of comparisons was an invitation to use them as vectorcalls. We retu...

Implementation Details 5-50 5.10.2 Division The integer division currently requires the use of several accumulator pointers.We divide a 16 bit integer located in A0 by a 16 bit integer located in A0~. Wereturn the quotient in A0~, and the remainder in A0. We make use of A3~ andA3 for scratch pads. W...

Implementation Details 5-51 Code Development Tools Function declarations ( or function prototypes) are introduced by themnemonic cmm_func . We only allow the new style of function declarations /prototypes, where the type of the arguments is declared within the function’sparentheses. For example: cmm...

Implementation Details 5-52 constant int M1[4]={0x04CB,0x71FB,0x011F,0x0}; constant int M2[4]={0x85EB,0x8FD9,0x08FB,0x0}; cmm_func string_multiply(int *p,int lgp,int *m1,int lgm1,int *m2,int lgm2) { /* note: length of p,(lgp+2) must be at least (lgm1+2) + (lgm2+2) +1 */ /* this function string multi...

Implementation Details 5-54 find the correct size for bogus. Bogus can be made larger for extra safety aslong as enough memory is left over for the C– – variables and the stack. Ifspace allows, it is a good idea to add a few extra words to bogus in caseassembly variables are added to the project wit...

Implementation Details 5-59 Code Development Tools | | |––––––––––––––| | | |––––––––––––––| | | | | |––––––––––––––| | | |––––––––––––––| R7 |Return Addr | |––––––––––––––| |Return Addr | |––––––––––––––| |Param 2 | |––––––––––––––| |Param 2 | |––––––––––––––| |Param 1 | |––––––––––––––| |Param 1 |...

Beware of Stack Corruption 5-67 Code Development Tools 5.11 Beware of Stack Corruption MSP50C614/MSP50P614 stack (pointed by R7 register) can easily get cor-rupted if care is not taken. Notice the following table read code: SUBB R7, 4 MOV A0, *R7–– ADD A0, address MOV A0, *A0 ADD A0, *R7–– MOV A0, *...

6-1 Applications This chapter contains application information on application circuits, proces-sor initialization sequence, resistor trim setting, synthesis code, memory over-lays, and ROM usage. Topic Page 6.1 Application Circuits 6–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Application Circuits 6-2 6.1 Application Circuits To pin 2 of Scan Port Connector † MSP50C614/MSP50P614 To pin 1 of Scan Port Connector † (optional ) 5 V 0.1 µ F (5) R REFERENCE 470 k Ω (1%) 3300 pF OSC IN OSC OUT PLL DAC P DAC M V PP V DD 1N914 † 32 Ω RESET V SS 5 5 1 µ F 20% 1 k Ω † 100 k Ω 5 V 1N...

Application Circuits 6-3 Applications It is of particular importance to provide a separate decoupling capacitor for theV DD , V SS pair which services the DAC. These pins are pad numbers 21 and 19, respectively. The relatively high current demands of the digital-to-analogcircuitry make this a requir...

MSP50C614/MSP50P614 Initialization Codes 6-4 In any C614 application, it is important for certain components to be locatedas close as possible to the C614 die or package. These include any of thedecoupling capacitors at V DD (0.1 µ F). It also includes all of the components in the crystal-reference ...

MSP50C614/MSP50P614 Initialization Codes 6-5 Applications 6.2.1 File init.asm ;****************************************************************; INIT.ASM;;; Copyright: 1998 Texas Instruments, Inc. All rights reserved.;; –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––; This ...

Texas Instruments C614 Synthesis Code 6-8 6.3 Texas Instruments C614 Synthesis Code Some sample codes are supplied with the development tools. These samplesare in the .\Examples subdirectory where the tool is installed. In this manualonly one example code is explained. This description applies to al...

Texas Instruments C614 Synthesis Code 6-9 Applications To continue, click on the Run Internal icon again. The LEDs should flash duringMELP synthesis ( Extra, extra, read all about it) and should flash in a different pattern after MELP synthesis. Running the Program The MELP1 program can run on eithe...

Texas Instruments C614 Synthesis Code 6-11 Applications File Description Util.obj Maths functions and tables used by the vocoders. Dsputil.asm Oversampling and miscellaneous functions. Getbits.asm Routine to get data from ROM. Speak.asm Routines to speak a phrase or sentence. Dsp_var.irx Various voc...

Texas Instruments C614 Synthesis Code 6-13 Applications These files may be edited for special purpose code INIT.ASM and SPEAK.ASM These files should never be edited SLEEP.ASM, RAM.IRX and SPK_RAM.IRX A good rule of thumb to follow is that files under the DSP directory should beleft alone, and all cu...

ROM Usage With Respect to Various Synthesis Algorithms 6-14 6.4 ROM Usage With Respect to Various Synthesis Algorithms The following table lists some possible synthesis options and their ROMrequirements. The models assume that just enough program space, asnecessary for storage of the synthesis algor...

7-1 Customer Information Customer information regarding package configurations, development cycle,and ordering forms are included in this chapter. Topic Page 7.1 Mechanical Information 7–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Customer Information Fields...

Mechanical Information 7-2 7.1 Mechanical Information The C614 is normally sold in die form but is also available in 100-pin PJMpackages. The P614 is available in a windowed ceramic package, 120-pinPGA. NOTE: Scan Port Bond Out The Scan Port Interface on the MSP50C6xx devices has five dedicated pins...

Mechanical Information 7-3 Customer Information 7.1.2 Package Information The MSP50C614 will be available in the 100-pin PJM package (seeFigure 7–1 and Table 7–1). Contact your local TI sales office for more informa-tion. Table 7–1. MSP50C614 100-Pin PJM Plastic Package Pinout Description Descriptio...

Mechanical Information 7-4 Figure 7–1. 100-Pin PJM Mechanical Information 4040022 / B 03/95 0,16 NOM 14,20 17,45 13,80 16,95 50 51 31 30 12,35 TYP 1,030,73 0,25 Seating Plane 0,25 MIN Gage Plane 0,380,22 80 1 81 100 22,95 23,45 20,2019,80 2,50 2,90 3,40 MAX 18,85 TYP 0 ° – 7 ° M 0,13 0,65 0,10 NOTES...

Customer Information Fields in the ROM 7-7 Customer Information 7.2 Customer Information Fields in the ROM In those cases where the customer code is programmed by TexasInstruments, some registration of the code-release is provided within theROM. This information appears as 7 distinct fields within t...

Speech Development Cycle 7-8 7.3 Speech Development Cycle Figure 7–4. Speech Development Cycle Speech Specification Speaker Selection Recording Script Preparation Software Design Hardware Design Software Writing Prototype Construction Software Debugging System Evaluation Speech Recording Speech Anal...

Ordering Information 7-10 7.5 Ordering Information Because the MSP50C614 is a custom device, it receives a distinct identifica-tion, as follows: CSM Gate Code CSM: Custom Synthesizer With Memory 614 XXX X X Family Member ROM Code Revision Letter Package or Die PJM: Loopin QFP (Preliminary) Y: Die 7....

A-1 Appendix A MSP50C605 Preliminary Data This Appendix contains preliminary data for the MSP50C605 device. Note: MSP50C605 MSP50C605 is in the Product Preview stage of development. For more in-formation contact your local TI sales office. Topic Page A.1 Introduction A–2 . . . . . . . . . . . . . . ...

Architecture A-3 MSP50C605 Preliminary Data A.3.1 RAM The MSP50C605 (like MSP50C614) has 640 17-bit words of internal datamemory (static RAM). This RAM occupies a space extending from 0 to 0x27Fin the address space. A.3.2 ROM The MSP50C605 contains 32K by 17-bit words of internal program ROM and229,...

Architecture A-5 MSP50C605 Preliminary Data Figure A–2. MSP50C605 Memory Organization 0x0000 0x0800 0x07FF 0x7FF0 0x7FF7 User ROM 30704 x 17 bit (C605 : read–only) (P614 : EPROM) Internal Test Code 2048 x 17 bit (reserved ) Program Memory Peripheral Ports 0x 027F 0x 0000 Data Memory RAM 640 x 17 bit...

Architecture A-6 Figure A–3. MSP50C605 100-Pin PJM Package MSP50C605 100 PIN PJM PLASTIC PACKAGE 1 80 81 100 30 31 50 51

B-1 Appendix A MSP50C604 Preliminary Data This Appendix contains preliminary data for the MSP50C604 device. Note: MSP50C604 MSP50C604 is in the Product Preview stage of development. For more in-formation contact your local TI sales office. Topic Page B.1 Introduction B–2 . . . . . . . . . . . . . . ...

Architecture B-3 MSP50C604 Preliminary Data B.3.1 RAM The MSP50C604 (like MSP50C614) has 640 17–bit words of internal datamemory (static RAM). This RAM occupies a space extending from 0 to 0x27Fin the address space. B.3.2 ROM The MSP50C604 contains 32K by 17-bit words of internal program ROM. Thepro...

Architecture B-6 Figure B–2. MSP50C604 Memory Organization and I/O ports 0x0000 0x0800 0x07FF 0x7FF0 0x7FF7 User ROM 30704 x 17 bit (C604 : read–only) (P614 : EPROM) Internal Test Code 2048 x 17 bit (reserved ) Program Memory Peripheral Ports 0x 027F 0x 0000 Data Memory RAM 640 x 17 bit Macro Call V...

Architecture B-7 MSP50C604 Preliminary Data B.3.7 Interrupts Interrupts for MSP50C604 are the same as MSP50C614 in host mode exceptINT5 (port F interrupt) is not available. But in slave mode, INT3 and INT4 areexternal interrupts triggered by write sequence and read sequence as ex-plained before. A s...

Packaging B-8 B.4 Packaging The MSP50C604 is sold in die form. A 64 pin plastic package is also available. Table B–1. MSP50C604 64-Pin PJM Plastic Package Pinout Description Description Pin# Description Pin# Description Pin# Description Pin# VCC 1 NC 17 PC6 33 GND 49 VCC3 2 NC 18 PC5 34 NC 50 PD3 3 ...

C-1 Appendix A MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed-signal pro-cessor. Topic Page C.1 MSP50C605 Data Sheet C–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix C