Texas Instruments MSP430x4xx - Manual

Page 3 - Preface; Read This First; About This Manual; Program examples, are shown in a

Related Documentation From Texas Instruments iii Preface Read This First About This Manual This manual discusses modules and peripherals of the MSP430x4xx family ofdevices. Each discussion presents the module or peripheral in a generalsense. Not all features and functions of all modules or periphera...

Page 4 - Glossary

Glossary iv Glossary ACLK Auxiliary Clock See Basic Clock Module ADC Analog-to-Digital Converter BOR Brown-Out Reset See System Resets, Interrupts, and Operating Modes BSL Bootstrap Loader See www.ti.com/msp430 for application reports CPU Central Processing Unit See RISC 16-Bit CPU DAC Digital-to-An...

Page 5 - Register Bit Conventions; Key

Register Bit Conventions v Register Bit Conventions Each register is shown with a key indicating the accessibility of the eachindividual bit, and the initial condition: Register Bit Accessibility and Initial Condition Key Bit Accessibility rw Read/write r Read only r0 Read as 0 r1 Read as 1 w Write ...

Page 7 - Contents; Introduction

Contents vii Contents 1 Introduction 1-1 1.1 Architecture 1-2 1.2 Flexible Clock System 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Embedded Emulation 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Page 8 - Flash Memory Controller

Contents viii 3.3.5 Indirect Register Mode 3-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.6 Indirect Autoincrement Mode 3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.7 Immediate Mode 3-16 . . . . . . . . ....

Page 9 - Hardware Multiplier

Contents ix 7 Hardware Multiplier 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Hardware Multiplier Introduction 7-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Har...

Page 10 - 4 USART Peripheral Interface, UART Mode

Contents x 11 Basic Timer1 11-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Basic Timer1 Introduction 11-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11 - 5 USART Peripheral Interface, SPI Mode

Contents xi 15 USART Peripheral Interface, SPI Mode 15-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1 USART Introduction: SPI Mode 15-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 USART Operation: SPI Mode...

Page 14 - This chapter describes the architecture of the MSP430.; Topic; Architecture; Chapter 1

1-1 Introduction Introduction This chapter describes the architecture of the MSP430. Topic Page 1.1 Architecture 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Flexible Clock System 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Page 15 - Flexible Clock System

Architecture 1-2 Introduction 1.1 Architecture The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clocksystem that interconnect using a von-Neumann common memory addressbus (MAB) and memory data bus (MDB). Partnering a modern CPU withmodular memory-mapped analog and digital perip...

Page 16 - Embedded Emulation; The benefits of embedded emulation include:

Embedded Emulation 1-3 Introduction Figure 1−1. MSP430 Architecture ACLK Bus Conv. Peripheral MAB 16-Bit MDB 16-Bit MCLK SMCLK Clock System Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Watchdog RAM Flash/ RISC CPU 16-Bit JT AG/Debug ACLK SMCLK ROM MDB 8-Bit JTAG 1.3 Embedded Emu...

Page 17 - Address Space; Figure 1−2. Memory Map; RAM

Address Space 1-4 Introduction 1.4 Address Space The MSP430 von-Neumann architecture has one address space shared withspecial function registers (SFRs), peripherals, RAM, and Flash/ROM memoryas shown in Figure 1−2. See the device-specific data sheets for specificmemory maps. Code access are always p...

Page 18 - Peripheral Modules; Organized Memory

Address Space 1-5 Introduction 1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address spacefrom 0100 to 01FFh is reserved for 16-bit peripheral modules. These modulesshould be accessed with word instructions. If byte instructions are used, onlyeven addresses are p...

Page 19 - System Resets, Interrupts, and Operating Modes; and Operating Modes; System Reset and Initialization; Chapter 2

2-1 System Resets, Interrupts, and Operating Modes System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x4xx system resets, interrupts, andoperating modes. Topic Page 2.1 System Reset and Initialization 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 21 - Figure 2−2. Brownout Timing

System Reset and Initialization 2-3 System Resets, Interrupts, and Operating Modes 2.1.1 Brownout Reset (BOR) All MSP430x4xx devices have a brownout reset circuit. The brownout resetcircuit detects low supply voltages such as when a supply voltage is appliedto or removed from the V CC terminal. The ...

Page 22 - Device Initial Conditions After System Reset; After a POR, the initial MSP430 conditions are:; Software Initialization; Initialize the SP, typically to the top of RAM.

System Reset and Initialization 2-4 System Resets, Interrupts, and Operating Modes 2.1.2 Device Initial Conditions After System Reset After a POR, the initial MSP430 conditions are: - The RST/NMI pin is configured in the reset mode. - I/O pins are switched to input mode as described in the Digital I...

Page 23 - Interrupts; There are three types of interrupts:; Figure 2−3. Interrupt Priority

System Reset and Initialization 2-5 System Resets, Interrupts, and Operating Modes 2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of themodules in the connection chain as shown in Figure 2−3. The nearer a moduleis to the CPU/NMIRS, the higher the priority. Interrupt...

Page 24 - An edge on the RST/NMI pin when configured in NMI mode; Modifying WDTNMIES

System Reset and Initialization 2-6 System Resets, Interrupts, and Operating Modes 2.2.1 (Non)-Maskable Interrupts (NMI) (Non)-maskable NMI interrupts are not masked by the general interrupt enablebit (GIE), but are enabled by individual interrupt enable bits (ACCVIE, NMIIE,OFIE). When a NMI interru...

Page 26 - Oscillator Fault

System Reset and Initialization 2-8 System Resets, Interrupts, and Operating Modes Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystaloscillator. The oscillator fault can be enabled to generate an NMI interrupt bysetting the OFIE bit. The OFIFG flag can ...

Page 27 - Example of an NMI Interrupt Handler; Figure 2−5. NMI Interrupt Handler; Enabling NMI Interrupts with ACCVIE, NMIIE, and OFIE; RETI; Maskable Interrupts

System Reset and Initialization 2-9 System Resets, Interrupts, and Operating Modes Example of an NMI Interrupt Handler The NMI interrupt is a multiple-source interrupt. An NMI interrupt automaticallyresets the NMIIE, OFIE and ACCVIE interrupt-enable bits. The user NMIservice routine resets the inter...

Page 28 - Interrupt Processing; ) Any currently executing instruction is completed.; Figure 2−6. Interrupt Processing

System Reset and Initialization 2-10 System Resets, Interrupts, and Operating Modes Each individual peripheral interrupt is discussed in the associated peripheralmodule chapter in this manual. 2.2.3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interruptena...

Page 29 - Return From Interrupt; The interrupt handling routine terminates with the instruction:; (return from an interrupt service routine); Figure 2−7. Return From Interrupt

System Reset and Initialization 2-11 System Resets, Interrupts, and Operating Modes Return From Interrupt The interrupt handling routine terminates with the instruction: RETI (return from an interrupt service routine) The return from the interrupt takes 5 cycles to execute the following actionsand i...

Page 30 - Interrupt Vectors; Reset

System Reset and Initialization 2-12 System Resets, Interrupts, and Operating Modes 2.2.4 Interrupt Vectors The interrupt vectors and the power-up starting address are located in theaddress range 0FFFFh − 0FFE0h as described in Table 2−1. A vector isprogrammed by the user with the 16-bit address of ...

Page 31 - The operating modes take into account three different needs:

Operating Modes 2-13 System Resets, Interrupts, and Operating Modes 2.3 Operating Modes The MSP430 family is designed for ultralow-power applications and usesdifferent operating modes shown in Figure 2−9. The operating modes take into account three different needs: - Ultralow-power - Speed and data ...

Page 32 - Figure 2−9. MSP430x4xx Operating Modes For Basic Clock System; OSCOFF; Active

Operating Modes 2-14 System Resets, Interrupts, and Operating Modes Figure 2−9. MSP430x4xx Operating Modes For Basic Clock System Active Mode CPU Is Active Peripheral Modules Are Active LPM0 CPU Off, FLL+ On, MCLK On, ACLK On CPUOFF = 1 SCG0 = 0SCG1 = 0 CPUOFF = 1 SCG0 = 1SCG1 = 0 LPM2 CPU Off, FLL+...

Page 33 - Entering and Exiting Low-Power Modes; Enter interrupt service routine:; Extended Time in Low-Power Modes

Operating Modes 2-15 System Resets, Interrupts, and Operating Modes 2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-poweroperating modes. The program flow is: - Enter interrupt service routine: J The PC and SR are stored on the stack J The C...

Page 34 - Principles for Low; A typical with both a real-time clock function and; Connection of Unused Pins; The correct termination of all unused pins is listed in Table 2−2.; Table 2−2. Connection of Unused Pins

Principles for Low - Power Applications 2-16 System Resets, Interrupts, and Operating Modes 2.4 Principles for Low - Power Applications Often, the most important factor for reducing power consumption is using theMSP430’s clock system to maximize the time in LPM3. LPM3 powerconsumption is less than 2...

Page 35 - CPU Introduction; Chapter 3

3-1 RISC 16-Bit CPU This chapter describes the MSP430 CPU, addressing modes, and instructionset. Topic Page 3.1 CPU Introduction 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 CPU Registers 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Page 37 - Figure 3−1. CPU Block Diagram

CPU Introduction 3-3 RISC 16-Bit CPU Figure 3−1. CPU Block Diagram 0 15 MDB − Memory Data Bus Memory Address Bus − MAB 16 Zero, ZCarry, COverflow, VNegative, N 16−bit ALU dst src R8 General Purpose R9 General Purpose R10 General Purpose R11 General Purpose R12 General Purpose R13 General Purpose R14...

Page 38 - CPU Registers; Figure 3−2. Program Counter; MOV

CPU Registers 3-4 RISC 16-Bit CPU 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 havededicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to beexecuted. E...

Page 39 - Figure 3−4 shows stack usage.; Figure 3−3. Stack Pointer; Figure 3−4. Stack Usage

CPU Registers 3-5 RISC 16-Bit CPU 3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addressesof subroutine calls and interrupts. It uses a predecrement, postincrementscheme. In addition, the SP can be used by software with all instructions andaddressing modes....

Page 40 - Figure 3−6. Status Register Bits; Table 3−1 describes the status register bits.; Table 3−1. Description of Status Register Bits; Bit

CPU Registers 3-6 RISC 16-Bit CPU 3.2.3 Status Register (SR) The status register (SR/R2), used as a source or destination register, can beused in the register mode only addressed with word instructions. The remain-ing combinations of addressing modes are used to support the constant gen-erator. Figu...

Page 41 - Constant Generator Registers CG1 and CG2; Table 3−2. Values of Constant Generators CG1, CG2; Register; Register mode; The constant generator advantages are:; Constant Generator − Expanded Instruction Set

CPU Registers 3-7 RISC 16-Bit CPU 3.2.4 Constant Generator Registers CG1 and CG2 Six commonly-used constants are generated with the constant generatorregisters R2 and R3, without requiring an additional 16-bit word of programcode. The constants are selected with the source-register addressing modes(...

Page 42 - General−Purpose Registers R4 - R15

CPU Registers 3-8 RISC 16-Bit CPU 3.2.5 General−Purpose Registers R4 - R15 The twelve registers, R4−R15, are general-purpose registers. All of theseregisters can be used as data registers, address pointers, or index values andcan be accessed with byte or word instructions as shown in Figure 3−7. Fig...

Page 43 - Addressing Modes; Table 3−3. Source/Destination Operand Addressing Modes; Addressing Mode

Addressing Modes 3-9 RISC 16-Bit CPU 3.3 Addressing Modes Seven addressing modes for the source operand and four addressing modesfor the destination operand can address the complete address space with noexceptions. The bit numbers in Table 3−3 describe the contents of the As(source) and Ad (destinat...

Page 44 - Register Mode; The register mode is described in Table 3−4.; Table 3−4. Register Mode Description; Assembler Code; One or two words; PC; Data in Registers

Addressing Modes 3-10 RISC 16-Bit CPU 3.3.1 Register Mode The register mode is described in Table 3−4. Table 3−4. Register Mode Description Assembler Code Content of ROM MOV R10,R11 MOV R10,R11 Length: One or two words Operation: Move the content of R10 to R11. R10 is not affected. Comment: Valid fo...

Page 45 - Indexed Mode; The indexed mode is described in Table 3−5.; Table 3−5. Indexed Mode Description; Two or three words

Addressing Modes 3-11 RISC 16-Bit CPU 3.3.2 Indexed Mode The indexed mode is described in Table 3−5. Table 3−5. Indexed Mode Description Assembler Code Content of ROM MOV 2(R5),6(R6) MOV X(R5),Y(R6) X = 2 Y = 6 Length: Two or three words Operation: Move the contents of the source address (contents o...

Page 46 - Symbolic Mode; The symbolic mode is described in Table 3−6.; Table 3−6. Symbolic Mode Description

Addressing Modes 3-12 RISC 16-Bit CPU 3.3.3 Symbolic Mode The symbolic mode is described in Table 3−6. Table 3−6. Symbolic Mode Description Assembler Code Content of ROM MOV EDE,TONI MOV X(PC),Y(PC) X = EDE − PC Y = TONI − PC Length: Two or three words Operation: Move the contents of the source addr...

Page 47 - Absolute Mode; The absolute mode is described in Table 3−7.; Table 3−7. Absolute Mode Description

Addressing Modes 3-13 RISC 16-Bit CPU 3.3.4 Absolute Mode The absolute mode is described in Table 3−7. Table 3−7. Absolute Mode Description Assembler Code Content of ROM MOV &EDE,&TONI MOV X(0),Y(0) X = EDE Y = TONI Length: Two or three words Operation: Move the contents of the source addres...

Page 48 - Indirect Register Mode; The indirect register mode is described in Table 3−8.; Table 3−8. Indirect Mode Description

Addressing Modes 3-14 RISC 16-Bit CPU 3.3.5 Indirect Register Mode The indirect register mode is described in Table 3−8. Table 3−8. Indirect Mode Description Assembler Code Content of ROM MOV @R10,0(R11) MOV @R10,0(R11) Length: One or two words Operation: Move the contents of the source address (con...

Page 49 - Indirect Autoincrement Mode; The indirect autoincrement mode is described in Table 3−9.; Table 3−9. Indirect Autoincrement Mode Description; Figure 3−8. Operand Fetch Operation

Addressing Modes 3-15 RISC 16-Bit CPU 3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 3−9. Table 3−9. Indirect Autoincrement Mode Description Assembler Code Content of ROM MOV @R10+,0(R11) MOV @R10+,0(R11) Length: One or two words Operation: Move the contents ...

Page 50 - Immediate Mode; The immediate mode is described in Table 3−10.; Table 3−10. Immediate Mode Description; Valid only for a source operand.

Addressing Modes 3-16 RISC 16-Bit CPU 3.3.7 Immediate Mode The immediate mode is described in Table 3−10. Table 3−10. Immediate Mode Description Assembler Code Content of ROM MOV #45h,TONI MOV @PC+,X(PC) 45 X = TONI − PC Length: Two or three wordsIt is one word less if a constant of CG1 or CG2 can b...

Page 51 - Instruction Set; Destination Address

Instruction Set 3-17 RISC 16-Bit CPU 3.4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24emulated instructions. The core instructions are instructions that have uniqueop-codes decoded by the CPU. The emulated instructions are instructions thatmake code easi...

Page 52 - Figure 3−9. Double Operand Instruction Format; Table 3−11. Double Operand Instructions; Mnemonic; Instructions; CMP

Instruction Set 3-18 RISC 16-Bit CPU 3.4.1 Double-Operand (Format I) Instructions Figure 3−9 illustrates the double-operand instruction format. Figure 3−9. Double Operand Instruction Format B/W D-Reg 15 0 Op-code Ad S-Reg 8 7 14 13 12 11 10 9 6 5 4 3 2 1 As Table 3−11 lists and describes the double ...

Page 53 - Figure 3−10. Single Operand Instruction Format; Table 3−12. Single Operand Instructions; CALL

Instruction Set 3-19 RISC 16-Bit CPU 3.4.2 Single-Operand (Format II) Instructions Figure 3−10 illustrates the single-operand instruction format. Figure 3−10. Single Operand Instruction Format B/W D/S-Reg 15 0 Op-code 8 7 14 13 12 11 10 9 6 5 4 3 2 1 Ad Table 3−12 lists and describes the single oper...

Page 54 - Jumps; Figure 3−11 shows the conditional-jump instruction format.; Figure 3−11. Jump Instruction Format; Table 3−13 lists and describes the jump instructions.; Table 3−13. Jump Instructions

Instruction Set 3-20 RISC 16-Bit CPU 3.4.3 Jumps Figure 3−11 shows the conditional-jump instruction format. Figure 3−11. Jump Instruction Format C 10-Bit PC Offset 15 0 Op-code 8 7 14 13 12 11 10 9 6 5 4 3 2 1 Table 3−13 lists and describes the jump instructions. Table 3−13. Jump Instructions Mnemon...

Page 67 - Clear zero bit

Instruction Set 3-33 RISC 16−Bit CPU * CLRZ Clear zero bit Syntax CLRZ Operation 0 → Z or(.NOT.src .AND. dst −> dst) Emulation BIC #2,SR Description The constant 02h is inverted (0FFFDh) and logically ANDed with thedestination operand. The result is placed into the destination. The clear zerobit ...

Page 71 - Figure 3−12. Decrement Overlap; EDE

Instruction Set 3-37 RISC 16−Bit CPU * DEC[.W] Decrement destination * DEC.B Decrement destination Syntax DEC dst or DEC.W dst DEC.B dst Operation dst − 1 −> dst Emulation SUB #1,dst Emulation SUB.B #1,dst Description The destination operand is decremented by one. The original contents arelost. S...

Page 82 - Jump unconditionally; Syntax; JMP; Operation; Status bits are not affected.

Instruction Set 3-48 RISC 16−Bit CPU JMP Jump unconditionally Syntax JMP label Operation PC + 2 × offset −> PC Description The 10-bit signed offset contained in the instruction LSBs is added to theprogram counter. Status Bits Status bits are not affected. Hint: This one-word instruction replaces ...

Page 91 - Figure 3−13. Main Program Interrupt

Instruction Set 3-57 RISC 16−Bit CPU RETI Return from interrupt Syntax RETI Operation TOS → SR SP + 2 → SP TOS → PC SP + 2 → SP Description The status register is restored to the value at the beginning of the interruptservice routine by replacing the present SR contents with the TOS contents.The sta...

Page 92 - Figure 3−14. Destination Operand—Arithmetic Shift Left

Instruction Set 3-58 RISC 16−Bit CPU * RLA[.W] Rotate left arithmetically * RLA.B Rotate left arithmetically Syntax RLA dst or RLA.W dst RLA.B dst Operation C <− MSB <− MSB−1 .... LSB+1 <− LSB <− 0 Emulation ADD dst,dst ADD.B dst,dst Description The destination operand is shifted left on...

Page 93 - Figure 3−15. Destination Operand—Carry Left Shift

Instruction Set 3-59 RISC 16−Bit CPU * RLC[.W] Rotate left through carry * RLC.B Rotate left through carry Syntax RLC dst or RLC.W dst RLC.B dst Operation C <− MSB <− MSB−1 .... LSB+1 <− LSB <− C Emulation ADDC dst,dst Description The destination operand is shifted left one position as s...

Page 94 - Figure 3−16. Destination Operand—Arithmetic Right Shift

Instruction Set 3-60 RISC 16−Bit CPU RRA[.W] Rotate right arithmetically RRA.B Rotate right arithmetically Syntax RRA dst or RRA.W dst RRA.B dst Operation MSB −> MSB, MSB −> MSB−1, ... LSB+1 −> LSB, LSB −> C Description The destination operand is shifted right one position as shown in Fi...

Page 95 - Figure 3−17. Destination Operand—Carry Right Shift

Instruction Set 3-61 RISC 16−Bit CPU RRC[.W] Rotate right through carry RRC.B Rotate right through carry Syntax RRC dst or RRC.W dst RRC dst Operation C −> MSB −> MSB−1 .... LSB+1 −> LSB −> C Description The destination operand is shifted right one position as shown in Figure 3−17.The ca...

Page 98 - Set negative bit

Instruction Set 3-64 RISC 16−Bit CPU * SETN Set negative bit Syntax SETN Operation 1 −> N Emulation BIS #4,SR Description The negative bit (N) is set. Status Bits N: SetZ: Not affectedC: Not affectedV: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.

Page 99 - Set zero bit

Instruction Set 3-65 RISC 16−Bit CPU * SETZ Set zero bit Syntax SETZ Operation 1 −> Z Emulation BIS #2,SR Description The zero bit (Z) is set. Status Bits N: Not affectedZ: SetC: Not affectedV: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.

Page 102 - Figure 3−18. Destination Operand Byte Swap

Instruction Set 3-68 RISC 16−Bit CPU SWPB Swap bytes Syntax SWPB dst Operation Bits 15 to 8 <−> bits 7 to 0 Description The destination operand high and low bytes are exchanged as shown in Figure 3−18. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected...

Page 103 - Extend Sign; Figure 3−19. Destination Operand Sign Extension; SXT

Instruction Set 3-69 RISC 16−Bit CPU SXT Extend Sign Syntax SXT dst Operation Bit 7 −> Bit 8 ......... Bit 15 Description The sign of the low byte is extended into the high byte as shown in Figure 3−19. Status Bits N: Set if result is negative, reset if positiveZ: Set if result is zero, reset oth...

Page 106 - Instruction Cycles and Lengths; Table 3−14 lists the CPU cycles for interrupt overhead and reset.; Table 3−14. Interrupt and Reset Cycles; Return from interrupt (; Table 3−15. Format-II Instruction Cycles and Lengths; Rn; Instruction Format II Immediate Mode; Do not use instructions

Instruction Set 3-72 RISC 16−Bit CPU 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on theinstruction format and the addressing modes used - not the instruction itself.The number of clock cycles refers to the MCLK. Interrupt and Reset Cycles T...

Page 107 - Table 3−16. Format I Instruction Cycles and Lengths

Instruction Set 3-73 RISC 16−Bit CPU Format-I (Double Operand) Instruction Cycles and Lengths Table 3−16 lists the length and CPU cycles for all addressing modes of format-Iinstructions. Table 3−16. Format I Instruction Cycles and Lengths Addressing Mode No. of Length of Src Dst Cycles Instruction E...

Page 108 - Instruction Set Description; Figure 3−20. Core Instruction Map

Instruction Set 3-74 RISC 16−Bit CPU 3.4.5 Instruction Set Description The instruction map is shown in Figure 3−20 and the complete instruction setis summarized in Table 3−17. Figure 3−20. Core Instruction Map 0xxx4xxx8xxx Cxxx 1xxx 14xx18xx 1Cxx 20xx24xx28xx 2Cxx 30xx34xx38xx 3Cxx 4xxx5xxx6xxx7xxx8...

Page 110 - FLL+ Clock Module Introduction; Chapter 4

4-1 FLL+ Clock Module The FLL+ clock module provides the clocks for MSP430x4xx devices. Thischapter discusses the FLL+ clock module. The FLL+ clock module isimplemented in all MSP430x4xx devices. Topic Page 4.1 FLL+ Clock Module Introduction 4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 111 - The FLL+ clock module includes two or three clock sources:

4-2 FLL+ Clock Module 4.1 FLL+ Clock Module Introduction The frequency-locked loop (FLL+) clock module supports low system cost andultralow-power consumption. Using three internal clock signals, the user canselect the best balance of performance and low power consumption. The FLL+features digital fr...

Page 114 - FLL+ Clock Module Operation; BIC; FLL+ Clock features for Low-Power Applications; Low clock frequency for energy conservation and time keeping

FLL+ Clock Module Operation 4-5 FLL+ Clock Module 4.2 FLL+ Clock Module Operation After a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times theACLK frequency. When a 32,768-Hz crystal is used for ACLK, MCLK andSMCLK will stabilize to 1.048576 MHz. Status register control bits SCG0, SCG1, OSCOF...

Page 115 - LFXT1 Oscillator; LFXT1 Oscillator Characteristics; XT2 Oscillator

FLL+ Clock Module Operation 4-6 FLL+ Clock Module 4.2.2 LFXT1 Oscillator The LFXT1 oscillator supports ultralow-current consumption using a32,768-Hz watch crystal in LF mode (XTS_FLL = 0). A watch crystal connectsto XIN and XOUT without any external components. The LFXT1 oscillator supports high-spe...

Page 116 - DCO Frequency Range; Table 4−1. DCO Range Control Bits; Typical; Range

FLL+ Clock Module Operation 4-7 FLL+ Clock Module 4.2.4 Digitally-Controlled Oscillator (DCO) The DCO is an integrated ring oscillator with RC-type characteristics. TheDCO frequency is stabilized by the FLL to a multiple of ACLK as defined byN, the lowest 7 bits of the SCFQCTL register. The DCOPLUS ...

Page 117 - DCO Modulator; The modulator mixes the two adjacent; Figure 4−3. Modulator Patterns

FLL+ Clock Module Operation 4-8 FLL+ Clock Module 4.2.6 DCO Modulator The modulator mixes two adjacent DCO frequencies to produce anintermediate effective frequency and spread the clock energy, reducingelectromagnetic interference (EMI) . The modulator mixes the two adjacent frequencies across 32 DC...

Page 119 - Buffered Clock Output; DCO Active During Oscillator Fault; Figure 4−4. Oscillator Fault Logic

Buffered Clock Output 4-10 FLL+ Clock Module 4.2.10 FLL+ Fail-Safe Operation The FLL+ module incorporates an oscillator-fault fail-safe feature. This featuredetects an oscillator fault for LFXT1, DCO and XT2 as shown in Figure 4−4.The available fault conditions are: - Low-frequency oscillator fault ...

Page 120 - FLL+ Clock Module Registers; The FLL+ registers are listed in Table 4−2.

FLL+ Clock Module Registers 4-11 FLL+ Clock Module 4.3 FLL+ Clock Module Registers The FLL+ registers are listed in Table 4−2. Table 4−2. FLL+ Registers Register Short Form Register Type Address Initial State System clock control SCFQCTL Read/write 052h 01Fh with PUC System clock frequency integrato...

Page 121 - SCFQCTL, System Clock Control Register; Modulation enabled; SCFI0, System Clock Frequency Integrator Register 0; FLLDx; DCO Range Control. These bits select the f; MODx

FLL+ Clock Module Registers 4-12 FLL+ Clock Module SCFQCTL, System Clock Control Register 7 6 5 4 3 2 1 0 SCFQ_M N rw−0 rw−0 rw−0 rw−1 rw−1 rw−1 rw−1 rw−1 SCFQ_M Bit 7 Modulation. This enables or disables modulation0 Modulation enabled 1 Modulation disabled N Bits6-0 Multiplier. These bits set the m...

Page 122 - SCFI1, System Clock Frequency Integrator Register 1; DCOx

FLL+ Clock Module Registers 4-13 FLL+ Clock Module SCFI1, System Clock Frequency Integrator Register 1 7 6 5 4 3 2 1 0 DCOx MODx (MSBs) rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 DCOx Bits7-3 These bits select the DCO tap and are modified automatically by the FLL+. MODx Bit 2 Most significant modulator...

Page 124 - Unused

FLL+ Clock Module Registers 4-15 FLL+ Clock Module FLL_CTL1, FLL+ Control Register 1 7 6 5 4 3 2 1 0 Unused SMCLK OFF † XT2OFF † SELMx † SELS † FLL_DIVx r0 r0 rw−(1) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) † Not present in MSP430x41x, MSP430x42x devices. Unused Bit 7 SMCLKOFF Bit 6 SMCLK off. This bit tu...

Page 125 - IE1, Interrupt Enable Register 1; OFIE; IFG1, Interrupt Flag Register 1

FLL+ Clock Module Registers 4-16 FLL+ Clock Module IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 OFIE rw−0 Bits7-2 These bits may be used by other modules. See device-specific datasheet. OFIE Bit 1 Oscillator fault interrupt enable. This bit enables the OFIFG interrupt.Because other bits in IE1 m...

Page 126 - Flash Memory Introduction; Chapter 5

5-1 Flash Memory Controller This chapter describes the operation of the MSP430 flash memory controller. Topic Page 5.1 Flash Memory Introduction 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Flash Memory Segmentation 5-3 . . . . . . . . . . . . . . . . . . . . . . ....

Page 127 - Minimum V; During Flash Write or Erase; Figure 5−1. Flash Memory Module Block Diagram

Flash Memory Introduction 5-2 Flash Memory Controller 5.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable andprogrammable. The flash memory module has an integrated controller thatcontrols programming and erase operations. The controller has threeregisters, a t...

Page 128 - Flash Memory Segmentation

Flash Memory Segmentation 5-3 Flash Memory Controller 5.2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments. Single bits, bytes, orwords can be written to flash memory, but the segment is the smallest size offlash memory that can be erased. The flash memory is partitioned in...

Page 129 - Flash Memory Operation; Block write; Flash Memory Timing Generator; Figure 5−3. Flash Memory Timing Generator Block Diagram; frequency deviates from the

Flash Memory Operation 5-4 Flash Memory Controller 5.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flashmemory is not being erased or written, the flash timing generator and voltagegenerator are off, and the memory operates identically to ROM. MSP430 f...

Page 130 - Erasing Flash Memory; Table 5−1. Erase Modes; MERAS; Segment erase; Figure 5−4. Erase Cycle Timing; BUSY

Flash Memory Operation 5-5 Flash Memory Controller 5.3.2 Erasing Flash Memory The erased level of a flash memory bit is 1. Each bit can be programmed from1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. Thesmallest amount of flash that can be erased is a segment. There are t...

Page 131 - Initiating an Erase from Within Flash Memory; The flow to initiate an erase from flash is shown in Figure 5−5.; Figure 5−5. Erase Cycle from Within Flash Memory; Setup flash controller and erase

Flash Memory Operation 5-6 Flash Memory Controller Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM. Whena flash segment erase operation is initiated from within flash memory, all timingis controlled by the flash controller, and the C...

Page 132 - Initiating an Erase from RAM; Figure 5−6. Erase Cycle from Within RAM

Flash Memory Operation 5-7 Flash Memory Controller Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not heldand can continue to execute code from RAM. The BUSY bit must be polled todetermine the end of the erase cycle before the CPU can access any flas...

Page 133 - Writing Flash Memory; Table 5−2. Write Modes; BLKWRT

Flash Memory Operation 5-8 Flash Memory Controller 5.3.3 Writing Flash Memory The write modes, selected by the WRT and BLKWRT bits, are listed inTable 5−1. Interrupts are automatically disabled during a flash write andre-enabled after the write. Any interrupt that occurred during the write will have...

Page 134 - cycles. With each byte or word write, the amount of time the block is; Initiating a Byte/Word Write from Within Flash Memory; Figure 5−8. Initiating a Byte/Word Write from Flash; Setup flash controller

Flash Memory Operation 5-9 Flash Memory Controller In byte/word mode, the internally-generated programming voltage is appliedto the complete 64-byte block, each time a byte or word is written, for 32 of the35 f FTG cycles. With each byte or word write, the amount of time the block is subjected to th...

Page 135 - Initiating a Byte/Word Write from RAM; The flow to initiate a byte/word write from RAM is shown in Figure 5−9.; Figure 5−9. Initiating a Byte/Word Write from RAM; yes

Flash Memory Operation 5-10 Flash Memory Controller Initiating a Byte/Word Write from RAM The flow to initiate a byte/word write from RAM is shown in Figure 5−9. Figure 5−9. Initiating a Byte/Word Write from RAM yes BUSY = 1 yes BUSY = 1 Disable watchdog Setup flash controller and set WRT=1 Write by...

Page 136 - Block Write; must not be exceeded for any block during

Flash Memory Operation 5-11 Flash Memory Controller Block Write The block write can be used to accelerate the flash write process when manysequential bytes or words need to be programmed. The flash programmingvoltage remains on for the duration of writing the 64-byte block. Thecumulative programming...

Page 137 - Block Write Flow and Example; A block write flow is shown in Figure 5−8 and the following example.; Figure 5−11. Block Write Flow

Flash Memory Operation 5-12 Flash Memory Controller Block Write Flow and Example A block write flow is shown in Figure 5−8 and the following example. Figure 5−11. Block Write Flow yes BUSY = 1 Disable watchdog Setup flash controller Set BLKWRT=WRT=1 Write byte or word no Block Border? yes WAIT=0? ye...

Page 139 - Flash Memory Access During Write or Erase; JMP PC

Flash Memory Operation 5-14 Flash Memory Controller 5.3.4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and whileBUSY=1, the CPU may not read or write to or from any flash location.Otherwise, an access violation occurs, ACCVIFG is set, and the ...

Page 140 - Stopping a Write or Erase Cycle; Any write to FCTL2 when the BUSY=1 is an access violation.; Flash Memory Controller Interrupts; Program via JTAG

Flash Memory Operation 5-15 Flash Memory Controller 5.3.5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion bysetting the emergency exit bit EMEX. Setting the EMEX bit stops the activeoperation immediately and stops the flash controller. All fla...

Page 141 - Programming Flash Memory via JTAG; Figure 5−12. User-Developed Programming Solution

Flash Memory Operation 5-16 Flash Memory Controller Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port. The JTAG interfacerequires four signals (5 signals on 20- and 28-pin devices), ground andoptionally V CC and RST/NMI. The JTAG port is protected with a fuse. Blow...

Page 142 - Flash Memory Registers; The flash memory registers are listed in Table 5−4.; Table 5−4. Flash Memory Registers; Flash memory control register 1

Flash Memory Registers 5-17 Flash Memory Controller 5.4 Flash Memory Registers The flash memory registers are listed in Table 5−4. Table 5−4. Flash Memory Registers Register Short Form Register Type Address Initial State Flash memory control register 1 FCTL1 Read/write 0128h 09600h with PUC Flash me...

Page 143 - FCTL1, Flash Memory Control Register; Block-write mode is off; No erase

Flash Memory Registers 5-18 Flash Memory Controller FCTL1, Flash Memory Control Register 15 14 13 12 11 10 9 8 FRKEY, Read as 096h FWKEY, Must be written as 0A5h 7 6 5 4 3 2 1 0 BLKWRT WRT Reserved Reserved Reserved MERAS ERASE Reserved rw−0 rw−0 r0 r0 r0 rw−0 rw−0 r0 FRKEY/FWKEY Bits15-8 FCTLx pass...

Page 144 - FCTL2, Flash Memory Control Register; FWKEYx; FNx

Flash Memory Registers 5-19 Flash Memory Controller FCTL2, Flash Memory Control Register 15 14 13 12 11 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 FSSELx FNx rw−0 rw−1 rw-0 rw-0 rw-0 rw−0 rw-1 rw−0 FWKEYx Bits15-8 FCTLx password. Always read as 096h. Must be written as 0A5h ...

Page 145 - FCTL3, Flash Memory Control Register FCTL3

Flash Memory Registers 5-20 Flash Memory Controller FCTL3, Flash Memory Control Register FCTL3 15 14 13 12 11 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 Reserved Reserved EMEX LOCK WAIT ACCVIFG KEYV BUSY r0 r0 rw-0 rw-1 r-1 rw−0 rw-(0) r(w)−0 FWKEYx Bits15-8 FCTLx password. ...

Page 146 - ACCVIE; or

Flash Memory Registers 5-21 Flash Memory Controller IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 ACCVIE rw−0 Bits7-6,4-0 These bits may be used by other modules. See device-specific datasheet. ACCVIE Bit 5 Flash memory access violation interrupt enable. This bit enables theACCVIFG interrupt. Bec...

Page 147 - Supply Voltage Supervisor; SVS Introduction; Chapter 6

6-1 Supply Voltage Supervisor This chapter describes the operation of the SVS. The SVS is implemented inall MSP430x4x devices. Topic Page 6.1 SVS Introduction 6−2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 SVS Operation 6−4 . . . . . . . . . . . . ....

Page 149 - Figure 6−1. SVS Block Diagram

SVS Introduction 6-3 Supply Voltage Supervisor Figure 6−1. SVS Block Diagram + − 1.25V Brownout Reset VCC Set SVSFG tReset ~ 50us Reset SVSCTL Bits 0001 0010 0011 1111 1101 1100 G D S SVSOUT G D S VLD SVSON PORON SVSOP SVSFG ~ 50us SVS_POR SVSIN AV CC AV CC

Page 150 - SVS Operation; Configuring the SVS

SVS Operation 6-4 Supply Voltage Supervisor 6.2 SVS Operation The SVS detects if the AV CC voltage drops below a selectable level. It can be configured to provide a POR or set a flag, when a low-voltage condition occurs.The SVS is disabled after a brownout reset to conserve current consumption. 6.2....

Page 151 - Changing the VLDx Bits; Figure 6−2. SVSON state When Changing VLDx

SVS Operation 6-5 Supply Voltage Supervisor 6.2.3 Changing the VLDx Bits When the VLDx bits are changed, two settling delays are implemented toallows the SVS circuitry to settle. During each delay, the SVS will not setSVSFG. The delays, t d(SVSon) and t settle, are shown in Figure 6−2. The t d(SVSon...

Page 152 - SVS Operating Range; is close to the threshold. The SVS operation and; Figure 6−3. Operating Levels for SVS and Brownout/Reset Circuit

SVS Operation 6-6 Supply Voltage Supervisor 6.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltagechanges when AV CC is close to the threshold. The SVS operation and SVS/Brownout interoperation are shown in Figure 6−3. Figure 6−3. Operating Levels for S...

Page 153 - SVS Registers; Table 6−1. SVS Registers; SVS Control Register; SVSCTL, SVS Control Register

SVS Registers 6-7 Supply Voltage Supervisor 6.3 SVS Registers The SVS registers are listed in Table 6−1. Table 6−1. SVS Registers Register Short Form Register Type Address Initial State SVS Control Register SVSCTL Read/write 056h Reset with BOR SVSCTL, SVS Control Register 7 6 5 4 3 2 1 0 VLDx PORON...

Page 154 - Hardware Multiplier Introduction; Chapter 7

7-1 Hardware Multiplier Hardware Multiplier This chapter describes the hardware multiplier. The hardware multiplier isimplemented in MSP430x44x devices. Topic Page 7.1 Hardware Multiplier Introduction 7-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Hardware Multiplier Operation...

Page 155 - Hardware Multiplier Introduction; Figure 7−1. Hardware Multiplier Block Diagram

Hardware Multiplier Introduction 7-2 Hardware Multiplier 7.1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU.This means, its activities do not interfere with the CPU activities. The multiplierregisters are peripheral registers that are loade...

Page 156 - Hardware Multiplier Operation; NOP; Operand Registers; Table 7−1. OP1 addresses; OP1 Address

Hardware Multiplier Operation 7-3 Hardware Multiplier 7.2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply, signed multiply, unsignedmultiply accumulate, and signed multiply accumulate operations. The type ofoperation is selected by the address the first operand is wr...

Page 157 - Result Registers; Table 7−2. RESHI Contents; Table 7−3. SUMEXT Contents; Mode; No carry for result; MACS Underflow and Overflow

Hardware Multiplier Operation 7-4 Hardware Multiplier 7.2.2 Result Registers The result low register RESLO holds the lower 16-bits of the calculation result.The result high register RESHI contents depend on the multiply operation andare listed in Table 7−2. Table 7−2. RESHI Contents Mode RESHI Conte...

Page 158 - Software Examples

Hardware Multiplier Operation 7-5 Hardware Multiplier 7.2.3 Software Examples Examples for all multiplier modes follow. All 8x8 modes use the absoluteaddress for the registers because the assembler will not allow .B access toword registers when using the labels from the standard definitions file. ; ...

Page 159 - Indirect Addressing of RESLO

Hardware Multiplier Operation 7-6 Hardware Multiplier 7.2.4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access theresult registers, At least one instruction is needed between loading the secondoperand and accessing one of the result registers: ; Acce...

Page 160 - Hardware Multiplier Registers; The hardware multiplier registers are listed in Table 7−4.; Table 7−4. Hardware Multiplier Registers

Hardware Multiplier Registers 7-7 Hardware Multiplier 7.3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 7−4. Table 7−4. Hardware Multiplier Registers Register Short Form Register Type Address Initial State Operand one - multiply MPY Read/write 0130h Unchanged Op...

Page 161 - DMA Introduction; Chapter 8

8-1 The DMA controller module transfers data from one address to anotherwithout CPU intervention. This chapter describes the operation of the DMAcontroller. The DMA controller is implemented in MSP430FG43x andimplements only one DMA channel. Topic Page 8.1 DMA Introduction 8-2 . . . . . . . . . . . ...

Page 163 - Figure 8−1. DMA Controller Block Diagram

8-3 Figure 8−1. DMA Controller Block Diagram DMA Priority And Control ENNMI DT DMA Channel 2 DMASRSBYTE DMA2SZ DMA2DA DMA2SA DMADSTBYTE DMASRCINCRx DMADSTINCRx 2 2 3 DMADTx DMAEN DT DMA Channel 1 DMASRSBYTE DMA1SZ DMA1DA DMA1SA DMADSTBYTE DMASRCINCRx DMADSTINCRx 2 2 3 DMADTx DMAEN DT DMA Channel 0 D...

Page 164 - DMA Operation; DMA Addressing Modes; Fixed address to fixed address; Figure 8−2. DMA Addressing Modes

8-4 8.2 DMA Operation The DMA controller is configured with user software. The setup and operationof the DMA is discussed in the following sections. 8.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode foreach DMA channel is independently configurable. For exa...

Page 165 - DMA Transfer Modes; Table 8−1. DMA Transfer Modes; DMADTx; Single transfer

8-5 8.2.2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits aslisted in Table 8−1. Each channel is individually configurable for its transfermode. For example, channel 0 may be configured in single transfer mode,while channel 1 is configured for burst-block tra...

Page 166 - Single Transfer

8-6 Single Transfer In single transfer mode, each byte/word transfer requires a separate trigger.The single transfer state diagram is shown in Figure 8−3. The DMAxSZ register is used to define the number of transfers to be made.The DMADSTINCRx and DMASRCINCRx bits select if the destinationaddress an...

Page 167 - Figure 8−3. DMA Single Transfer State Diagram

8-7 Figure 8−3. DMA Single Transfer State Diagram Reset Wait for Trigger Idle Hold CPU, Transfer one word/byte [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] DMAABORT=0 DMAABORT = 1 2 x MCLK DMAEN = 0 Modify T_SourceAdd Modify T_DestAdd Decrement DMAxSZ [ENNMI = 1 AND NMI event] OR [DMAL...

Page 168 - Block Transfers

8-8 Block Transfers In block transfer mode, a transfer of a complete block of data occurs after onetrigger. When DMADTx = 1, the DMAEN bit is cleared after the completion ofthe block transfer and must be set again before another block transfer can betriggered. After a block transfer has been trigger...

Page 169 - Figure 8−4. DMA Block Transfer State Diagram

8-9 Figure 8−4. DMA Block Transfer State Diagram Reset Wait for Trigger Idle Hold CPU, Transfer one word/byte [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] DMAABORT=0 DMAABORT = 1 2 x MCLK DMAEN = 0 Modify T_SourceAdd Modify T_DestAdd Decrement DMAxSZ DMAxSZ > 0 [ENNMI = 1 AND NMI ev...

Page 170 - Burst-Block Transfers

8-10 Burst-Block Transfers In burst-block mode, transfers are block transfers with CPU activityinterleaved. The CPU executes 2 MCLK cycles after every four byte/wordtransfers of the block resulting in 20% CPU execution capacity. After theburst-block, CPU execution resumes at 100% capacity and the DM...

Page 171 - Figure 8−5. DMA Burst-Block Transfer State Diagram

8-11 Figure 8−5. DMA Burst-Block Transfer State Diagram 2 x MCLK Reset Wait for Trigger Idle Hold CPU, Transfer one word/byte Burst State (release CPU for 2xMCLK) [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] DMAABORT=0 DMAABORT = 1 2 x MCLK DMAEN = 0 Modify T_SourceAdd Modify T_DestAdd...

Page 172 - Note: DMAONFETCH Must Be Used When The DMA Writes To Flash

8-12 8.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with theDMAxTSELx bits as described in Table 8−2.The DMAxTSELx bits should bemodified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictableDMA triggers may occur. When selecting the trigg...

Page 173 - Table 8−2. DMA Trigger Operation; DMAxTSELx Operation; A transfer is triggered when USART0 receives new data. In I; URXIFG1 flag will not trigger a transfer.; No transfer is triggered.

8-13 Table 8−2. DMA Trigger Operation DMAxTSELx Operation 0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically resetwhen the transfer starts 0001 A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag isautomatically reset when the transf...

Page 174 - Stopping DMA Transfers; There are two ways to stop DMA transfers in progress:; DMA Channel Priorities; DMA Priority; DMA channel priorites are not applicable to MSP430FG43x devices.

8-14 8.2.4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress: - A single, block, or burst-block transfer may be stopped with an NMIinterrupt, if the ENNMI bit is set in register DMACTL1. - A burst-block transfer may be stopped by clearing the DMAEN bit. 8.2.5 DMA Channel Pr...

Page 175 - DMA Transfer Cycle Time; Table 8−3. Maximum Single-Transfer DMA Cycle Time; CPU Operating Mode

8-15 8.2.6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronizebefore each single transfer or complete block or burst-block transfer. Eachbyte/word transfer requires two MCLK cycles after synchronization, and onecycle of wait time after the transfer. Becaus...

Page 178 - DMA Registers; The DMA registers are listed in Table 8−4.; Table 8−4. DMA Registers

8-18 8.3 DMA Registers The DMA registers are listed in Table 8−4. Table 8−4. DMA Registers Register Short Form Register Type Address Initial State DMA control 0 DMACTL0 Read/write 0122h Reset with POR DMA control 1 DMACTL1 Read/write 0124h Reset with POR DMA channel 0 control DMA0CTL Read/write 01E0...

Page 179 - DMACTL0, DMA Control Register 0; Reserved; Reserved

8-19 DMACTL0, DMA Control Register 0 15 14 13 12 11 10 9 8 Reserved DMA2TSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 DMA1TSELx DMA0TSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Reserved Bits15−12 Reserved DMA2TSELx Bits11−8 DMA trigger select. These b...

Page 180 - DMACTL1, DMA Control Register 1; The DMA transfer occurs immediately; ENNMI; NMI interrupt does not interrupt DMA transfer

8-20 DMACTL1, DMA Control Register 1 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 0 0 DMA ONFETCH ROUND ROBIN ENNMI r0 r0 r0 r0 r0 rw−(0) rw−(0) rw−(0) Reserved Bits15−3 Reserved. Read only. Always read as 0. DMAONFETCH Bit 2 DMA on fetch0 The DMA transfer occu...

Page 181 - DMAxCTL, DMA Channel x Control Register

8-21 DMAxCTL, DMA Channel x Control Register 15 14 13 12 11 10 9 8 Reserved DMADTx DMADSTINCRx DMASRCINCRx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 DMA DSTBYTE DMA SRCBYTE DMALEVEL DMAEN DMAIFG DMAIE DMA ABORT DMAREQ rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−...

Page 182 - DMAxSA, DMA Source Address Register; DMAxSAx

8-22 DMASRCBYTE Bit 6 DMA source byte. This bit selects the source as a byte or word.0 Word 1 Byte DMALEVEL Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitivetriggers.0 Edge sensitive (rising edge) 1 Level sensitive (high level) DMAEN Bit 4 DMA enable0 Disabled 1 Enabled DM...

Page 183 - DMAxDA, DMA Destination Address Register; DMAxDAx; DMAxSZ, DMA Size Address Register; Transfer is disabled

8-23 DMAxDA, DMA Destination Address Register 15 14 13 12 11 10 9 8 DMAxDAx rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DMAxDAx rw rw rw rw rw rw rw rw DMAxDAx Bits15−0 DMA destination address. The destination address register points to thedestination address for single transfers or the first address fo...

Page 184 - Digital I/O Introduction; Chapter 9

9-1 Digital I/O Digital I/O This chapter describes the operation of the digital I/O ports. Ports P1-P6 areimplemented in all MSP430x4xx devices. Topic Page 9.1 Digital I/O Introduction 9-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Digital I/O Operation 9-3 ....

Page 185 - Independently programmable individual I/Os

Digital I/O Introduction 9-2 Digital I/O 9.1 Digital I/O Introduction MSP430 devices have up to 6 digital I/O ports implemented, P1 - P6. Each porthas eight I/O pins. Every I/O pin is individually configurable for input or outputdirection, and each I/O line can be individually read or written to. Po...

Page 186 - Digital I/O Operation; Input Register PxIN; Writing to Read-Only Registers PxIN; Output Registers PxOUT; Bit = 0: The port pin is switched to input direction

Digital I/O Operation 9-3 Digital I/O 9.2 Digital I/O Operation The digital I/O is configured with user software. The setup and operation of thedigital I/O is discussed in the following sections. 9.2.1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at theco...

Page 187 - Function Select Registers PxSEL; Bit = 1: Peripheral module function is selected for the pin; P1 and P2 Interrupts Are Disabled When PxSEL = 1

Digital I/O Operation 9-4 Digital I/O 9.2.4 Function Select Registers PxSEL Port pins are often multiplexed with other peripheral module functions. See thedevice-specific data sheet to determine pin functions. Each PxSEL bit is usedto select the pin function − I/O port or peripheral module function....

Page 188 - P1 and P2 Interrupts; PxIFG Flags When Changing PxOUT or PxDIR

Digital I/O Operation 9-5 Digital I/O 9.2.5 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability, configured with thePxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector,and all P2 pins source a different single interrupt vector. The PxIFG registercan ...

Page 189 - Interrupt Edge Select Registers P1IES, P2IES; Writing to PxIESx; May be set; Interrupt Enable P1IE, P2IE; Each PxIE bit enables the associated PxIFG interrupt flag.; Configuring Unused Port Pins

Digital I/O Operation 9-6 Digital I/O Interrupt Edge Select Registers P1IES, P2IES Each PxIES bit selects the interrupt edge for the corresponding I/O pin. Bit = 0: The PxIFGx flag is set with a low-to-high transition Bit = 1: The PxIFGx flag is set with a high-to-low transition Note: Writing to PxI...

Page 190 - Digital I/O Registers

Digital I/O Registers 9-7 Digital I/O 9.3 Digital I/O Registers Seven registers are used to configure P1 and P2. Four registers are used toconfigure ports P3 - P6. The digital I/O registers are listed in Table 9−1. Table 9−1. Digital I/O Registers Port Register Short Form Address Register Type Initi...

Page 191 - Watchdog Timer Introduction

10-1 Watchdog Timer, Watchdog Timer+ The watchdog timer is a 16-bit timer that can be used as a watchdog or as aninterval timer. This chapter describes the watchdog timer. The watchdog timeris implemented in all MSP430x4xx devices, except those with the enhancedwatchdog timer, WDT+. The WDT+ is impl...

Page 192 - Watchdog Timer Introduction; Watchdog Timer Powers Up Active

Watchdog Timer Introduction 10-2 Watchdog Timer, Watchdog Timer+ 10.1 Watchdog Timer Introduction The primary function of the watchdog timer (WDT) module is to perform acontrolled system restart after a software problem occurs. If the selected timeinterval expires, a system reset is generated. If th...

Page 193 - Figure 10−1. Watchdog Timer Block Diagram

Watchdog Timer Introduction 10-3 Watchdog Timer, Watchdog Timer+ Figure 10−1. Watchdog Timer Block Diagram WDTQn Y 1 2 3 4 Q6 Q9 Q13 Q15 16−bit Counter CLK AB 1 1 A EN PUC SMCLK ACLK Clear Password Compare 0 0 0 0 1 1 1 1 WDTCNTCL WDTTMSEL WDTNMI WDTNMIES WDTIS1 WDTSSEL WDTIS0 WDTHOLD EQU EQU Write ...

Page 194 - Watchdog Timer Operation; Modifying the Watchdog Timer

Watchdog Timer Operation 10-4 Watchdog Timer, Watchdog Timer+ 10.2 Watchdog Timer Operation The WDT module can be configured as either a watchdog or interval timer withthe WDTCTL register. The WDTCTL register also contains control bits toconfigure the RST/NMI pin. WDTCTL is a 16-bit, password-protec...

Page 195 - The WDT uses two bits in the SFRs for interrupt control.

Watchdog Timer Operation 10-5 Watchdog Timer, Watchdog Timer+ 10.2.4 Watchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control. - The WDT interrupt flag, WDTIFG, located in IFG1.0 - The WDT interrupt enable, WDTIE, located in IE1.0 When using the WDT in the watchdog mode, the...

Page 196 - Periodically clear an active watchdog

Watchdog Timer Operation 10-6 Watchdog Timer, Watchdog Timer+ 10.2.6 Operation in Low-Power Modes The MSP430 devices have several low-power modes. Different clock signalsare available in different low-power modes. The requirements of the user’sapplication and the type of clocking used determine how ...

Page 197 - Watchdog Timer Registers; The watchdog timer module registers are listed in Table 10−1.; Table 10−1. Watchdog Timer Registers

Watchdog Timer Registers 10-7 Watchdog Timer, Watchdog Timer+ 10.3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 10−1. Table 10−1. Watchdog Timer Registers Register Short Form Register Type Address Initial State Watchdog timer control register WDTCTL Read/write 012...

Page 198 - WDTCTL, Watchdog Timer Register

Watchdog Timer Registers 10-8 Watchdog Timer, Watchdog Timer+ WDTCTL, Watchdog Timer Register 15 14 13 12 11 10 9 8 Read as 069h WDTPW, must be written as 05Ah 7 6 5 4 3 2 1 0 WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx rw−0 rw−0 rw−0 rw−0 r0(w) rw−0 rw−0 rw−0 WDTPW Bits15-8 Watchdog ti...

Page 199 - NMIIE

Watchdog Timer Registers 10-9 Watchdog Timer, Watchdog Timer+ IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 NMIIE WDTIE rw−0 rw−0 Bits7-5 These bits may be used by other modules. See device-specific datasheet. NMIIE Bit 4 NMI interrupt enable. This bit enables the NMI interrupt. Because other bit...

Page 200 - NMIIFG

Watchdog Timer Registers 10-10 Watchdog Timer, Watchdog Timer+ IFG1, Interrupt Flag Register 1 7 6 5 4 3 2 1 0 NMIIFG WDTIFG rw−(0) rw−(0) Bits7-5 These bits may be used by other modules. See device-specific datasheet. NMIIFG Bit 4 NMI interrupt flag. NMIIFG must be reset by software. Because other ...

Page 201 - Basic Timer1; Basic Timer1 Introduction

11-1 Basic Timer1 The Basic Timer1 module is two independent, cascadable 8-bit timers. Thischapter describes the Basic Timer1. Basic Timer1 is implemented in allMSP430x4xx devices. Topic Page 11.1 Basic Timer1 Introduction 11−2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11...

Page 202 - Basic Timer1 Initialization

Basic Timer1 Introduction 11-2 Basic Timer1 11.1 Basic Timer1 Introduction The Basic Timer1 supplies LCD timing and low frequency time intervals. TheBasic Timer1 is two independent 8-bit timers that can also be cascaded to formone 16-bit timer function. Some uses for the Basic Timer1 include: - Real...

Page 203 - Figure 11−1. Basic Timer1 Block Diagram

Basic Timer1 Introduction 11-3 Basic Timer1 Figure 11−1. Basic Timer1 Block Diagram BTCNT2 Set_BTIFG BTCNT1 EN1 CLK1 Q4 Q5 Q6 Q7 BTDIV BTHOLD ACLK EN2 CLK2 Q4 Q5 Q6 Q7 Q3 Q2 Q1 Q0 BTSSEL SMCLK BTIPx BTFRFQx ACLK:256 fLCD 00 01 10 11 11 10 01 00 111 110 101 100 001 011 010 000

Page 204 - Basic Timer1 Operation; Reading or Writing BTCNT1 and BTCNT2

Basic Timer1 Introduction 11-4 Basic Timer1 11.2 Basic Timer1 Operation The Basic Timer1 module can be configured as two 8-bit timers or one 16-bittimer with the BTCTL register. The BTCTL register is an 8-bit, read/writeregister. Any read or write access must use byte instructions. The BasicTimer1 c...

Page 206 - Basic Timer1 Registers; The watchdog timer module registers are listed in Table 11−1.; Table 11−1. Basic Timer1 Registers

Basic Timer1 Introduction 11-6 Basic Timer1 11.3 Basic Timer1 Registers The watchdog timer module registers are listed in Table 11−1. Table 11−1. Basic Timer1 Registers Register Short Form Register Type Address Initial State Basic Timer1 Control BTCTL Read/write 040h Unchanged Basic Timer1 Counter 1...

Page 207 - BTCTL, Basic Timer1 Control Register; BTCNT1 and BTCNT2 are operational; frequency. These bits control the LCD update frequency.

Basic Timer1 Introduction 11-7 Basic Timer1 BTCTL, Basic Timer1 Control Register 7 6 5 4 3 2 1 0 BTSSEL BTHOLD BTDIV BTFRFQx BTIPx rw rw rw rw rw rw rw rw BTSSEL Bit 7 BTCNT2 clock select. This bit, together with the BTDIV bit, selects theclock source for BTCNT2. See the description for BTDIV. BTHOL...

Page 208 - BTCNT1, Basic Timer1 Counter 1; BTCNT1x; BTCNT1 register. The BTCNT1 register is the count of BTCNT1.; BTCNT2, Basic Timer1 Counter 2; BTCNT2 register. The BTCNT2 register is the count of BTCNT2.

Basic Timer1 Introduction 11-8 Basic Timer1 BTCNT1, Basic Timer1 Counter 1 7 6 5 4 3 2 1 0 BTCNT1x rw rw rw rw rw rw rw rw BTCNT1x Bits7−0 BTCNT1 register. The BTCNT1 register is the count of BTCNT1. BTCNT2, Basic Timer1 Counter 2 7 6 5 4 3 2 1 0 BTCNT2x rw rw rw rw rw rw rw rw BTCNT2x Bits7−0 BTCNT...

Page 209 - IE2, Interrupt Enable Register 2; BTIE; IFG2, Interrupt Flag Register 2

Basic Timer1 Introduction 11-9 Basic Timer1 IE2, Interrupt Enable Register 2 7 6 5 4 3 2 1 0 BTIE rw−0 BTIE Bit 7 Basic Timer1 interrupt enable. This bit enables the BTIFG interrupt Becauseother bits in IE2 may be used for other modules, it is recommended to set orclear this bit using BIS.B or BIC.B...

Page 211 - Use of the Word Count; Second Timer_A On Select Devices

Timer_A Introduction 12-2 Timer_A 12.1 Timer_A Introduction Timer_A is a 16-bit timer/counter with three or five capture/compare registers.Timer_A can support multiple capture/compares, PWM outputs, and intervaltiming. Timer_A also has extensive interrupt capabilities. Interrupts may begenerated fro...

Page 213 - Modifying Timer_A Registers; Clock Source Select and Divider

Timer_A Operation 12-4 Timer_A 12.2 Timer_A Operation The Timer_A module is configured with user software. The setup andoperation of Timer_A is discussed in the following sections. 12.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TAR, increments or decrements (dependingon mode of opera...

Page 214 - Table 12−1. Timer Modes; MCx; Stop

Timer_A Operation 12-5 Timer_A 12.2.2 Starting the Timer The timer may be started, or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stoppedby writing 0 to TACCR0. The timer may then ...

Page 215 - Up Mode; Figure 12−3. Up Mode Flag Setting; Changing the Period Register TACCR0

Timer_A Operation 12-6 Timer_A Up Mode The up mode is used if the timer period must be different from 0FFFFh counts.The timer repeatedly counts up to the value of compare register TACCR0,which defines the period, as shown in Figure 12−2. The number of timercounts in the period is TACCR0+1. When the ...

Page 216 - Continuous Mode; Figure 12−4. Continuous Mode

Timer_A Operation 12-7 Timer_A Continuous Mode In the continuous mode, the timer repeatedly counts up to 0FFFFh and restartsfrom zero as shown in Figure 12−4. The capture/compare register TACCR0works the same way as the other capture/compare registers. Figure 12−4. Continuous Mode 0h 0FFFFh The TAIF...

Page 217 - Use of the Continuous Mode; and; Figure 12−6. Continuous Mode Time Intervals; is greater than the TACCR0

Timer_A Operation 12-8 Timer_A Use of the Continuous Mode The continuous mode can be used to generate independent time intervals andoutput frequencies. Each time an interval is completed, an interrupt isgenerated. The next time interval is added to the TACCRx register in theinterrupt service routine...

Page 219 - Use of the Up/Down Mode; Time during which both outputs need to be inactive

Timer_A Operation 12-10 Timer_A Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, and counting in the downdirection, the timer continues its descent until it reaches zero. The new periodtakes affect after the counter counts down to zero. When the timer is counting ...

Page 220 - Capture Mode; The timer value is copied into the TACCRx register

Timer_A Operation 12-11 Timer_A 12.2.4 Capture/Compare Blocks Three or five identical capture/compare blocks, TACCRx, are present inTimer_A. Any of the blocks may be used to capture the timer data, or togenerate time intervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is ...

Page 221 - Figure 12−11. Capture Cycle; Capture Initiated by Software; Compare Mode; Interrupt flag CCIFG is set

Timer_A Operation 12-12 Timer_A Figure 12−11. Capture Cycle Second Capture Taken COV = 1 Capture Taken No Capture Taken Read Taken Capture Clear Bit COV in Register TACCTLx Idle Idle Capture Capture Read and No Capture Capture Capture Read Capture Capture Initiated by Software Captures can be initia...

Page 222 - Output Modes; Table 12−2. Output Modes; OUTMODx; Output

Timer_A Operation 12-13 Timer_A 12.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is usedto generate output signals such as PWM signals. Each output unit has eightoperating modes that generate signals based on the EQU0 and EQUx signals. Output Modes The output mo...

Page 223 - Output Example—Timer in Up Mode; Figure 12−12. Output Example—Timer in Up Mode

Timer_A Operation 12-14 Timer_A Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value,and rolls from TACCR0 to zero, depending on the output mode. An exampleis shown in Figure 12−12 using TACCR0 and TACCR1. Figure 12−12. Output Example—Timer in Up Mo...

Page 224 - Output Example—Timer in Continuous Mode; Figure 12−13. Output Example—Timer in Continuous Mode

Timer_A Operation 12-15 Timer_A Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx andTACCR0 values, depending on the output mode. An example is shown inFigure 12−13 using TACCR0 and TACCR1. Figure 12−13. Output Example—Timer in Continuous Mode 0h 0F...

Page 225 - Output Example—Timer in Up/Down Mode; Figure 12−14. Output Example—Timer in Up/Down Mode; Switching Between Output Modes; BIS

Timer_A Operation 12-16 Timer_A Output Example—Timer in Up/Down Mode The OUTx signal changes when the timer equals TACCRx in either countdirection and when the timer equals TACCR0, depending on the output mode.An example is shown in Figure 12−14 using TACCR0 and TACCR2. Figure 12−14. Output Example—...

Page 226 - TACCR0 Interrupt; Figure 12−15. Capture/Compare TACCR0 Interrupt Flag; TAIV, Interrupt Vector Generator

Timer_A Operation 12-17 Timer_A 12.2.6 Timer_A Interrupts Two interrupt vectors are associated with the 16-bit Timer_A module: - TACCR0 interrupt vector for TACCR0 CCIFG - TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured i...

Page 228 - The Timer_A registers are listed in Table 12−3 and Table 12−4.

Timer_A Registers 12-19 Timer_A 12.3 Timer_A Registers The Timer_A registers are listed in Table 12−3 and Table 12−4. Table 12−3. Timer_A3 Registers Register Short Form Register Type Address Initial State Timer_A controlTimer0_A3 Control TACTL/TA0CTL Read/write 0160h Reset with POR Timer_A counterTi...

Page 230 - TARx

Timer_A Registers 12-21 Timer_A TAR, Timer_A Register 15 14 13 12 11 10 9 8 TARx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 TARx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) TARx Bits15-0 Timer_A register. The TAR register is the count of Timer_A.

Page 231 - TACCTLx, Capture/Compare Control Register

Timer_A Registers 12-22 Timer_A TACCTLx, Capture/Compare Control Register 15 14 13 12 11 10 9 8 CMx CCISx SCS SCCI Unused CAP rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) r−(0) rw−(0) 7 6 5 4 3 2 1 0 OUTMODx CCIE CCI OUT COV CCIFG rw−(0) rw−(0) rw−(0) rw−(0) r rw−(0) rw−(0) rw−(0) CMx Bit15-14 Capture m...

Page 236 - Modifying Timer_B Registers; TBR Length; , for the selectable lengths

Timer_B Operation 13-4 Timer_B 13.2 Timer_B Operation The Timer_B module is configured with user software. The setup andoperation of Timer_B is discussed in the following sections. 13.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TBR, increments or decrements (dependingon mode of opera...

Page 237 - Table 13−1. Timer Modes

Timer_B Operation 13-5 Timer_B 13.2.2 Starting the Timer The timer may be started or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stoppedby loading 0 to TBCL0. The timer may then be...

Page 238 - The up mode is used if the timer period must be different from TBR; Figure 13−3. Up Mode Flag Setting; Changing the Period Register TBCL0

Timer_B Operation 13-6 Timer_B Up Mode The up mode is used if the timer period must be different from TBR (max) counts. The timer repeatedly counts up to the value of compare latch TBCL0, whichdefines the period, as shown in Figure 13−2. The number of timer counts inthe period is TBCL0+1. When the t...

Page 239 - In continuous mode the timer repeatedly counts up to TBR; Figure 13−4. Continuous Mode; The TBIFG interrupt flag is set when the timer counts from TBR; Figure 13−5. Continuous Mode Flag Setting

Timer_B Operation 13-7 Timer_B Continuous Mode In continuous mode the timer repeatedly counts up to TBR (max) and restarts from zero as shown in Figure 13−4. The compare latch TBCL0 works the sameway as the other capture/compare registers. Figure 13−4. Continuous Mode 0h TBR(max) The TBIFG interrupt...

Page 240 - and t; Figure 13−6. Continuous Mode Time Intervals; is greater than the TBCL0

Timer_B Operation 13-8 Timer_B Use of the Continuous Mode The continuous mode can be used to generate independent time intervals andoutput frequencies. Each time an interval is completed, an interrupt isgenerated. The next time interval is added to the TBCLx latch in the interruptservice routine. Fi...

Page 242 - Changing the Value of Period Register TBCL0

Timer_B Operation 13-10 Timer_B Changing the Value of Period Register TBCL0 When changing TBCL0 while the timer is running, and counting in the downdirection, and when the TBCL0 load mode is immediate, the timer continuesits descent until it reaches zero. The new period takes effect after the counte...

Page 243 - The timer value is copied into the TBCCRx register

Timer_B Operation 13-11 Timer_B 13.2.4 Capture/Compare Blocks Three or seven identical capture/compare blocks, TBCCRx, are present inTimer_B. Any of the blocks may be used to capture the timer data or togenerate time intervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is ...

Page 244 - Figure 13−11. Capture Cycle

Timer_B Operation 13-12 Timer_B Figure 13−11. Capture Cycle Second Capture Taken COV = 1 Capture Taken No Capture Taken Read Taken Capture Clear Bit COV in Register TBCCTLx Idle Idle Capture Capture Read and No Capture Capture Capture Read Capture Capture Initiated by Software Captures can be initia...

Page 245 - Compare Latch TBCLx; Table 13−2. TBCLx Load Events; CLLDx; New data is transferred from TBCCRx to TBCLx when TBR counts to 0; Grouping Compare Latches; Table 13−3. Compare Latch Operating Modes; TBCLGRPx; None

Timer_B Operation 13-13 Timer_B Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to thetimer value in compare mode. TBCLx is buffered by TBCCRx. The bufferedcompare latch gives the user control over when a compare period updates.The user cannot directly access T...

Page 246 - Table 13−4. Output Modes

Timer_B Operation 13-14 Timer_B 13.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is usedto generate output signals such as PWM signals. Each output unit has eightoperating modes that generate signals based on the EQU0 and EQUx signals.The TBOUTH pin function can...

Page 247 - Figure 13−12. Output Example—Timer in Up Mode

Timer_B Operation 13-15 Timer_B Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value, androlls from TBCL0 to zero, depending on the output mode. An example is shownin Figure 13−12 using TBCL0 and TBCL1. Figure 13−12. Output Example—Timer in Up Mode 0...

Page 248 - Figure 13−13. Output Example—Timer in Continuous Mode

Timer_B Operation 13-16 Timer_B Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0values, depending on the output mode, An example is shown in Figure 13−13using TBCL0 and TBCL1. Figure 13−13. Output Example—Timer in Continuous Mode 0h TBR(ma...

Page 249 - Output Example − Timer in Up/Down Mode; Figure 13−14. Output Example—Timer in Up/Down Mode

Timer_B Operation 13-17 Timer_B Output Example − Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either countdirection and when the timer equals TBCL0, depending on the output mode.An example is shown in Figure 13−14 using TBCL0 and TBCL3. Figure 13−14. Output Example—Ti...

Page 250 - Figure 13−15. Capture/Compare TBCCR0 Interrupt Flag; TBIV, Interrupt Vector Generator

Timer_B Operation 13-18 Timer_B 13.2.6 Timer_B Interrupts Two interrupt vectors are associated with the 16-bit Timer_B module: - TBCCR0 interrupt vector for TBCCR0 CCIFG - TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured ...

Page 251 - TBIV, Interrupt Handler Examples; Capture/compare block CCR0

Timer_B Operation 13-19 Timer_B TBIV, Interrupt Handler Examples The following software example shows the recommended use of TBIV and thehandling overhead. The TBIV value is added to the PC to automatically jumpto the appropriate routine. The numbers at the right margin show the necessary CPU clock ...

Page 252 - The Timer_B registers are listed in Table 13−5.

Timer_B Registers 13-20 Timer_B 13.3 Timer_B Registers The Timer_B registers are listed in Table 13−5. Table 13−5. Timer_B Registers Register Short Form Register Type Address Initial State Timer_B control TBCTL Read/write 0180h Reset with POR Timer_B counter TBR Read/write 0190h Reset with POR Timer...

Page 253 - Timer_B Control Register TBCTL

Timer_B Registers 13-21 Timer_B Timer_B Control Register TBCTL 15 14 13 12 11 10 9 8 Unused TBCLGRPx CNTLx Unused TBSSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 IDx MCx Unused TBCLR TBIE TBIFG rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) w−(0) rw−(0) rw−(0) Unused Bit 15 Unuse...

Page 254 - TBCLR; Interrupt disabled; No interrupt pending; TBRx

Timer_B Registers 13-22 Timer_B Unused Bit 3 Unused TBCLR Bit 2 Timer_B clear. Setting this bit resets TBR, the TBCLK divider, and the countdirection. The TBCLR bit is automatically reset and is always read as zero. TBIE Bit 1 Timer_B interrupt enable. This bit enables the TBIFG interrupt request.0 ...

Page 255 - TBCCTLx, Capture/Compare Control Register

Timer_B Registers 13-23 Timer_B TBCCTLx, Capture/Compare Control Register 15 14 13 12 11 10 9 8 CMx CCISx SCS CLLDx CAP rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) rw−(0) 7 6 5 4 3 2 1 0 OUTMODx CCIE CCI OUT COV CCIFG rw−(0) rw−(0) rw−(0) rw−(0) r rw−(0) rw−(0) rw−(0) CMx Bit15-14 Capture mode00...

Page 257 - Timer_B interrupt vector value

Timer_B Registers 13-25 Timer_B TBIV, Timer_B Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 0 TBIVx 0 r0 r0 r0 r0 r−(0) r−(0) r−(0) r0 TBIVx Bits15-0 Timer_B interrupt vector value TBIV Contents Interrupt Source Interrupt Flag Interrupt...

Page 258 - USART Peripheral Interface, UART Mode

14-1 USART Peripheral Interface, UART Mode The universal synchronous/asynchronous receive/transmit (USART)peripheral interface supports two serial modes with one hardware module.This chapter discusses the operation of the asynchronous UART mode.USART0 is implemented on the MSP430x42x and MSP430x43x ...

Page 260 - Figure 14−1. USART Block Diagram: UART Mode

USART Introduction: UART Mode 14-3 USART Peripheral Interface, UART Mode Figure 14−1. USART Block Diagram: UART Mode Receiver Shift Register Transmit Shift Register Receiver Buffer UxRXBUF Transmit Buffer UxTXBUF LISTEN MM UCLK Clock Phase and Polarity Receive Status SYNC CKPH CKPL SSEL1 SSEL0 UCLKI...

Page 261 - Note: Initializing or Re-Configuring the USART Module; The required USART initialization/re-configuration process is:; Figure 14−2. Character Format

USART Operation: UART Mode 14-4 USART Peripheral Interface, UART Mode 14.2 USART Operation: UART Mode In UART mode, the USART transmits and receives characters at a bit rateasynchronous to another device. Timing for each character is based on theselected baud rate of the USART. The transmit and rece...

Page 262 - Asynchronous Communication Formats; Line Format

USART Operation: UART Mode 14-5 USART Peripheral Interface, UART Mode 14.2.3 Asynchronous Communication Formats When two devices communicate asynchronously, the idle-line format is usedfor the protocol. When three or more devices communicate, the USARTsupports the idle-line and address-bit multiproc...

Page 263 - ) Set TXWAKE, then write any character to UxTXBUF. UxTXBUF must be

USART Operation: UART Mode 14-6 USART Peripheral Interface, UART Mode The URXWIE bit is used to control data reception in the idle-linemultiprocessor format. When the URXWIE bit is set, all non-addresscharacters are assembled but not transferred into the UxRXBUF, andinterrupts are not generated. Whe...

Page 264 - Address; Figure 14−4. Address

USART Operation: UART Mode 14-7 USART Peripheral Interface, UART Mode Address - Bit Multiprocessor Format When MM = 1, the address-bit multiprocessor format is selected. Eachprocessed character contains an extra bit used as an address indicator shownin Figure 14−4. The first character in a block of ...

Page 265 - Automatic Error Detection; will be ignored. See the device-specific datasheet for parameters.; Table 14−1. Receive Error Conditions; Error Condition; Framing error

USART Operation: UART Mode 14-8 USART Peripheral Interface, UART Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started. Anylow-level on URXDx shorter than the deglitch time t τ (approximately 300 ns) will be ignored. See the device-specific datasheet fo...

Page 266 - Figure 14−5. State Diagram of Receiver Enable

USART Operation: UART Mode 14-9 USART Peripheral Interface, UART Mode 14.2.4 USART Receive Enable The receive enable bit, URXEx, enables or disables data reception on URXDxas shown in Figure 14−5. Disabling the USART receiver stops the receiveoperation following completion of any character currently...

Page 267 - Figure 14−6. State Diagram of Transmitter Enable

USART Operation: UART Mode 14-10 USART Peripheral Interface, UART Mode 14.2.5 USART Transmit Enable When UTXEx is set, the UART transmitter is enabled. Transmission is initiatedby writing data to UxTXBUF. The data is then moved to the transmit shiftregister on the next BITCLK after the TX shift regi...

Page 268 - Figure 14−8. BITCLK Baud Rate Timing

USART Operation: UART Mode 14-11 USART Peripheral Interface, UART Mode 14.2.6 UART Baud Rate Generation The USART baud rate generator is capable of producing standard baud ratesfrom non-standard source frequencies. The baud rate generator uses oneprescaler/divider and a modulator as shown in Figure ...

Page 269 - Baud Rate Bit Timing; UxBR; Determining the Modulation Value

USART Operation: UART Mode 14-12 USART Peripheral Interface, UART Mode Baud Rate Bit Timing The first stage of the baud rate generator is the 16-bit counter and comparator.At the beginning of each bit transmitted or received, the counter is loaded withINT(N/2) where N is the value stored in the comb...

Page 270 - Transmit Bit Timing; baud rate

USART Operation: UART Mode 14-13 USART Peripheral Interface, UART Mode Transmit Bit Timing The timing for each character is the sum of the individual bit timings. Bymodulating each bit, the cumulative bit error is reduced. The individual bit errorcan be calculated by: Error [%] + Ǌ baud rate BRCLK ƪ...

Page 271 - Receive Bit Timing; Figure 14−9. Receive Error; ȧȡȢ

USART Operation: UART Mode 14-14 USART Peripheral Interface, UART Mode Receive Bit Timing Receive timing consists of two error sources. The first is the bit-to-bit timingerror. The second is the error between a start edge occurring and the startedge being accepted by the USART. Figure 14−9 shows the...

Page 272 - 3, since the ideal division factor is 13.65

USART Operation: UART Mode 14-15 USART Peripheral Interface, UART Mode For example, the receive errors for the following conditions are calculated: Baud rate = 2400BRCLK = 32,768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.65 UxMCTL = 6B:m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0,...

Page 273 - Typical Baud Rates and Errors; Table 14−2. Commonly Used Baud Rates, Baud Rate Data, and Errors

USART Operation: UART Mode 14-16 USART Peripheral Interface, UART Mode Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed inTable 14−2 for a 32,768-Hz watch crystal (ACLK) and a typical 1,048,576-HzSMCLK. The receive error is the accumulated time versus t...

Page 274 - USART Transmit Interrupt Operation; Figure 14−10. Transmit Interrupt Operation

USART Operation: UART Mode 14-17 USART Peripheral Interface, UART Mode 14.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vectorfor reception. USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUFis...

Page 275 - USART Receive Interrupt Operation; Figure 14−11. Receive Interrupt Operation; Two types of characters do not set URXIFGx:

USART Operation: UART Mode 14-18 USART Peripheral Interface, UART Mode USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loadedinto UxRXBUF. An interrupt request is generated if URXIEx and GIE are alsoset. URXIFGx and URXIEx are reset by a syst...

Page 276 - Receive-Start Edge Detect Operation; Break Detect With Halted UART Clock

USART Operation: UART Mode 14-19 USART Peripheral Interface, UART Mode Receive-Start Edge Detect Operation The URXSE bit enables the receive start-edge detection feature. Therecommended usage of the receive-start edge feature is when BRCLK issourced by the DCO and when the DCO is off because of low-...

Page 277 - Receive-Start Edge Detect Conditions; Figure 14−12. Glitch Suppression, USART Receive Not Started; When a glitch is longer than; Figure 14−13. Glitch Suppression, USART Activated; URXDx

USART Operation: UART Mode 14-20 USART Peripheral Interface, UART Mode Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from beingaccidentally started. Any low-level on URXDx shorter than the deglitch time t τ (approximately 300 ns) will be ignored by the US...

Page 278 - Table 14−3. USART0 Control and Status Registers; Modifying SFR bits

USART Registers: UART Mode 14-21 USART Peripheral Interface, UART Mode 14.3 USART Registers: UART Mode Table 14−3 lists the registers for all devices implementing a USART module.Table 14−4 applies only to devices with a second USART module, USART1. Table 14−3. USART0 Control and Status Registers Reg...

Page 279 - UxCTL, USART Control Register

USART Registers: UART Mode 14-22 USART Peripheral Interface, UART Mode UxCTL, USART Control Register 7 6 5 4 3 2 1 0 PENA PEV SPB CHAR LISTEN SYNC MM SWRST rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 PENA Bit 7 Parity enable0 Parity disabled. 1 Parity enabled. Parity bit is generated (UTXDx) and expecte...

Page 280 - UxTCTL, USART Transmit Control Register

USART Registers: UART Mode 14-23 USART Peripheral Interface, UART Mode UxTCTL, USART Transmit Control Register 7 6 5 4 3 2 1 0 Unused CKPL SSELx URXSE TXWAKE Unused TXEPT rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 Unused Bit 7 Unused CKPL Bit 6 Clock polarity select0 UCLKI = UCLK 1 UCLKI = inverted UCL...

Page 281 - UxRCTL, USART Receive Control Register

USART Registers: UART Mode 14-24 USART Peripheral Interface, UART Mode UxRCTL, USART Receive Control Register 7 6 5 4 3 2 1 0 FE PE OE BRK URXEIE URXWIE RXWAKE RXERR rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 FE Bit 7 Framing error flag0 No error 1 Character received with low stop bit PE Bit 6 Parity e...

Page 282 - UxBR0, USART Baud Rate Control Register 0; UxBRx; The valid baud-rate control range is 3; UxMCTL, USART Modulation Control Register; UxMCTLx; Modulation bits. These bits select the modulation for BRCLK.

USART Registers: UART Mode 14-25 USART Peripheral Interface, UART Mode UxBR0, USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 rw rw rw rw rw rw rw rw UxBR1, USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 rw rw rw rw rw rw r...

Page 283 - UxRXBUF, USART Receive Buffer Register; UxRXBUFx; UxTXBUF, USART Transmit Buffer Register; UxTXBUFx

USART Registers: UART Mode 14-26 USART Peripheral Interface, UART Mode UxRXBUF, USART Receive Buffer Register 7 6 5 4 3 2 1 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 r r r r r r r r UxRXBUFx Bits7−0 The receive-data buffer is user accessible and contains the last receivedcharacter from the receive shift reg...

Page 284 - ME1, Module Enable Register 1

USART Registers: UART Mode 14-27 USART Peripheral Interface, UART Mode ME1, Module Enable Register 1 7 6 5 4 3 2 1 0 UTXE0 URXE0 rw−0 rw−0 UTXE0 Bit 7 USART0 transmit enable. This bit enables the transmitter for USART0.0 Module not enabled 1 Module enabled URXE0 Bit 6 USART0 receive enable. This bit...

Page 286 - UTXIFG0

USART Registers: UART Mode 14-29 USART Peripheral Interface, UART Mode IFG1, Interrupt Flag Register 1 7 6 5 4 3 2 1 0 UTXIFG0 URXIFG0 rw−1 rw−0 UTXIFG0 † Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty.0 No interrupt pending 1 Interrupt pending URXIFG0 † Bit 6 USART0 rece...

Page 287 - USART Peripheral Interface, SPI Mode

15-1 USART Peripheral Interface, SPI Mode USART Peripheral Interface, SPI Mode The universal synchronous/asynchronous receive/transmit (USART)peripheral interface supports two serial modes with one hardware module.This chapter discusses the operation of the synchronous peripheral interfaceor SPI mod...

Page 289 - Figure 15−1. USART Block Diagram: SPI Mode

USART Introduction: SPI Mode 15-3 USART Peripheral Interface, SPI Mode Figure 15−1. USART Block Diagram: SPI Mode Receiver Shift Register Transmit Shift Register Receiver Buffer UxRXBUF Transmit Buffer UxTXBUF LISTEN MM UCLK Clock Phase and Polarity Receive Status SYNC CKPH CKPL SSEL1 SSEL0 UCLKI AC...

Page 291 - Figure 15−2. USART Master and External Slave; Four-Pin SPI Master Mode; SIMO and UCLK are set to inputs and no longer drive the bus

USART Operation: SPI Mode 15-5 USART Peripheral Interface, SPI Mode 15.2.2 Master Mode Figure 15−2. USART Master and External Slave Receive Buffer UxRXBUF Receive Shift Register MSB LSB Transmit Buffer UxTXBUF Transmit Shift Register MSB LSB SPI Receive Buffer Data Shift Register (DSR) MSB LSB SOMI ...

Page 292 - Figure 15−3. USART Slave and External Master; Four-Pin SPI Slave Mode; Any receive operation in progress on SIMO is halted

USART Operation: SPI Mode 15-6 USART Peripheral Interface, SPI Mode 15.2.3 Slave Mode Figure 15−3. USART Slave and External Master Receive Buffer UxRXBUF Receive Shift Register LSB MSB Transmit Buffer UxTXBUF Transmit Shift Register LSB MSB SPI Receive Buffer Data Shift Register DSR LSB MSB SOMI SOM...

Page 293 - Transmit Enable; Figure 15−4. Master Mode Transmit Enable

USART Operation: SPI Mode 15-7 USART Peripheral Interface, SPI Mode 15.2.4 SPI Enable The SPI transmit/receive enable bit USPIEx enables or disables the USARTin SPI mode. When USPIEx = 0, the USART stops operation after the currenttransfer completes, or immediately if no operation is active. A PUC o...

Page 294 - Receive Enable; Figure 15−6. SPI Master Receive-Enable State Diagram

USART Operation: SPI Mode 15-8 USART Peripheral Interface, SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 15−6 andFigure 15−7. When USPIEx = 0, UCLK is disabled from shifting data into theRX shift register. Figure 15−6. SPI Master Receive-Enable State Diagram Idle ...

Page 295 - Figure 15−8. SPI Baud Rate Generator; BRCLK

USART Operation: SPI Mode 15-9 USART Peripheral Interface, SPI Mode 15.2.5 Serial Clock Control UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK isprovided by the USART baud rate generator on the UCLK pin as shown inFigure 15−8. When MM = 0, the USART clock is provided on the UCLK ...

Page 296 - Serial Clock Polarity and Phase; Figure 15−9. USART SPI Timing

USART Operation: SPI Mode 15-10 USART Peripheral Interface, SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPLand CKPH control bits of the USART. Timing for each case is shown inFigure 15−9. Figure 15−9. USART SPI Timing CKPH CKPL Cycle#...

Page 297 - SPI Transmit Interrupt Operation; Figure 15−10. Transmit Interrupt Operation; Writing to UxTXBUF in SPI Mode

USART Operation: SPI Mode 15-11 USART Peripheral Interface, SPI Mode 15.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vectorfor reception. SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUFis ready...

Page 298 - SPI Receive Interrupt Operation; Figure 15−11. Receive Interrupt Operation; Figure 15−12. Receive Interrupt State Diagram

USART Operation: SPI Mode 15-12 USART Peripheral Interface, SPI Mode SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loadedinto UxRXBUF as shown in Figure 15−11 and Figure 15−12. An interruptrequest is generated if URXIEx and GIE are also set. ...

Page 299 - Table 15−1. USART0 Control and Status Registers; Modifying the SFR bits

USART Registers: SPI Mode 15-13 USART Peripheral Interface, SPI Mode 15.3 USART Registers: SPI Mode Table 15−1 lists the registers for all devices implementing a USART module.Table 15−2 applies only to devices with a second USART module, USART1. Table 15−1. USART0 Control and Status Registers Regist...

Page 305 - ME2, Module Enable Register 2; Module not enabled

USART Registers: SPI Mode 15-19 USART Peripheral Interface, SPI Mode ME1, Module Enable Register 1 7 6 5 4 3 2 1 0 USPIE0 rw−0 Bit 7 This bit may be used by other modules. See device-specific datasheet. USPIE0 Bit 6 USART0 SPI enable. This bit enables the SPI mode for USART0.0 Module not enabled 1 M...

Page 308 - OA

16-1 OA OA The OA is a general purpose operational amplifier. This chapter describes theOA. Three OA modules are implemented in the MSP430FG43x devices. Topic Page 16.1 OA Introduction 16-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 OA Operation ...

Page 309 - Features of the OA include:; Note: Multiple OA Modules; The block diagram of the OA module is shown in Figure 16−1.

OA Introduction 16-2 OA 16.1 OA Introduction The OA op amps support front-end analog signal conditioning prior to analog-to-digital conversion. Features of the OA include: - Single supply, low-current operation - Rail-to-rail output - Software selectable Rail-to-Rail input - Programmable settling ti...

Page 310 - Figure 16−1. OA Block Diagram

OA Introduction 16-3 OA Figure 16−1. OA Block Diagram OAPMx OAPx 0 1 1 OAFBRx A12 ext. (OA0)A13 ext. (OA1)A14 ext. (OA2) OAADC0 4R 4R 2R 2R R R R R OAxOUT R BOTTOM RTOP OAx + − OAFCx={2 − 7} OAFBRx > 0 OAADC1OAFCx=0 OAFCx=1 R BOTTOM OAxTAP OAFCx=6 OAxI0 OA0I1 Int. DAC12_0OUT 00 01 10 11 0 1 OANx=...

Page 312 - Table 16−1. OA Mode Select; OAFCx; General Purpose Opamp Mode; In this mode the output of the OAx is connected to R; and the inverting; Comparator Mode; and R; is connected to AV

OA 16-5 OA 16.2.4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits.as listed in Table 16−1. Table 16−1. OA Mode Select OAFCx OA Mode 000 General-purpose opamp 001 Unity gain buffer 010 Reserved 011 Comparator 100 Non-inverting PGA amplifier 101 Reserve...

Page 313 - Non-Inverting PGA Mode

OA 16-6 OA Non-Inverting PGA Mode In this mode the output of the OAx is connected to R TOP and R BOTTOM is connected to AV SS . The OAxTAP signal is connected to the inverting input of the OAx providing a non-inverting amplifier configuration with a programmablegain of [1+OAxTAP ratio]. The OAxTAP r...

Page 314 - Table 16−3. Two-Opamp Differential Amplifier Gain Settings; OA1 OAFBRx; Figure 16−2. Two Opamp Differential Amplifier

OA 16-7 OA Figure 16−2 shows an example of a two-opamp differential amplifier usingOA0 and OA1. The control register settings and are shown in Table 16−2. Thegain for the amplifier is selected by the OAFBRx bits for OA1 and is shown inTable 16−3. The OAx interconnections are shown in Figure 16−3. Ta...

Page 316 - Table 16−5. Three-Opamp Differential Amplifier Gain Settings; Gain; Figure 16−4. Three Opamp Differential Amplifier

OA 16-9 OA Figure 16−4 shows an example of a three-opamp differential amplifier usingOA0, OA1 and OA2. The control register settings are shown in Table 16−4.The gain for the amplifier is selected by the OAFBRx bits of OA0 and OA2. TheOAFBRx settings for both OA0 and OA2 must be equal. The gain setti...

Page 318 - The OA registers are listed in Table 16−6.

OA Registers 16-11 OA 16.3 OA Registers The OA registers are listed in Table 16−6. Table 16−6. Register Short Form Register Type Address Initial State OA0 Control Register 0 OA0CTL0 Read/write 0C0h Reset with POR OA0 Control Register 1 OA0CTL1 Read/write 0C1h Reset with POR OA1 Control Register 0 OA...

Page 319 - OAxCTL0, Opamp Control Register 0; OANx

OA Registers 16-12 OA OAxCTL0, Opamp Control Register 0 7 6 5 4 3 2 1 0 OANx OAPx OAPMx OAADC1 OAADC0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 OANx Bits7-6 Inverting input select. These bits select the input signal for the OA invertinginput.00 OAxI0 01 OAxI1 10 DAC0 internal 11 DAC1 internal OAPx Bit...

Page 320 - OAxCTL1, Opamp Control Register 1; OAFBRx; Differential amplifier; OARRIP

OA Registers 16-13 OA OAxCTL1, Opamp Control Register 1 7 6 5 4 3 2 1 0 OAFBRx OAFCx Reserved OARRIP rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 OAFBRx Bits7-5 OAx feedback resistor select000 Tap 0001 Tap 1010 Tap 2011 Tap 3100 Tap 4101 Tap 5110 Tap 6111 Tap 7 OAFCx Bits4-2 OAx function control. This bi...

Page 322 - Comparator_A Introduction

Comparator_A Introduction 17-2 Comparator_A 17.1 Comparator_A Introduction The comparator_A module supports precision slope analog-to-digitalconversions, supply voltage supervision, and monitoring of external analogsignals. Features of Comparator_A include: - Inverting and non-inverting terminal inp...

Page 324 - Comparator_A Operation; Comparator Input Connection

Comparator_A Operation 17-4 Comparator_A 17.2 Comparator_A Operation The comparator_A module is configured with user software. The setup andoperation of comparator_A is discussed in the following sections. 17.2.1 Comparator The comparator compares the analog voltages at the + and – input terminals.I...

Page 325 - Figure 17−2. RC-Filter Response at the Output of the Comparator; The voltage reference generator is used to generate V; which can be; is applied. If external signals are applied to both; or a fixed transistor threshold voltage

Comparator_A Operation 17-5 Comparator_A 17.2.3 Output Filter The output of the comparator can be used with or without internal filtering.When control bit CAF is set, the output is filtered with an on-chip RC-filter. Any comparator output oscillates if the voltage difference across the inputterminal...

Page 326 - Figure 17−4. Comparator_A Interrupt System

Comparator_A Operation 17-6 Comparator_A 17.2.5 Comparator_A, Port Disable Register CAPD The comparator input and output functions are multiplexed with the associatedI/O port pins, which are digital CMOS gates. When analog signals are appliedto digital CMOS gates, parasitic current can flow from V C...

Page 327 - Figure 17−5. Temperature Measurement System

Comparator_A Operation 17-7 Comparator_A 17.2.7 Comparator_A Used to Measure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elementsusing single slope analog-to-digital conversion. For example, temperature canbe converted into digital data using a thermistor, by ...

Page 328 - Figure 17−6. Timing for Temperature Measurement Systems; The V; voltage; and the capacitor value should remain constant during the

Comparator_A Operation 17-8 Comparator_A The thermistor measurement is based on a ratiometric conversion principle.The ratio of two capacitor discharge times is calculated as shown inFigure 17−6. Figure 17−6. Timing for Temperature Measurement Systems V C V CC 0.25 × V CC Phase I: Charge Phase II: D...

Page 329 - Comparator_A Registers; The Comparator_A registers are listed in Table 17−1.

Comparator_A Registers 17-9 Comparator_A 17.3 Comparator_A Registers The Comparator_A registers are listed in Table 17−1. Table 17−1. Comparator_A Registers Register Short Form Register Type Address Initial State Comparator_A control register 1 CACTL1 Read/write 059h Reset with POR Comparator_A cont...

Page 332 - LCD Controller; LCD Controller Introduction

18-1 LCD Controller LCD Controller The LCD controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapterdescribes LCD controller. The LCD controller is implemented on allMSP430x4xx devices, except the MSP430x42x0 devices. Topic Page 18.1 LCD Controller Introduction 18−2 . . . . . . . . . . . ....

Page 333 - Max LCD Segment Control

LCD Controller Introduction 18-2 LCD Controller 18.1 LCD Controller Introduction The LCD controller directly drives LCD displays by creating the ac segmentand common voltage signals automatically. The MSP430 LCD controller cansupport static, 2-mux, 3-mux, and 4-mux LCDs. The LCD controller features ...

Page 334 - Figure 18−1. LCD Controller Block Diagram

LCD Controller Introduction 18-3 LCD Controller Figure 18−1. LCD Controller Block Diagram Display Memory 20x 8−bits Segment Output Control Mux Analog Voltage Multiplexer Timing Generator R23 R13 R03 COM0 COM2 COM1 R33 COM3 S0 S1 Common Output Control S39 S38 SEG0 SEG1 SEG38 SEG39 Mux Mux Mux LCDP2 L...

Page 335 - LCD Controller Operation; Figure 18−2. LCD memory; The LCD controller uses the f; signal from the Basic Timer1 to generate the; depends on

LCD Controller Operation 18-4 LCD Controller 18.2 LCD Controller Operation The LCD controller is configured with user software. The setup and operationof LCD controller is discussed in the following sections. 18.2.1 LCD Memory The LCD memory map is shown in Figure 18−2. Each memory bit correspondsto...

Page 336 - Values of R from 100k; output. This allows the power to the resistor ladder to; Table 18−1. External LCD Module Analog Voltage; LCD Contrast Control; LCDPx Bits Do Not Affect Dedicated LCD Segment Pins

LCD Controller Operation 18-5 LCD Controller 18.2.4 LCD Voltage Generation The voltages required for the LCD signals are supplied externally to pins R33,R23, R13, and R03. Using an equally weighted resistor divider ladder betweenthese pins establishes the analog voltages as shown in Table 18−1. Ther...

Page 337 - Figure 18−3. Example Static Waveforms

LCD Controller Operation 18-6 LCD Controller 18.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and onecommon line, COM0, is used. Figure 18−3 shows some example staticwaveforms. Figure 18−3. Example Static Waveforms f frame COM0 SP1 SP2 Resulting Voltage forSegment a ...

Page 338 - Figure 18−4. Static LCD Example

LCD Controller Operation 18-7 LCD Controller Figure 18−4 shows an example static LCD, pin-out, LCD-to-MSP430connections, and the resulting segment mapping. This is only an example.Segment mapping in a user’s application depends on the LCD pin-out and onthe MSP430-to-LCD connections. Figure 18−4. Sta...

Page 339 - Static Mode Software Example

LCD Controller Operation 18-8 LCD Controller Static Mode Software Example ; All eight segments of a digit are often located in four ; display memory bytes with the static display method. ;a EQU 001h b EQU 010h c EQU 002h d EQU 020h e EQU 004h f EQU 040h g EQU 008h h EQU 080h ; The register content o...

Page 340 - Mux Waveforms

LCD Controller Operation 18-9 LCD Controller 18.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments and twocommon lines, COM0 and COM1, are used. Figure 18−5 shows someexample 2-mux waveforms. Figure 18−5. Example 2- Mux Waveforms COM1 COM0 COM0 COM1 SP1 SP2 SP1 SP2 SP3 SP4...

Page 341 - Figure 18−6. 2−Mux LCD Example

LCD Controller Operation 18-10 LCD Controller Figure 18−6 shows an example 2-mux LCD, pin-out, LCD-to-MSP430connections, and the resulting segment mapping. This is only an example.Segment mapping in a user’s application completely depends on the LCDpin-out and on the MSP430-to-LCD connections. Figur...

Page 342 - -Mux Mode Software Example

LCD Controller Operation 18-11 LCD Controller 2-Mux Mode Software Example ; All eight segments of a digit are often located in two ; display memory bytes with the 2mux display rate ;a EQU 002h b EQU 020h c EQU 008h d EQU 004h e EQU 040h f EQU 001h g EQU 080h h EQU 010h ; The register content of Rx s...

Page 345 - -Mux Mode Software Example

LCD Controller Operation 18-14 LCD Controller 3-Mux Mode Software Example ; The 3mux rate can support nine segments for each ; digit. The nine segments of a digit are located in ; 1 1/2 display memory bytes. ;a EQU 0040h b EQU 0400h c EQU 0200h d EQU 0010h e EQU 0001h f EQU 0002h g EQU 0020h h EQU 0...

Page 347 - Display Memory

LCD Controller Operation 18-16 LCD Controller Figure 18−10 shows an example 4-mux LCD, pin-out, LCD-to-MSP430connections, and the resulting segment mapping. This is only an example.Segment mapping in a user’s application depends on the LCD pin-out and onthe MSP430-to-LCD connections. Figure 18−10. 4...

Page 348 - -Mux Mode Software Example

LCD Controller Operation 18-17 LCD Controller 4-Mux Mode Software Example ; The 4mux rate supports eight segments for each digit. ; All eight segments of a digit can often be located in ; one display memory byte a EQU 080h b EQU 040h c EQU 020h d EQU 001h e EQU 002h f EQU 008h g EQU 004h h EQU 010h ...

Page 349 - LCD Controller Registers; The LCD Controller registers are listed in Table 18−2.; Table 18−2. LCD Controller Registers

LCD Controller Operation 18-18 LCD Controller 18.3 LCD Controller Registers The LCD Controller registers are listed in Table 18−2. Table 18−2. LCD Controller Registers Register Short Form Register Type Address Initial State LCD control register LCDCTL Read/write 090h Reset with PUC LCD memory 1 LCDM...

Page 350 - LCDCTL, LCD Control Register; LCDPx

LCD Controller Operation 18-19 LCD Controller LCDCTL, LCD Control Register 7 6 5 4 3 2 1 0 LCDPx LCDMXx LCDSON Unused LCDON rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 LCDPx Bits7-5 LCD Port Select. These bits select the pin function to be port I/O or LCDfunction for groups of segments pins. These bits ...

Page 351 - LCD Controller Introduction

19-1 LCD_A Controller LCD_A Controller The LCD_A controller drives static, 2-mux, 3-mux, or 4-mux LCDs. Thischapter describes the LCD_A controller. The LCD_A controller is implementedon the MSP430x42x0 and MSP430F46xx devices. Topic Page 19.1 LCD Controller Introduction 19−2 . . . . . . . . . . . . ...

Page 352 - LCD_A Controller Introduction; Maximum LCD Segment Control

LCD_A Controller Introduction 19-2 LCD_A Controller 19.1 LCD_A Controller Introduction The LCD_A controller directly drives LCD displays by creating the ac segmentand common voltage signals automatically. The MSP430 LCD controller cansupport static, 2-mux, 3-mux, and 4-mux LCDs. The LCD controller f...

Page 353 - Figure 19−1. LCD_A Controller Block Diagram

LCD_A Controller Introduction 19-3 LCD_A Controller Figure 19−1. LCD_A Controller Block Diagram VLCDREFx Display Memory 20x 8−bits Segment Output Control Mux Analog Voltage Multiplexer Timing Generator COM0 COM2 COM1 COM3 S0 S1 Common Output Control S39 S38 SEG0 SEG1 SEG38 SEG39 Mux Mux Mux LCDSx LC...

Page 354 - LCD_A Controller Operation; Figure 19−2. LCD memory

LCD_A Controller Operation 19-4 LCD_A Controller 19.2 LCD_A Controller Operation The LCD_A controller is configured with user software. The setup andoperation of the LCD_A controller is discussed in the following sections. 19.2.1 LCD Memory The LCD memory map is shown in Figure 19−2. Each memory bit...

Page 355 - LCD Voltage Selection; Capacitor Required For Internal Charge Pump; LCD Bias Generation

LCD_A Controller Operation 19-5 LCD_A Controller 19.2.3 LCD_A Voltage And Bias Generation The LCD_A module allows selectable sources for the peak output waveformvoltage, V1 , as well as the fractional LCD biasing voltages V2 − V5. V LCD may be sourced from AV CC , an internal charge pump, or externa...

Page 356 - to 1 M; Figure 19−3. Bias Generation

LCD_A Controller Operation 19-6 LCD_A Controller To source the bias voltages V2 − V4 externally, REXT is set. This also disablesthe internal bias generation. Typically an equally weighted resistor divider isused with resistors ranging from 100 k to 1 M When using an external resistor divider, the V ...

Page 357 - Table 19−1. LCD Voltage and Biasing Characteristics; static

LCD_A Controller Operation 19-7 LCD_A Controller The internal bias generator supports 1/2 bias LCDs when LCD2B = 1, and 1/3bias LCDs when LCD2B = 0 in 2-mux, 3-mux, and 4-mux modes. In staticmode the internal divider is disabled. Some devices share the LCDCAP, R33, and R23 functions. In this case, t...

Page 358 - LCDSx Bits Do Not Affect Dedicated LCD Segment Pins

LCD_A Controller Operation 19-8 LCD_A Controller 19.2.4 LCD Timing Generation The LCD_A controller uses the f LCD signal from the integrated ACLK prescaler to generate the timing for common and segment lines. ACLK is assumed tobe 32768 Hz for generating f LCD . The f LCD frequency is selected with t...

Page 359 - Figure 19−4. Example Static Waveforms

LCD_A Controller Operation 19-9 LCD_A Controller 19.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and onecommon line, COM0, is used. Figure 19−4 shows some example staticwaveforms. Figure 19−4. Example Static Waveforms f frame COM0 SP1 SP2 Resulting Voltage forSegmen...

Page 360 - Figure 19−5. Static LCD Example

LCD_A Controller Operation 19-10 LCD_A Controller Figure 19−5 shows an example static LCD, pin-out, LCD-to-MSP430connections, and the resulting segment mapping. This is only an example.Segment mapping in a user’s application depends on the LCD pin-out and onthe MSP430-to-LCD connections. Figure 19−5...

Page 363 - Figure 19−7. 2−Mux LCD Example

LCD_A Controller Operation 19-13 LCD_A Controller Figure 19−7 shows an example 2-mux LCD, pin-out, LCD-to-MSP430connections, and the resulting segment mapping. This is only an example.Segment mapping in a user’s application completely depends on the LCDpin-out and on the MSP430-to-LCD connections. F...

Page 371 - LCD Controller Registers; The LCD Controller registers are listed in Table 19−2.; Table 19−2. LCD Controller Registers

LCD_A Controller Operation 19-21 LCD_A Controller 19.3 LCD Controller Registers The LCD Controller registers are listed in Table 19−2. Table 19−2. LCD Controller Registers Register Short Form Register Type Address Initial State LCD_A control register LCDACTL Read/write 090h Reset with PUC LCD memory...

Page 372 - LCDFREQx; Static; LCDSON; All LCD segments are off; LCDON

LCD_A Controller Operation 19-22 LCD_A Controller LCDACTL, LCD_A Control Register 7 6 5 4 3 2 1 0 LCDFREQx LCDMXx LCDSON Unused LCDON rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 LCDFREQx Bits7-5 LCD Frequency Select. These bits select the ACLK divider for the LCDfrequency.000 Divide by 32001 Divide by 6...

Page 375 - LCDAVCTL0, LCD_A Voltage Control Register 0; REXT; LCDCPEN

LCD_A Controller Operation 19-25 LCD_A Controller LCDAVCTL0, LCD_A Voltage Control Register 0 7 6 5 4 3 2 1 0 Unused R03EXT REXT VLCDEXT LCDCPEN VLCDREFx LCD2B rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Unused Bit 7 Unused R03EXT Bit 6 V5 voltage select. This bit selects the external connection for the...

Page 376 - LCDAVCTL1, LCD_A Voltage Control Register 1; VLCDx; is used for V

LCD_A Controller Operation 19-26 LCD_A Controller LCDAVCTL1, LCD_A Voltage Control Register 1 7 6 5 4 3 2 1 0 Unused VLCDx Unused rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Unused Bits7−5 Unused VLCDx Bits4−1 Charge pump voltage select. LCDCPEN must be 1 for the charge pump tobe enabled. AV CC is used ...

Page 378 - ADC12 Introduction

ADC12 Introduction 20-2 ADC12 20.1 ADC12 Introduction The ADC12 module supports fast, 12-bit analog-to-digital conversions. Themodule implements a 12-bit SAR core, sample select control, referencegenerator and a 16 word conversion-and-control buffer. Theconversion-and-control buffer allows up to 16 ...

Page 380 - ADC12 Operation; ADC; Conversion Clock Selection

ADC12 Operation 20-4 ADC12 20.2 ADC12 Operation The ADC12 module is configured with user software. The setup and operationof the ADC12 is discussed in the following sections. 20.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation andstores the result in con...

Page 381 - ) so that the stray capacitance is grounded to help; Figure 20−2. Analog Multiplexer; Analog Port Selection; to GND. This parasitic current occurs if the

ADC12 Operation 20-5 ADC12 20.2.2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channelfor conversion by the analog input multiplexer. The input multiplexer is abreak-before-make type to reduce input-to-input noise injection resulting fromchanne...

Page 382 - Reference Decoupling

ADC12 Operation 20-6 ADC12 20.2.3 Voltage Reference Generator The ADC12 module contains a built-in voltage reference with two selectablevoltage levels, 1.5 V and 2.5 V. Either of these reference voltages may be usedinternally and externally on pin V REF+ . Setting REFON=1 enables the internal refere...

Page 383 - The ADC12SC bit; Extended Sample Mode; When; Figure 20−3. Extended Sample Mode

ADC12 Operation 20-7 ADC12 20.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of the sampleinput signal SHI. The source for SHI is selected with the SHSx bits andincludes the following: - The ADC12SC bit - The Timer_A Output Unit 1 - The Timer_B Outpu...

Page 384 - Pulse Sample Mode; AD12CLK for a programmed interval t; Figure 20−4. Pulse Sample Mode

ADC12 Operation 20-8 ADC12 Pulse Sample Mode The pulse sample mode is selected when SHP = 1. The SHI signal is used totrigger the sampling timer. The SHT0x and SHT1x bits in ADC12CTL0 controlthe interval of the sampling timer that defines the SAMPCON sample periodt sample. The sampling timer keeps S...

Page 385 - Sample Timing Considerations; Figure 20−5. Analog Input Equivalent Circuit

ADC12 Operation 20-9 ADC12 Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON =1, the selected Ax input can be modeled as an RC low-pass filter during thesampling time t sample , as shown below in Figure 20−5. An internal MUX-on input resistance R I (max. 2 ...

Page 386 - Table 20−1. Conversion Mode Summary; CONSEQx; A single channel is converted once.

ADC12 Operation 20-10 ADC12 20.2.6 Conversion Memory There are 16 ADC12MEMx conversion memory registers to store conversionresults. Each ADC12MEMx is configured with an associated ADC12MCTLxcontrol register. The SREFx bits define the voltage reference and the INCHxbits select the input channel. The ...

Page 391 - Using the Multiple Sample and Convert (MSC) Bit; No EOS Bit Set For Sequence

ADC12 Operation 20-15 ADC12 Using the Multiple Sample and Convert (MSC) Bit To configure the converter to perform successive conversions automaticallyand as quickly as possible, a multiple sample and convert function is available.When MSC = 1, CONSEQx > 0, and the sample timer is used, the first ...

Page 392 - Using the Integrated Temperature Sensor; output or affect the reference selections for the conversion.; Figure 20−10. Typical Temperature Sensor Transfer Function

ADC12 Operation 20-16 ADC12 20.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog inputchannel INCHx = 1010. Any other configuration is done as if an externalchannel was selected, including reference selection, conversion-memoryselection, e...

Page 393 - ADC12 Grounding and Noise Considerations; Figure 20−11. ADC12 Grounding and Noise Considerations

ADC12 Operation 20-17 ADC12 20.2.9 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout andgrounding techniques should be followed to eliminate ground loops, unwantedparasitic effects, and noise. Ground loops are formed when return curren...

Page 394 - ADC12 Interrupts; The ADC12 has 18 interrupt sources:; ADC12IV, Interrupt Vector Generator

ADC12 Operation 20-18 ADC12 20.2.10 ADC12 Interrupts The ADC12 has 18 interrupt sources: - ADC12IFG0-ADC12IFG15 - ADC12OV, ADC12MEMx overflow - ADC12TOV, ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memoryregister is loaded with a conversion result. An...

Page 395 - ADC12 Interrupt Handling Software Example; ADTOV

ADC12 Operation 20-19 ADC12 ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IVand the handling overhead. The ADC12IV value is added to the PC toautomatically jump to the appropriate routine. The numbers at the right margin show the necessary...

Page 396 - ADC12 Registers; The ADC12 registers are listed in Table 20−2 .

ADC12 Registers 20-20 ADC12 20.3 ADC12 Registers The ADC12 registers are listed in Table 20−2 . Table 20−2. ADC12 Registers Register Short Form Register Type Address Initial State ADC12 control register 0 ADC12CTL0 Read/write 01A0h Reset with POR ADC12 control register 1 ADC12CTL1 Read/write 01A2h R...

Page 397 - SHTx Bits

ADC12 Registers 20-21 ADC12 ADC12CTL0, ADC12 Control Register 0 15 14 13 12 11 10 9 8 SHT1x SHT0x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 MSC REF2_5V REFON ADC12ON ADC12OVIE ADC12 TOVIE ENC ADC12SC rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Modifiable onl...

Page 399 - SHSx; SAMPCON signal is sourced from the sample-input signal.; ISSH

ADC12 Registers 20-23 ADC12 ADC12CTL1, ADC12 Control Register 1 15 14 13 12 11 10 9 8 CSTARTADDx SHSx SHP ISSH rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 ADC12DIVx ADC12SSELx CONSEQx ADC12 BUSY rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) Modifiable only when E...

Page 400 - No operation is active.; ADC12MEMx, ADC12 Conversion Memory Registers

ADC12 Registers 20-24 ADC12 ADC12SSELx Bits4-3 ADC12 clock source select00 ADC12OSC 01 ACLK 10 MCLK 11 SMCLK CONSEQx Bits2-1 Conversion sequence mode select00 Single-channel, single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels ADC12BUSY Bit 0 ADC12 busy....

Page 401 - ADC12MCTLx, ADC12 Conversion Memory Control Registers; EOS

ADC12 Registers 20-25 ADC12 ADC12MCTLx, ADC12 Conversion Memory Control Registers 7 6 5 4 3 2 1 0 EOS SREFx INCHx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 EOS Bit 7 End of sequence. Indicates the last conversion in a sequence.0 Not end of sequence 1 End of...

Page 402 - ADC12IE, ADC12 Interrupt Enable Register; ADC12IFG, ADC12 Interrupt Flag Register

ADC12 Registers 20-26 ADC12 ADC12IE, ADC12 Interrupt Enable Register 15 14 13 12 11 10 9 8 ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IE9 ADC12IE8 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 ADC12IE7 ADC12IE6 ADC12IE5 ADC12IE4 ADC12IE3 ADC12IE2 ADC12...

Page 403 - ADC12IV, ADC12 Interrupt Vector Register; ADC12 interrupt vector value

ADC12 Registers 20-27 ADC12 ADC12IV, ADC12 Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 ADC12IVx 0 r0 r0 r−(0) r−(0) r−(0) r−(0) r−(0) r0 ADC12IVx Bits15-0 ADC12 interrupt vector value ADC12IV Contents Interrupt Source Interrupt Flag Int...

Page 405 - SD16 Introduction

SD16 Introduction 21-2 SD16 21.1 SD16 Introduction The SD16 module consists of up to three independent sigma-deltaanalog-to-digital converters and an internal voltage reference. Each channelhas up to 8 fully differential multiplexed inputs including a built-in temperaturesensor. The converters are b...

Page 407 - SD16 Operation; GAIN

SD16 Operation 21-4 SD16 21.2 SD16 Operation The SD16 module is configured with user software. The setup and operationof the SD16 is discussed in the following sections. 21.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-ordersigma-delta modulator. A single-bit comparat...

Page 408 - Analog Input Setup; conversion after a start condition.; Analog Input Characteristics

SD16 Operation 21-5 SD16 21.2.5 Channel Selection Each SD16 channel can convert up to 8 differential pair inputs multiplexed intothe PGA. Up to six input pairs (A0-A5) are available externally on the device.See the device-specific data sheet for analog input pin information. An internaltemperature s...

Page 409 - sin; sin; Ǔ ȧ; Figure 21−2. Comb Filter’s Frequency Response with OSR = 32

SD16 Operation 21-6 SD16 21.2.6 Digital Filter The digital filter processes the 1-bit data stream from the modulator using aSINC 3 comb filter. The transfer function is described in the z-Domain by: H ( z ) + ǒ 1 OSR 1 * z * OSR 1 * z * 1 Ǔ 3 and in the frequency domain by: H ǒ f Ǔ + ȧ ȱȲ sinc ǒ OSR...

Page 410 - Figure 21−3. Digital Filter Step Response and Conversion Points

SD16 Operation 21-7 SD16 Figure 21−3 shows the digital filter step response and conversion points. Forstep changes at the input after start of conversion a settling time must beallowed before a valid conversion result is available. The SD16INTDLYx bitscan provide sufficient filter settling time for ...

Page 411 - Digital Filter Output; Figure 21−4. Used Bits of Digital Filter Output.

SD16 Operation 21-8 SD16 Digital Filter Output The number of bits output by each digital filter is dependent on theoversampling ratio and ranges from 16 to 24 bits. Figure 21−4 shows thedigital filter output bits and their relation to SD16MEMx for each OSR. Forexample, for OSR = 256 and LSBACC = 1, ...

Page 412 - Output Data Format; Table 21−1. Data Format; Format; and the conversion result. The digital values for both data; Figure 21−5. Input Voltage vs. Digital Output

SD16 Operation 21-9 SD16 21.2.7 Conversion Memory Registers: SD16MEMx One SD16MEMx register is associated with each SD16 channel. Conversionresults for each channel are moved to the corresponding SD16MEMx registerwith each decimation step of the digital filter. The SD16IFG bit for a givenchannel is ...

Page 413 - Table 21−2. Conversion Mode Summary; Single Channel, Single Conversion

SD16 Operation 21-10 SD16 21.2.8 Conversion Modes The SD16 module can be configured for four modes of operation, listed inTable 21−2. The SD16SNGL and SD16GRP bits for each channel selects theconversion mode. Table 21−2. Conversion Mode Summary SD16SNGL SD16GRP { Mode Operation 1 0 Single channel,Si...

Page 414 - Figure 21−6. Single Channel Operation; Group of Channels, Single Conversion

SD16 Operation 21-11 SD16 Figure 21−6. Single Channel Operation Channel 0SD16SNGL = 1SD16GRP = 0 Time Conversion SD16SC Channel 1SD16SNGL = 1SD16GRP = 0 Conversion Channel 2SD16SNGL = 0SD16GRP = 0 Conversion SD16SC SD16SC Conversion Conversion Conversion Set by SW Auto−clear Set by SW Auto−clear Set...

Page 415 - Group of Channels, Continuous Conversion; Figure 21−7. Grouped Channel Operation

SD16 Operation 21-12 SD16 Group of Channels, Continuous Conversion When SD16SNGL = 0 for a channel in a group, continuous conversion modeis selected. Continuous conversion of that channel will occur synchronouslywhen the master channel SD16SC bit is set. SD16SC bits for all groupedchannels will be a...

Page 416 - Conversion Operation Using Preload; Figure 21−8. Conversion Delay using Preload

SD16 Operation 21-13 SD16 21.2.9 Conversion Operation Using Preload When multiple channels are grouped the SD16PREx registers can be used todelay the conversion time frame for each channel. Using SD16PREx, thedecimation time of the digital filter is increased by the specified number of f M clock cyc...

Page 417 - Figure 21−9. Start of Conversion using Preload

SD16 Operation 21-14 SD16 Figure 21−9. Start of Conversion using Preload Delayed Conversion 40 SD16OSRx = 32 Start of Conversion Time Conversion 32 Conversion 32 f M cycles: 1st Sample Ch1 SD16PRE0 = 8 SD16PRE1 = 0 Conversion 32 Conversion 32 Conversion 32 Conversion 1st Sample Ch0 When channels are...

Page 418 - Using the Integrated Temperature Sensor; Figure 21−11. Typical Temperature Sensor Transfer Function

SD16 Operation 21-15 SD16 21.2.10 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog inputchannel SD16INCHx = 110. Any other configuration is done as if an externalchannel was selected, including SD16INTDLYx and SD16GAINx settings. The typical ...

Page 419 - Interrupt Handling; The SD16 has 2 interrupt sources for each ADC channel:; SD16IV, Interrupt Vector Generator

SD16 Operation 21-16 SD16 21.2.11 Interrupt Handling The SD16 has 2 interrupt sources for each ADC channel: - SD16IFG - SD16OVIFG The SD16IFG bits are set when their corresponding SD16MEMx memoryregister is written with a conversion result. An interrupt request is generatedif the corresponding SD16I...

Page 420 - SD16 Interrupt Handling Software Example

SD16 Operation 21-17 SD16 SD16 Interrupt Handling Software Example The following software example shows the recommended use of SD16IV andthe handling overhead. The SD16IV value is added to the PC to automaticallyjump to the appropriate routine. The numbers at the right margin show the necessary CPU ...

Page 421 - SD16 Registers; The SD16 registers are listed in Table 21−3:

SD16 Registers 21-18 SD16 21.3 SD16 Registers The SD16 registers are listed in Table 21−3: Table 21−3. SD16 Registers Register Short Form Register Type Address Initial State SD16 Control SD16CTL Read/write 0100h Reset with PUC SD16 Interrupt Vector SD16IV Read/write 0110h Reset with PUC SD16 Channel...

Page 422 - SD16CTL, SD16 Control Register

SD16 Registers 21-19 SD16 SD16CTL, SD16 Control Register 15 14 13 12 11 10 9 8 Reserved SD16LP r0 r0 r0 r0 r0 r0 r0 rw−0 7 6 5 4 3 2 1 0 SD16DIVx SD16SSELx SD16 VMIDON SD16 REFON SD16OVIE Reserved rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 r0 Reserved Bits15-9 Reserved SD16LP Bit 8 Low power mode. This bit ...

Page 423 - SD16CCTLx, SD16 Channel x Control Register

SD16 Registers 21-20 SD16 SD16CCTLx, SD16 Channel x Control Register 15 14 13 12 11 10 9 8 Reserved SD16SNGL SD16OSRx r0 r0 r0 r0 r0 rw−0 rw−0 rw−0 7 6 5 4 3 2 1 0 SD16 LSBTOG SD16 LSBACC SD16 OVIFG SD16DF SD16IE SD16IFG SD16SC SD16GRP rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 r(w)−0 Reserved Bits15-11 Res...

Page 424 - SD16INCTLx, SD16 Channel x Input Control Register

SD16 Registers 21-21 SD16 SD16IFG Bit 2 SD16 interrupt flag. SD16IFG is set when new conversion results areavailable. SD16IFG is automatically reset when the correspondingSD16MEMx register is read, or may be cleared with software.0 No interrupt pending 1 Interrupt pending SD16SC Bit 1 SD16 start con...

Page 425 - SD16MEMx, SD16 Channel x Conversion Memory Register; SD16PREx, SD16 Channel x Preload Register; SD16 digital filter preload value.

SD16 Registers 21-22 SD16 SD16MEMx, SD16 Channel x Conversion Memory Register 15 14 13 12 11 10 9 8 Conversion Results r r r r r r r r 7 6 5 4 3 2 1 0 Conversion Results r r r r r r r r ConversionResult Bits15-0 Conversion Results. The SD16MEMx register holds the upper or lower16-bits of the digital...

Page 426 - SD16IV, SD16 Interrupt Vector Register; SD16 interrupt vector value

SD16 Registers 21-23 SD16 SD16IV, SD16 Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 SD16IVx 0 r0 r0 r0 r−0 r−0 r−0 r−0 r0 SD16IVx Bits15-0 SD16 interrupt vector value SD16IV Contents Interrupt Source Interrupt Flag InterruptPriority 00...

Page 431 - Table 22−1. High Input Impedance Buffer; Buffer; Buffer disabled

SD16_A Operation 22-5 SD16_A 22.2.5 Channel Selection The SD16_A can convert up to 8 differential pair inputs multiplexed into thePGA. Up to five input pairs (A0-A4) are available externally on the device. Aresistive divider to measure the supply voltage is available using the A5multiplexer input. A...

Page 432 - Figure 22−2. Comb Filter’s Frequency Response with OSR = 32

SD16_A Operation 22-6 SD16_A 22.2.7 Digital Filter The digital filter processes the 1-bit data stream from the modulator using aSINC 3 comb filter. The transfer function is described in the z-Domain by: H ( z ) + ǒ 1 OSR 1 * z * OSR 1 * z * 1 Ǔ 3 and in the frequency domain by: H ǒ f Ǔ + ȧ ȱȲ sinc ǒ...

Page 433 - Figure 22−3. Digital Filter Step Response and Conversion Points

SD16_A Operation 22-7 SD16_A Figure 22−3 shows the digital filter step response and conversion points. Forstep changes at the input after start of conversion a settling time must beallowed before a valid conversion result is available. The SD16INTDLYx bitscan provide sufficient filter settling time ...

Page 434 - Figure 22−4. Used Bits of Digital Filter Output

SD16_A Operation 22-8 SD16_A Digital Filter Output The number of bits output by the digital filter is dependent on the oversamplingratio and ranges from 15 to 30 bits. Figure 22−4 shows the digital filter outputand their relation to SD16MEM0 for each OSR, LSBACC, and SD16UNIsetting. For example, for...

Page 436 - Table 22−2. Data Format; and the conversion result. The data formats are; Figure 22−5. Input Voltage vs. Digital Output

SD16_A Operation 22-10 SD16_A 22.2.8 Conversion Memory Register: SD16MEM0 The SD16MEM0 register is associated with the SD16_A channel. Conversionresults are moved to the SD16MEM0 register with each decimation step of thedigital filter. The SD16IFG bit is set when new data is written to SD16MEM0.SD16...

Page 437 - Table 22−3. Conversion Mode Summary; Single conversion; Single Conversion; Figure 22−6 shows conversion operation.; Figure 22−6. Single Channel Operation

SD16_A Operation 22-11 SD16_A 22.2.9 Conversion Modes The SD16_A module can be configured for two modes of operation, listed inTable 22−3. The SD16SNGL bit selects the conversion mode. Table 22−3. Conversion Mode Summary SD16SNGL Mode Operation 1 Single conversion The channel is converted once. 0 Co...

Page 438 - Figure 22−7. Typical Temperature Sensor Transfer Function

SD16_A Operation 22-12 SD16_A 22.2.10 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog inputchannel SD16INCHx = 110. Any other configuration is done as if an externalchannel was selected, including SD16INTDLYx and SD16GAINx settings. The typi...

Page 439 - The SD16_A has 2 interrupt sources for its ADC channel:

SD16_A Operation 22-13 SD16_A 22.2.11 Interrupt Handling The SD16_A has 2 interrupt sources for its ADC channel: - SD16IFG - SD16OVIFG The SD16IFG bit is set when the SD16MEM0 memory register is written witha conversion result. An interrupt request is generated if the correspondingSD16IE bit and the...

Page 440 - The SD16_A registers are listed in Table 22−4:

SD16_A Registers 22-14 SD16_A 22.3 SD16_A Registers The SD16_A registers are listed in Table 22−4: Table 22−4. SD16_A Registers Register Short Form Register Type Address Initial State SD16_A Control SD16CTL Read/write 0100h Reset with PUC SD16_A Interrupt Vector SD16IV Read/write 0110h Reset with PU...

Page 441 - REFON

SD16_A Registers 22-15 SD16_A SD16CTL, SD16_A Control Register 15 14 13 12 11 10 9 8 Reserved SD16XDIV SD16LP r0 r0 r0 r0 rw−0 rw−0 rw−0 rw−0 7 6 5 4 3 2 1 0 SD16DIVx SD16SSELx SD16 VMIDON SD16 REFON SD16OVIE Reserved rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 r0 Reserved Bits15-12 Reserved SD16XDIV Bits11-...

Page 444 - SD16INCTL0, SD16_A Input Control Register

SD16_A Registers 22-18 SD16_A SD16INCTL0, SD16_A Input Control Register 7 6 5 4 3 2 1 0 SD16INTDLYx SD16GAINx SD16INCHx rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 SD16INTDLYx Bits7-6 Interrupt delay generation after conversion start. These bits select thedelay for the first interrupt after conversion s...

Page 445 - SD16MEM0, SD16_A Conversion Memory Register; SD16AE, SD16_A Analog Input Enable Register; External input enabled.

SD16_A Registers 22-19 SD16_A SD16MEM0, SD16_A Conversion Memory Register 15 14 13 12 11 10 9 8 Conversion Results r r r r r r r r 7 6 5 4 3 2 1 0 Conversion Results r r r r r r r r ConversionResult Bits15-0 Conversion Results. The SD16MEMx register holds the upper or lower16-bits of the digital fil...

Page 446 - SD16_A interrupt vector value

SD16_A Registers 22-20 SD16_A SD16IV, SD16_A Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 SD16IVx 0 r0 r0 r0 r−0 r−0 r−0 r−0 r0 SD16IVx Bits15-0 SD16_A interrupt vector value SD16IV Contents Interrupt Source Interrupt Flag InterruptPri...

Page 448 - DAC12 Introduction; Note: Multiple DAC12 Modules

DAC12 Introduction 23-2 DAC12 23.1 DAC12 Introduction The DAC12 module is a 12-bit, voltage output DAC. The DAC12 can beconfigured in 8- or 12-bit mode and may be used in conjunction with the DMAcontroller. When multiple DAC12 modules are present, they may be groupedtogether for synchronous update o...

Page 451 - DAC12 Operation; or V; Resolution; DAC12 Port Selection

DAC12 Operation 23-5 DAC12 23.2 DAC12 Operation The DAC12 module is configured with user software. The setup and operationof the DAC12 is discussed in the following sections. 23.2.1 DAC12 Core The DAC12 can be configured to operate in 8- or 12-bit mode using theDAC12RES bit. The full-scale output is...

Page 452 - DAC12 Reference Input and Voltage Output Buffers

DAC12 Operation 23-6 DAC12 23.2.2 DAC12 Reference On MSP430FG43x devices, the reference for the DAC12 is configured to useeither an external reference voltage or the internal 1.5-V/2.5-V reference fromthe ADC12 module with the DAC12SREFx bits. When DAC12SREFx = {0,1}the V REF+ signal is used as the ...

Page 454 - DAC12 Output Amplifier Offset Calibration; Figure 23−5. Negative Offset; Figure 23−6. Positive Offset

DAC12 Operation 23-8 DAC12 23.2.5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative.When the offset is negative, the output amplifier attempts to drive the voltagenegative, but cannot do so. The output voltage remains at zero until...

Page 455 - The DAC12LSELx bits for both DACs must be > 0; DAC12 Settling Time

DAC12 Operation 23-9 DAC12 23.2.6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit tosynchronize the update of each DAC12 output. Hardware ensures that allDAC12 modules in a group update simultaneously independent of anyinterrupt or NMI event. On the MSP4...

Page 457 - DAC12 Registers; The DAC12 registers are listed in Table 23−2.; Reset with POR

DAC12 Registers 23-11 DAC12 23.3 DAC12 Registers The DAC12 registers are listed in Table 23−2. Table 23−2. DAC12 Registers Register Short Form Register Type Address Initial State DAC12_0 control DAC12_0CTL Read/write 01C0h Reset with POR DAC12_0 data DAC12_0DAT Read/write 01C8h Reset with POR DAC12_...

Page 459 - Input Buffer

DAC12 Registers 23-13 DAC12 DAC12CALON Bit 9 DAC12 calibration on. This bit initiates the DAC12 offset calibration sequenceand is automatically reset when the calibration completes.0 Calibration is not active 1 Initiate calibration/calibration in progress DAC12IR Bit 8 DAC12 input range. This bit se...

Page 460 - Unused. These bits are always 0 and do not affect the DAC12 core.; DAC12 Data Format; 2-bit 2’s complement

DAC12 Registers 23-14 DAC12 DAC12_xDAT, DAC12 Data Register 15 14 13 12 11 10 9 8 0 0 0 0 DAC12 Data r(0) r(0) r(0) r(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 DAC12 Data rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Unused Bits15-12 Unused. These bits are always 0 and do not affect t...

Page 461 - Scan IF; Scan IF Introduction

24-1 Scan IF The Scan IF peripheral automatically scans sensors and measures linear orrotational motion. This chapter describes the Scan interface. The Scan IF isimplemented in the MSP430FW42x devices. Topic Page 24.1 Scan IF Introduction 24-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 462 - Scan IF Introduction

Scan IF Introduction 24-2 Scan IF 24.1 Scan IF Introduction The Scan IF module is used to automatically measure linear or rotationalmotion with the lowest possible power consumption. The Scan IF consists ofthree blocks: the analog front end (AFE), the processing state machine (PSM),and the timing st...

Page 463 - Figure 24−1. Scan IF Block Diagram

Scan IF Introduction 24-3 Scan IF Figure 24−1. Scan IF Block Diagram Timing State Machine (TSM) w/ oscillator Processing State Machine (PSM) Analog Input Multiplexer InterruptRequest RotationData ACLK SMCLK Analog Front−End (AFE) SIFCH1 SIFCH0 SIFCH2 SIFCH3 SIFCI0 SIFCOM SIFVSS SIFCI SIFCI1 SIFCI2 S...

Page 464 - Scan IF Operation; Timing State Machine Signals

Scan IF Operation 24-4 Scan IF 24.2 Scan IF Operation The Scan IF is configured with user software. The setup and operation of theScan IF is discussed in the following sections. 24.2.1 Scan IF Analog Front End The Scan IF analog front end provides sensor excitation and measurement.The analog front e...

Page 465 - Figure 24−2. Scan IF Analog Front End Block Diagram

Scan IF Operation 24-5 Scan IF Figure 24−2. Scan IF Analog Front End Block Diagram SIFTESTD SIFTESTS1(tsm) + − 1 0 SIFCH0 SIFCH1 SIFCH2 00 01 10 11 SIFCH3 1 0 SIFCI SIFCISEL SIFCAON SIFCAX SIFCACI3 10 11 01 00 SIFTCH0x 2 SIFTCH1x SIF2OUT SIF3OUT SIFTCH0OUT SIF1OUT SIF0OUT SIFTCH1OUT SIFCAINV SIFRSON...

Page 466 - Excitation; and the SIFCOM input; Mid-Voltage Generator

Scan IF Operation 24-6 Scan IF Excitation The excitation circuitry is used to excite the LC sensors or to power the resistordividers. The excitation circuitry is shown in Figure 24−3 for one LC sensorconnected. When the SIFTEN bit is set and the SIFSH bit is cleared theexcitation circuitry is enable...

Page 468 - Figure 24−4. Analog Input Equivalent Circuit; SIFCHx

Scan IF Operation 24-8 Scan IF Sample-And-Hold The sample-and-hold is used to sample the sensor voltage to be measured.The sample-and-hold circuitry is shown in Figure 24−3. When SIFSH = 1 andSIFTEN = 0 the sample-and-hold circuitry is enabled and the excitationcircuitry and mid-voltage generator ar...

Page 469 - Direct Analog And Digital Inputs; Table 24−1. SIFCAX and SIFSH Input Selection; SIFCAX; Table 24−2. Selected Output Bits; TESTDX

Scan IF Operation 24-9 Scan IF Direct Analog And Digital Inputs By setting the SIFCAX bit, external analog or digital signals can be connecteddirectly to the comparator through the SIFCIx inputs. This allowsmeasurement capabilities for optical encoders and other sensors. Comparator Input Selection A...

Page 470 - Figure 24−5. Analog Front-End Output Timing

Scan IF Operation 24-10 Scan IF When SIFCAX = 1, the SIFCSEL and SIFCI3 bits select between the SIFCIxchannels and the SIFCI input allowing storage of the comparator output forone input signal into the four output bits SIF0OUT - SIF3OUT. This can be usedto observe the envelope function of sensors. T...

Page 471 - Comparator and DAC

Scan IF Operation 24-11 Scan IF Comparator and DAC The analog input signals are converted into digital signals by the comparatorand the programmable 10-bit DAC. The comparator compares the selectedanalog signal to a reference voltage generated by the DAC. If the voltage isabove the reference the com...

Page 472 - Table 24−3. Selected DAC Registers; SIFxOUT; Figure 24−6. Analog Hysteresis With DAC Registers; Table 24−4. DAC Register Select When TESTDX = 1; DAC Register Used

Scan IF Operation 24-12 Scan IF For each input there are two DAC registers to set the reference level as listedin Table 24−3. Together with the last stored output of the comparator,SIFxOUT, the two levels can be used as an analog hysteresis as shown inFigure 24−6. The individual settings for the fou...

Page 473 - Internal Signal Connections to Timer1_A5; Figure 24−7. TimerA Output Stage of the Analog Front End

Scan IF Operation 24-13 Scan IF Internal Signal Connections to Timer1_A5 The outputs of the analog front end are connected to 3 differentcapture/compare registers of Timer1_A5. The output stage of the analog frontend, shown in Figure 24−7. provides two different modes that are selected bythe SIFCS b...

Page 475 - Figure 24−8. Timing State Machine Block Diagram

Scan IF Operation 24-15 Scan IF Figure 24−8. Timing State Machine Block Diagram SIFDIV3Bx State Pointer and Control Start Stop SIFTSM0 SIFTSM23 Set_SIFIFG2 SIFTSMx SIFCH0 SIFCH1 SIFLCOFF SIFEX SIFCA SIFCLKON SIFRSON SIFTESTS1 SIFDAC SIFSTOP SIFACLK SIFREPEAT0 SIFREPEAT1 SIFREPEAT2 SIFREPEAT3 SIFREPE...

Page 476 - TSM Operation; Table 24−5. TSM State Duration

Scan IF Operation 24-16 Scan IF TSM Operation The TSM state machine automatically starts and re-starts periodically basedon a divided ACLK start signal selected with the SIFDIV2x bits the SIFDIV3Axand SIFDIV3Bx bits when SIFTSMRP = 0. For example, if SIFDIV3A andSIFDIV3B are configured to 270 ACLK c...

Page 477 - TSM State Clock Source Select

Scan IF Operation 24-17 Scan IF TSM State Clock Source Select The TSM clock source is individually configurable for each state. The TSM canbe clocked from ACLK or a high frequency clock selected with the SIFACLKbit. When SIFACLK = 1, ACLK is used for the state, and when SIFACLK = 0,the high frequenc...

Page 478 - TSM Test Cycles; Figure 24−9. Test Cycle Insertion

Scan IF Operation 24-18 Scan IF TSM Test Cycles For calibration purposes, to detect sensor drift, or to measure signals otherthan the sensor signals, a test cycle may be inserted between TSM cycles bysetting the SIFTESTD bit. The time between the TSM cycles is not altered bythe test cycle insertion ...

Page 479 - TSM Example; Table 24−6. TSM Example Register Values; TSMx Register; SIFTSM5; Figure 24−10. Timing State Machine Example

Scan IF Operation 24-19 Scan IF TSM Example Figure 24−10 shows an example for a TSM sequence. The TSMx registervalues for the example are shown in Table 24−6. ACLK and SIFCLK are notdrawn to scale. The TSM sequence starts with SIFTSM0 and ends with a setSIFSTOP bit in SIFTSM9. Only the SIFTSM5 to SI...

Page 481 - Figure 24−11. Scan IF Processing State Machine Block Diagram; PSM Operation

Scan IF Operation 24-21 Scan IF Figure 24−11. Scan IF Processing State Machine Block Diagram Q0 Q3 Q4 Q5 Q6 Q7 S2 S1 SIFQ6EN SIFQ7EN Q7 . . . Q0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MSP430Memory Range State Table SIFCNT1 +1 −1 SIFCNT1ENM SIFEN SIFCNT1ENP SIFIS1x SIFCNT2 −1 SIFCNT2EN SIFIS2x Q6 Q7 ∆ 1 ∆ 4 ∆ 64 ∆ ...

Page 482 - Next State Calculation

Scan IF Operation 24-22 Scan IF The current-state and next-state logic are reset while the Scan IF is disabled.One of the bytes stored at addresses SIFPSMV to SIFPSMV + 3 will be loadedfirst depending on the S1 and S2 signals when the Scan IF is enabled. Signals S1 and S2 form a 2-bit offset added t...

Page 483 - PSM Counters

Scan IF Operation 24-23 Scan IF PSM Counters The PSM has two 8-bit counters SIFCNT1 and SIFCNT2. SIFCNT1 is updatedwith Q1 and Q2 and SIFCNT2 is updated with Q2. The counters can be readvia the SIFCNT register. If the SIFCNTRST bit is set, each read access willreset the counters, otherwise the count...

Page 484 - Simplest State Machine; Figure 24−12. Simplest PSM State Diagram

Scan IF Operation 24-24 Scan IF Simplest State Machine Figure 24−12 shows the simplest state machine that can be realized with thePSM. The following code shows the corresponding state table and the PSMinitialization. Figure 24−12. Simplest PSM State Diagram S1=1 & S2=0 S1=0 & S2=0 S1=1 &...

Page 485 - Q1 is set In state 11, so SIFCNT1 will be incremented.

Scan IF Operation 24-25 Scan IF If the PSM is in state 01 of the simplest state machine and the PSM has loadedthe corresponding byte at index 01h of the state table: Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 0 0 0 0 0 0 0 0 For this example, S1 and S2 are set at the end of the next TSM sequence. Tocalculate the next ...

Page 487 - Table 24−7. Scan IF Interrupts; Interrupt

Scan IF Operation 24-27 Scan IF 24.2.5 Scan IF Interrupts The Scan IF has one interrupt vector for seven interrupt flags listed inTable 24−7. Each interrupt flag has its own interrupt enable bit. When aninterrupt is enabled, and the GIE bit is set, the interrupt flag will generate aninterrupt. The i...

Page 488 - Figure 24−14. LC Sensor Oscillations

Scan IF Operation 24-28 Scan IF 24.2.6 Using the Scan IF with LC Sensors Systems with LC sensors use a disk that is partially covered with a dampingmaterial to measure rotation. Rotation is measured with LC sensors byexciting the sensors and observing the resulting oscillation. The oscillation iseit...

Page 489 - Figure 24−15. LC Sensor Connections For The Oscillation Test

Scan IF Operation 24-29 Scan IF 24.2.6.1 LC-Sensor Oscillation Test The oscillation test tests if the amplitude of the oscillation after sensorexcitation is above a reference level. The DAC is used to set the referencelevel for the comparator, and the comparator detects if the LC sensoroscillations ...

Page 490 - Figure 24−16. LC Sensor Connections For The Envelope Test

Scan IF Operation 24-30 Scan IF 24.2.6.2 LC-Sensor Envelope Test The envelop test measures the decay time of the oscillations after sensorexcitation. The oscillation envelope is created by the diodes and RC filters. TheDAC is used to set the reference level for the comparator, and the comparatordete...

Page 491 - Figure 24−17. LC Sensor Connections For The Envelope Test

Scan IF Operation 24-31 Scan IF Figure 24−17. LC Sensor Connections For The Envelope Test PowerSupplyTerminals SIFCI0 SIFCI SIFCI1 SIFCI2 SIFCI3 470 nF AV CC DV CC DV SS AV SS SIFVSS 470 nF SIFCOM SIFCH1 SIFCH0 SIFCH2 SIFCH3

Page 492 - Using the Scan IF With Resistive Sensors; Figure 24−18. Resistive Sensor Connections

Scan IF Operation 24-32 Scan IF 24.2.7 Using the Scan IF With Resistive Sensors Systems with GMRs use magnets on an impeller to measure rotation. Thedamping material and magnets modify the electrical behavior of the sensor sothat rotation and direction can be detected. Rotation is measured with resi...

Page 493 - out of phase with each other are said to be in quadrature. To Create; Figure 24−19. Sensor Position and Quadrature Signals

Scan IF Operation 24-33 Scan IF 24.2.8 Quadrature Decoding The Scan IF can be used to decode quadrature-encoded signals. Signals thatare 90 ° out of phase with each other are said to be in quadrature. To Create the signals, two sensors are positioned depending on the slotting, or coatingof the encod...

Page 494 - Figure 24−20. Quadrature Decoding State Diagram; disk with the sensors 90; Table 24−8. Quadrature Decoding PSM Table

Scan IF Operation 24-34 Scan IF Figure 24−20. Quadrature Decoding State Diagram 00 10 11 01 00 10 11 01 Correct State Transitions Erroneous State Transitions +1 −1 To transfer the state encoding into counts it is necessary to decide whatfraction of the rotation should be counted and on what state tr...

Page 495 - Scan IF Registers; The Scan IF registers are listed in Table 24−9.; Table 24−9. Scan IF Registers

Scan IF Registers 24-35 Scan IF 24.3 Scan IF Registers The Scan IF registers are listed in Table 24−9. Table 24−9. Scan IF Registers Register Short Form Register Type Address Initial State Scan IF debug register SIFDEBUG Read/write 01B0h Unchanged Scan IF counter 1 and 2 SIFCNT Read/write 01B2h Rese...

Page 496 - SIFDEBUG, Scan IF Debug Register, Write Mode; SIFDEBUG, Scan IF Debug Register, Read Mode After 00h Is Written; Last PSM

Scan IF Registers 24-36 Scan IF SIFDEBUG, Scan IF Debug Register, Write Mode 15 14 13 12 11 10 9 8 Reserved w w w w w w w w 7 6 5 4 3 2 1 0 Reserved SIFDEBUGx w w w w w w w w Reserved Bits15-2 Reserved. Must be written as zero. SIFDEBUGx Bits1-0 SIFDEBUG register mode. Writing these bits selects the...

Page 497 - SIFDEBUG, Scan IF Debug Register, Read Mode After 01h Is Written; SIFDEBUG, Scan IF Debug Register, Read Mode After 02h Is Written

Scan IF Registers 24-37 Scan IF SIFDEBUG, Scan IF Debug Register, Read Mode After 01h Is Written 15 14 13 12 11 10 9 8 0 0 0 Index Of TSM Register r r r r r r r r 7 6 5 4 3 2 1 0 PSM Bits Q7 − Q0 r r r r r r r r Unused Bits15-13 Unused. After 01h is written to SIFDEBUG, these bits are always read as...

Page 498 - SIFDEBUG, Scan IF Debug Register, Read Mode After 03h Is Written

Scan IF Registers 24-38 Scan IF SIFDEBUG, Scan IF Debug Register, Read Mode After 03h Is Written 15 14 13 12 11 10 9 8 0 Active DAC Register 0 0 DAC Data r r r r r r r r 7 6 5 4 3 2 1 0 DAC Data r r r r r r r r Unused Bit 15 Unused. After 03h is written to SIFDEBUG, this bit is always read as zero. ...

Page 499 - SIFCNT, Scan IF Counter Register; SIFCNT2x; SIFPSMV, Scan IF Processing State Machine Vector Register

Scan IF Registers 24-39 Scan IF SIFCNT, Scan IF Counter Register 15 14 13 12 11 10 9 8 SIFCNT2x r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) 7 6 5 4 3 2 1 0 SIFCNT1x r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) SIFCNT2x Bits15-8 SIFCNT2. These bits are the SIFCNT2 counter. SIFCNT2 is reset whe...

Page 500 - SIFCTL1, Scan IF Control Register 1

Scan IF Registers 24-40 Scan IF SIFCTL1, Scan IF Control Register 1 15 14 13 12 11 10 9 8 SIFIE6 SIFIE5 SIFIE4 SIFIE3 SIFIE2 SIFIE1 SIFIE0 SIFIFG6 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFIFG5 SIFIFG4 SIFIFG3 SIFIFG2 SIFIFG1 SIFIFG0 SIFTESTD SIFEN rw−(0) rw−(0) rw−(...

Page 501 - SIFIFG0

Scan IF Registers 24-41 Scan IF SIFIFG0 Bit 2 SIF interrupt flag 0. This bit is set by the SIFxOUT conditions selected by theSIFIFGSETx bits. SIFIFG0 must be reset with software.0 No interrupt pending 1 Interrupt pending SIFTESTD Bit 1 Test cycle insertion. Setting this bit inserts a test cycle betw...

Page 502 - SIFCTL2, Scan IF Control Register 2

Scan IF Registers 24-42 Scan IF SIFCTL2, Scan IF Control Register 2 15 14 13 12 11 10 9 8 SIFDACON SIFCAON SIFCAINV SIFCAX SIFCISEL SIFCACI3 SIFVSS SIFVCC2 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFSH SIFTEN SIFTCH1x SIFTCH0x SIFTCH1 OUT SIFTCH0 OUT rw−(0) rw−(0) rw−...

Page 503 - SIFVCC2; SIFSH

Scan IF Registers 24-43 Scan IF SIFVCC2 Bit 8 Mid-voltage generator0 AV CC /2 generator is off 1 AV CC /2 generator is on if SIFSH = 0 SIFSH Bit 7 Sample-and-hold enable0 Sample-and-hold is disabled 1 Sample-and-hold is enabled SIFTEN Bit 6 Excitation enable0 Excitation circuitry is disabled 1 Excit...

Page 504 - SIFCTL3, Scan IF Control Register 3; SIFIS2x

Scan IF Registers 24-44 Scan IF SIFCTL3, Scan IF Control Register 3 15 14 13 12 11 10 9 8 SIFS2x SIFS1x SIFIS2x SIFIS1x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFCS SIFIFGSETx SIF3OUT SIF2OUT SIF1OUT SIF0OUT rw−(0) rw−(0) rw−(0) rw−(0) r−(0) r−(0) r−(0) r−(0) SIFS2x ...

Page 505 - SIFIFGSETx; SIFIFG0 is set when SIF3OUT is reset.; SIF3OUT; AFE output bit 3; SIF2OUT; AFE output bit 2; SIF1OUT; AFE output bit 1; SIF0OUT; AFE output bit 0

Scan IF Registers 24-45 Scan IF SIFIFGSETx Bits6-4 SIFIFG0 interrupt flag source. These bits select when the SIFIFG0 flag is set.000 SIFIFG0 is set when SIF0OUT is set.001 SIFIFG0 is set when SIF0OUT is reset.010 SIFIFG0 is set when SIF1OUT is set.011 SIFIFG0 is set when SIF1OUT is reset.100 SIFIFG0...

Page 506 - SIFCTL4, Scan IF Control Register 4; SIFCNTRST

Scan IF Registers 24-46 Scan IF SIFCTL4, Scan IF Control Register 4 15 14 13 12 11 10 9 8 SIFCNTRST SIFCNT2EN SIFCNT1 ENM SIFCNT1 ENP SIFQ7EN SIFQ6EN SIFDIV3Bx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFDIV3Bx SIFDIV3Ax SIFDIV2x SIFDIV1x rw−(0) rw−(0) rw−(0) rw−(0) rw...

Page 508 - SIFCTL5, Scan IF Control Register 5; SIFCNT3x; No internal oscillator calibration is started.; SIFCLKEN; TSM high frequency clock source is SMCLK.

Scan IF Registers 24-48 Scan IF SIFCTL5, Scan IF Control Register 5 15 14 13 12 11 10 9 8 SIFCNT3x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFTSMRP SIFCLFQx SIFFNOM SIFCLKG ON SIFCLKEN rw−(0) rw−(1) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFCNT3x Bits15-8 Internal ...

Page 510 - SIFTSMx, Scan IF Timing State Machine Registers; SIFACLK

Scan IF Registers 24-50 Scan IF SIFTSMx, Scan IF Timing State Machine Registers 15 14 13 12 11 10 9 8 SIFREPEATx SIFACLK SIFSTOP SIFDAC rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 SIFTESTS1 SIFRSON SIFCLKON SIFCA SIFEX SIFLCEN SIFCHx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−...

Page 511 - SIFCLKON; High-frequency clock is off for this state when SIFACLK = 1; SIFCA; Comparator off during this state; SIFEX; All SIFCHx channels are internally damped. No LC oscillations.

Scan IF Registers 24-51 Scan IF SIFCLKON Bit 5 High-frequency clock on. Setting this bit turns the high-frequency clock sourceon for this state when SIFACLK = 1, even though the high frequency clock isnot used for the TSM. When the high-frequency clock is sourced from theDCO, the DCO is forced on fo...

Page 512 - Processing State Machine Table Entry (MSP430 Memory Location); Bit 5 of the next state.

Scan IF Registers 24-52 Scan IF Processing State Machine Table Entry (MSP430 Memory Location) 7 6 5 4 3 2 1 0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Bit 7 When Q7 = 1, SIFIFG6 will be set. When SIFQ6EN = 1 and SIFQ7EN = 1and Q7 = 1, the PSM proceeds to the next state immediately, regardless ofthe SIFSTOP(tsm) s...

Texas Instruments MSP430x4xx - Manual

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