Cypress STK22C48 - Manual
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Table of Contents:
- Page 2 – Pin Configurations; Top View
- Page 3 – Figure 2; WRITE; AutoStore Inhibit mode; Figure 3; Figure 2. AutoStore Mode
- Page 4 – Figure 3. AutoStore Inhibit Mode; Data Protection; Figure 4
- Page 6 – DC Electrical Characteristics
- Page 7 – Capacitance; Thermal Resistance; AC Test Conditions
- Page 8 – AC Switching Characteristics; SRAM Read Cycle; Switching Waveforms
- Page 9 – SRAM Write Cycle
- Page 11 – Hardware STORE Cycle; Switching Waveform
- Page 12 – Ordering Information; Ordering Code; Commercial
- Page 13 – Package Diagrams
- Page 14 – Document History Page; Worldwide Sales and Design Support; Change
STK22C48
16 Kbit (2K x 8) AutoStore nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-51000 Rev. **
Revised January 30, 2009
Features
■
25 ns and 45 ns access times
■
Hands off automatic STORE on power down with external 68
µF capacitor
■
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■
RECALL to SRAM initiated by software or power up
■
Unlimited Read, Write, and Recall cycles
■
1,000,000 STORE cycles to QuantumTrap
■
100 year data retention to QuantumTrap
■
Single 5V+10% operation
■
Commercial and industrial temperatures
■
28-pin 300 mil and (330 mil) SOIC package
■
RoHS compliance
Functional Description
The Cypress STK22C48 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. A hardware STORE is initiated with
the HSB pin.
STORE/
RECALL
CONTROL
POWER
CONTROL
STATIC RAM
ARRAY
32 X 512
Quantum Trap
32 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT
BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
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Summary
STK22C48 Document Number: 001-51000 Rev. ** Page 2 of 14 Pin Configurations Figure 1. Pin Diagram - 28-Pin SOIC Table 1. Pin Definitions Pin Name Alt IO Type Description A 0 –A 10 Input Address Inputs. Used to select one of the 2,048 bytes of the nvSRAM. DQ 0 -DQ 7 Input or Output Bidirectional Data...
STK22C48 Document Number: 001-51000 Rev. ** Page 3 of 14 Device Operation The STK22C48 nvSRAM is made up of two functional compo-nents paired in the same physical cell. These are an SRAMmemory cell and a nonvolatile QuantumTrap cell. The SRAMmemory cell operates as a standard fast static RAM. Data i...
STK22C48 Document Number: 001-51000 Rev. ** Page 4 of 14 Figure 3. AutoStore Inhibit Mode Hardware STORE (HSB) Operation The STK22C48 provides the HSB pin for controlling andacknowledging the STORE operations. The HSB pin is used torequest a hardware STORE cycle. When the HSB pin is drivenLOW, the S...
