Cypress STK14D88 - Manual
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Table of Contents:
- Page 2 – SS
- Page 3 – Absolute Maximum Ratings; DC Characteristics; STORE
- Page 4 – Figure 2
- Page 7 – AutoStore/POWER UP RECALL; RECALL
- Page 9 – Hardware STORE Cycle; Soft Sequence Commands
- Page 10 – Mode Selection; Mode
- Page 11 – nvSRAM Operation; nvSRAM; Figure 12. AutoStore Mode; Software STORE
- Page 13 – Figure 13. Current versus Cycle Time; Noise Considerations; Preventing AutoStore; AutoStore Disable; er; Writes
- Page 14 – Part Number
- Page 15 – Package Diagrams; PIN 1 ID; REFERENCE JEDEC MO-119
- Page 17 – Document History Page; Worldwide Sales and Design Support
STK14D88
32Kx8 AutoStore™ nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-52037 Rev. **
Revised March 02, 2009
Features
■
25, 35, 45 ns Read Access and R/W Cycle Time
■
Unlimited Read/Write Endurance
■
Automatic Nonvolatile STORE on Power Loss
■
Nonvolatile STORE Under Hardware or Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited RECALL Cycles
■
200K STORE Cycles
■
20-Year Nonvolatile Data Retention
■
Single 3.0V +20%, -10% Power Supply
■
Commercial, Industrial Temperatures
■
Small Footprint SOIC and SSOP Packages (RoHS-Compliant)
Description
The Cypress STK14D88 is a 256Kb fast static RAM with a
nonvolatile Quantum Trap™ storage element included with each
memory cell.
The SRAM provides fast access and cycle times, ease of use,
and unlimited read and write endurance of a normal SRAM.
Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.
A
0
A
1
A
2
A
3
A
4
A
10
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
512 x 512
ROW DECODER
INPUT
BUFF
ERS
Quantum Trap
512 x 512
STORE/
RECALL
CONTROL
STORE
RECALL
POWER
CONTROL
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
SOFTWARE
DETECT
G
E
W
HSB
V
CCX
V
CAP
A
0
- A
13
Logic Block Diagram
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Summary
STK14D88 Document Number: 001-52037 Rev. ** Page 2 of 17 Pin Configurations Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC Pin Descriptions Pin Name I/O Description A 14 -A 0 Input Address : The 15 address inputs select one of 32,768 bytes in the nvSRAM array DQ 7 -DQ 0 I/O Data : Bi-directional 8-bit da...
STK14D88 Document Number: 001-52037 Rev. ** Page 3 of 17 Absolute Maximum Ratings Voltage on Input Relative to Ground................. –0.5V to 4.1V Voltage on Input Relative to V SS ...........–0.6V to (V CC + 0.5V) Voltage on DQ 0-7 or HSB ......................–0.5V to (V CC + 0.5V) Temperature u...
STK14D88 Document Number: 001-52037 Rev. ** Page 4 of 17 V OL Output Logic “0” Voltage 0.4 0.4 V I OUT = 4mA T A Operating Temperature 0 70 - 40 85 ° C V CC Operating Voltage 2.7 3.6 2.7 3.6 V 3.3V +20%, -10% V CAP Storage Capacitance 17 120 17 120 μ F Between V CAP pin and V SS , 5V Rated DATA R Da...
