Cypress CY7C68003 - Manual
Cypress CY7C68003 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Functional Overview; Table 5; DP and DM pins; Table 1
- Page 3 – Clocking; Figure 3; Power Domains; XTAL
- Page 4 – Operation Modes; Figure 3. Mode Change State Diagram
- Page 5 – VID and PID; Table 6
DATA BRIEF
CY7C68003
MoBL-USB™ TX2UL USB 2.0
ULPI Transceiver
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 1, 2009
Features
The Cypress MoBL-USB
™
TX2UL is a low voltage high speed
(HS) USB 2.0 ULPI Transceiver.
The TX2UL is specifically designed for mobile handset
applications by offering tiny package options and low power
consumption.
■
USB 2.0 Full Speed and High Speed Compliant Transceiver
■
Multi-Range (1.8V to 3.3V) IO Voltages
■
Fully Compliant ULPI Link Interface
■
8-bit SDR ULPI Data Path
■
UTMI+ Level 0 Support
■
Integrated Oscillator
■
Integrated PLL (13, 19.2, 24, or 26 MHz Reference)
■
Integrated USB Pull Up and Termination Resistors
■
3.0V to 5.775V VBATT Input
■
Chip Select Pin
■
Single Ended Device RESET Input
■
UART Pass Through Mode
■
ESD Compliance:
❐
JESD22-A114D 8 kV Contact Human Body Model (HBM) for
DP, DM, and VSS Pins
❐
IEC61000-4-2 8 kV Contact Discharge
❐
IEC61000-4-2 15 kV Air Discharge
■
Support for Industrial Temperature Range (-40°C to 85°C)
■
Low Power Consumption for Mobile Applications:
❐
5 uA Nominal Sleep Mode
❐
30 mA Nominal Active HS Transfer
■
Small Package for Mobile Applications:
❐
2.14 x 1.76 mm 20-pin WLCSP 0.4 mm Pitch
❐
4 x 4 mm 24-pin QFN
Applications
■
Mobile Phones
■
PDAs
■
Portable Media Players (PMPs)
■
DTV Applications
■
Portable GPS Units
TX2UL
ULPI Block
XOSC
ULPI Wrapper
UTMI+
Level0
DATA[7:0]
CLOCK
DIR
STP
NXT
XI
XO
VBATT
13/19.2/
24/26 MHz
RESET_N
DP
DM
IO
Control/
Data
Logic
Operational
mode
tracking
interrupt
Tx/Rx
Core
Registers
Block
Global Control Block
Reset / Clock / Power /
Misc. Control
POR
PLL
1.8V
Bandgap
USB
FS/HS
PHY
CS_N
3.3V Regulator
Block
(3.0 –
5.775V)
VCC
(1.8V)
RXD
TXD
TX2UL Block Diagram
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Summary
CY7C68003 Page 2 of 5 Functional Overview UTMI+ Low Pin Interface (ULPI) This block conforms to the ULPI Specification. It supports the8-bit wide SDR data path. The primary IOs of this block supportmulti-range LVCMOS signaling from 1.8V to 3.3V (±5%). Thelevel used is automatically selected by the v...
CY7C68003 Page 3 of 5 Clocking TX2UL supports external crystal and clock inputs at the 13, 19.2,24, and 26 MHz frequencies. The internal PLL applies the properclock multiply option depending on the input frequency. For appli-cations that use an external clock source to drive XI, the XO pin(in 24-pin...
CY7C68003 Page 4 of 5 Operation Modes There are six operation modes available in TX2UL. They are: ■ Normal Operation Mode ■ Configuration Mode ■ ULPI Low Power Mode ■ Sleep Mode ■ Carkit UART Pass Through Mode ■ Tri-state ULPI Interface Output Mode (only available in 24-pin QFN package) When changin...
