Cypress CY7C1365C - Manual
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Table of Contents:
- Page 3 – Pin Configurations
- Page 5 – Pin Descriptions
- Page 7 – Functional Overview; DD
- Page 9 – Truth Table for Read/Write; Read
- Page 10 – Electrical Characteristics
- Page 11 – Capacitance; Thermal Resistance; AC Test Loads and Waveforms
- Page 12 – Switching Characteristics
- Page 13 – Timing Diagrams; Read Cycle Timing
- Page 14 – Write Cycle Timing
- Page 16 – Ordering Information; Commercial; CLK
- Page 17 – Package Diagram
- Page 18 – Document History Page; Issue Date
9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1365C
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05690 Rev. *E
Revised September 14, 2006
Features
• 256K x 32 common I/O
• 3.3V core power supply (V
DD
)
• 2.5V/3.3V I/O power supply (V
DDQ
)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V I/O level
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• “ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1365C is a 256K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
[2]
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1365C allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and Chip Enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1365C operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Notes:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
is not available on 2 Chip Enable TQFP package.
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
250
180
mA
Maximum Standby Current
40
40
mA
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Summary
CY7C1365C Document #: 38-05690 Rev. *E Page 3 of 18 Pin Configurations 100-Pin TQFP Pinout (2 Chip Enable) (AJ version) A A A A A 1 A 0 NC NC V SS V DD NC A A A A A A NC DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A...
CY7C1365C Document #: 38-05690 Rev. *E Page 5 of 18 Pin Descriptions Name TQFP I/O Description A0, A1, A 37,36,32,33,34,35,44,45,46,47,48,49,50,81,82,99,10092 (for 2 Chip Enable Version)43 (for 3 Chip Enable Version) Input- Synchronous Address Inputs used to select one of the 256K address locations ...
CY7C1365C Document #: 38-05690 Rev. *E Page 7 of 18 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. Maximum access delay fromthe clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1365C supports secondary cache in systemsutilizi...
