Cypress CY7C1339G - Manual
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Table of Contents:
- Page 2 – Unit
- Page 5 – DD; ZZ Mode Electrical Characteristics
- Page 6 – Truth Table
- Page 7 – Partial Truth Table for Read/Write
- Page 8 – Electrical Characteristics
- Page 10 – Switching Characteristics
- Page 11 – Switching Waveforms; Read Cycle Timing
- Page 12 – Write Cycle Timing
- Page 13 – Read/Write Cycle Timing
- Page 14 – ZZ Mode Timing
- Page 15 – Ordering Information
- Page 16 – Package Diagrams
- Page 18 – Document History Page; Change
4-Mbit (128K x 32) Pipelined Sync SRAM
CY7C1339G
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05520 Rev. *F
Revised July 5, 2006
Features
• Registered inputs and outputs for pipelined operation
• 128K × 32 common I/O architecture
• 3.3V core power supply (V
DD
)
• 2.5V/3.3V I/O power supply (V
DDQ
)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1339G SRAM integrates 128K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:D]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1339G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
1
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
A D D R E SS
R E G IST E R
A D V
CLK
B U R ST
CO U N T E R
A N D
LO G IC
CLR
Q 1
Q 0
A D SP
A D SC
M O D E
B W E
G W
CE
1
CE
2
CE
3
O E
E N A B LE
R E G IST E R
O U T PU T
R E G IST E R S
SE N SE
A M PS
O U T PU T
B U FFE R S
E
PIPE LIN E D
E N A B LE
IN PU T
R E G IST E R S
A 0, A 1, A
B W
B
BW
C
B W
D
B W
A
M E M O R Y
A R R A Y
D Q s
SLE E P
CO N T R O L
ZZ
A
[ 1: 0]
2
DQ
A
B Y TE
W R ITE R E G ISTE R
DQ
B
B Y TE
W R ITE R E G ISTE R
DQ
C
B Y TE
W R ITE R E G ISTE R
DQ
D
B Y TE
W R ITE R E G ISTE R
DQ
A
B Y TE
W R ITE DR IV E R
DQ
B
B Y TE
W R ITE DR IV E R
DQ
C
B Y TE
W R ITE DR IV E R
DQ
D
B Y TE
W R ITE DR IV E R
Logic Block Diagram
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Summary
CY7C1339G Document #: 38-05520 Rev. *F Page 2 of 18 Pin Configurations Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access Time 2.6 2.8 3.5 4.0 ns Maximum Operating Current 325 265 240 225 mA Maximum CMOS Standby Current 40 40 40 40 mA A A A A A 1 A 0 N C /72M NC/36M V SS V DD NC/18 ...
CY7C1339G Document #: 38-05520 Rev. *F Page 5 of 18 signal. Consecutive single Read cycles are supported. Oncethe SRAM is deselected at clock rise by the chip select andeither ADSP or ADSC signals, its output will tri-state immedi-ately. Single Write Accesses Initiated by ADSP This access is initiat...
CY7C1339G Document #: 38-05520 Rev. *F Page 6 of 18 Truth Table [2, 3, 4, 5, 6, 7] Operation Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power-down None H X X L X L X X X L-H Tri-State Deselect Cycle, Power-down None L L X L L X X X X L-H Tri-State Deselect Cycle, Power...
