Cypress CY7C1019BN - Manual
Cypress CY7C1019BN – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Electrical Characteristics
- Page 3 – Parameter
- Page 4 – Data Retention Characteristics; Data Retention Waveform
- Page 5 – Switching Waveforms
- Page 6 – Truth Table; Ordering Information
- Page 7 – Package Diagrams
- Page 8 – Document History Page; Issue Date; See ECN
128K x 8 Static RAM
CY7C1019BN
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-06425 Rev. **
Revised February 1, 2006
Features
• High speed
— t
AA
= 12, 15 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE
and OE options
• Functionally equivalent to CY7C1019
Functional Description
The CY7C1019BN is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019BN is available in standard 32-pin TSOP Type
II and 400-mil-wide SOJ packages.
14
15
Logic Block Diagram
Pin Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DE
CODE
R
SE
N
SE A
M
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
A
10
CE
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15
17
18
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
A
13
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
10
A
9
I/O
2
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
A
8
I/O
3
WE
V
SS
A
14
V
SS
/ TSOPII
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Summary
CY7C1019BN Document #: 001-06425 Rev. ** Page 2 of 8 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied .............................................
CY7C1019BN Document #: 001-06425 Rev. ** Page 3 of 8 AC Test Loads and Waveforms Switching Characteristics [4] Over the Operating Range Parameter Description -12 -15 Unit Min. Max. Min. Max. Read Cycle t RC Read Cycle Time 12 15 ns t AA Address to Data Valid 12 15 ns t OHA Data Hold from Address Cha...
CY7C1019BN Document #: 001-06425 Rev. ** Page 4 of 8 Data Retention Characteristics Over the Operating Range (L Version Only) Parameter Description Conditions Min. Max. Unit V DR V CC for Data Retention No input may exceed V CC + 0.5V V CC = V DR = 2.0V, CE > V CC – 0.3V, V IN > V CC – 0.3V or...
