Cypress CY7C1018DV33 - Manual
Cypress CY7C1018DV33 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – CC; DC Electrical Characteristics
- Page 3 – Capacitance; Input Capacitance; pF; Output Capacitance; Thermal Resistance; AC Test Loads and Waveforms; GND
- Page 4 – AC Switching Characteristics; Parameter
- Page 5 – Data Retention Characteristics; Data Retention Waveform
- Page 6 – Switching Waveforms
- Page 7 – Truth Table; Ordering Information; DATA VALID
- Page 8 – Package Diagram; DIMENSIONS IN INCHES
- Page 9 – Document History Page; Issue Date
1-Mbit (128K x 8) Static RAM
CY7C1018DV33
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05465 Rev. *D
Revised November 8, 2006
Features
• Pin- and function-compatible with CY7C1018CV33
• High speed
— t
AA
= 10 ns
• Low Active Power
— I
CC
= 60 mA @ 10 ns
• Low CMOS Standby Power
— I
SB2
= 3 mA
• 2.0V Data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Center power/ground pinout
• Easy memory expansion with CE
and OE options
• Available in Pb-free 32-pin 300-Mil wide Molded SOJ
Functional Description
[1]
The CY7C1018DV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil
wide Molded SOJ.
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
O
W
DE
CO
DE
R
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
13
A
11
A
12
A
9
A
10
128K × 8
ARRAY
A
14
A
15
A
16
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15
17
18
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
A
13
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
10
A
9
I/O
2
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
A
8
I/O
3
WE
V
SS
A
14
V
SS
Pin Configuration
Note
1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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Summary
CY7C1018DV33 Document #: 38-05465 Rev. *D Page 2 of 9 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ............................................
CY7C1018DV33 Document #: 38-05465 Rev. *D Page 3 of 9 Capacitance [3] Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = 3.3V 8 pF C OUT Output Capacitance 8 pF Thermal Resistance [3] Parameter Description Test Conditions 400-Mil Wide SOJ Unit Θ JA T...
CY7C1018DV33 Document #: 38-05465 Rev. *D Page 4 of 9 AC Switching Characteristics Over the Operating Range [5] Parameter Description –10 (Industrial) Unit Min. Max. Read Cycle t power [6] V CC (typical) to the first access 100 µ s t RC Read Cycle Time 10 ns t AA Address to Data Valid 10 ns t OHA Da...
