Cypress CY62148BN - Manual
Cypress CY62148BN – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Pin; CC; Com’l; SOIC
- Page 3 – Electrical Characteristics
- Page 4 – Switching Characteristics; Parameter
- Page 5 – Data Retention Characteristics; Data Retention Waveform
- Page 6 – Switching Waveforms; HZCE
- Page 7 – Truth Table; SB; Ordering Information; DATA VALID
- Page 8 – Package Diagrams; PACKAGE WEIGHT 1.42gms
- Page 10 – Document History Page; Issue
4-Mbit (512K x 8) Static RAM
CY62148BN MoBL
®
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-06517 Rev. *A
Revised August 2, 2006
Features
• High Speed
— 70 ns
• 4.5V–5.5V operation
• Low active power
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current: 12.5 mA @ f = f
max
(70 ns)
•
Low standby current
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
and OE features
• CMOS for optimum speed/power
• Available in standard lead-free and non-lead-free
32-lead (450-mil) SOIC, 32-lead TSOP II and 32-lead
Reverse TSOP II packages
Functional Description
The CY62148BN is a high-performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
consumption by more than 99% when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
18
13
Logic Block Diagram
A
1
A
4
A
5
A
6
A
7
A
12
A
14
A
16
COLUMN
DECODER
ROW DE
CODE
R
S
E
N
SE AM
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512
x
K
8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
2
A
15
A
3
A
CE
A
A
8
A
17
A
9
A
11
A
10
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Summary
CY62148BN MoBL ® Document #: 001-06517 Rev. *A Page 2 of 10 Note: 1. Typical values are measured at V CC = 5V, T A = 25°C, and are included for reference only and are not tested or guaranteed. Pin Configuration Product Portfolio Product V CC Range Speed Temp. Power Dissipation Operating, I CC Standb...
CY62148BN MoBL ® Document #: 001-06517 Rev. *A Page 3 of 10 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ......................................
CY62148BN MoBL ® Document #: 001-06517 Rev. *A Page 4 of 10 Switching Characteristics [5] Over the Operating Range Parameter Description 62148BNLL-70 Unit Min. Max. READ CYCLE t RC Read Cycle Time 70 ns t AA Address to Data Valid 70 ns t OHA Data Hold from Address Change 10 ns t ACE CE LOW to Data V...
