Cypress CY14B101L - Manual
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Table of Contents:
- Page 2 – SS
- Page 3 – Figure 2; Figure 2. AutoStore Mode
- Page 4 – Figure 3; Figure 3. Current Versus Cycle Time
- Page 6 – Notes
- Page 7 – DC Electrical Characteristics
- Page 8 – IN; Thermal Resistance; JC; AC Test Conditions; Note
- Page 9 – AC Switching Characteristics; SRAM Read Cycle; Switching Waveforms
- Page 10 – SRAM Write Cycle
- Page 11 – AutoStore or Power Up RECALL; Power up RECALL Duration
- Page 13 – Hardware STORE Cycle; PHSB; Hardware STORE Pulse Width; Time Allowed to Complete SRAM Cycle; ss; Soft Sequence Processing Time
- Page 14 – Ordering Information; Commercial; Part Numbering Nomenclature
- Page 15 – Package Diagrams; PIN 1 ID; REFERENCE JEDEC MO-119
- Page 17 – Document History Page; Submission
CY14B101L
1 Mbit (128K x 8) nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-06400 Rev. *I
Revised January 30, 2009
Features
■
25 ns, 35 ns, and 45 ns access times
■
Pin compatible with STK14CA8
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■
RECALL to SRAM initiated by software or power up
■
Unlimited READ, WRITE, and RECALL cycles
■
200,000 STORE cycles to QuantumTrap
■
20 year data retention at 55
°
C
■
Single 3V +20%
,
–10% operation
■
Commercial and industrial temperature
■
32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages
■
RoHS compliance
Functional Description
The Cypress CY14B101L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
1024 X 1024
QuantumTrap
1024 x 1024
STORE
RECALL
COLUMN IO
COLUMN DEC
ROW DECODER
INPUT
BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
15
-
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
11
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
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Summary
CY14B101L Document Number: 001-06400 Rev. *I Page 2 of 18 Pinouts Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP Pin Definitions Pin Name Alt IO Type Description A 0 –A 16 Input Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM. DQ 0 -DQ 7 Input or Output Bidirectional Data ...
CY14B101L Document Number: 001-06400 Rev. *I Page 3 of 18 Device Operation The CY14B101L nvSRAM is made up of two functional compo-nents paired in the same physical cell. These are an SRAMmemory cell and a nonvolatile QuantumTrap cell. The SRAMmemory cell operates as a standard fast static RAM. Data...
CY14B101L Document Number: 001-06400 Rev. *I Page 4 of 18 Hardware RECALL (Power Up) During power up or after any low power condition (V CC < V SWITCH ), an internal RECALL request is latched. When V CC once again exceeds the sense voltage of V SWITCH , a RECALL cycle is automatically initiated a...
