Page 2 - RECOMMENDED OPERATING CONDITIONS
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 2 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam duringstorage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION T A O...
Page 3 - ELECTRICAL CHARACTERISTICS
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 3 ELECTRICAL CHARACTERISTICS T J = − 40 ° C to 125 ° C, V I = 4 V to 6 V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN Input voltage range, VIN 4.0 6.0 V f s = 350 kHz, SYNC ≤ 0.8 V, RT open, P...
Page 4 - ELECTRICAL CHARACTERISTICS CONTINUED
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 4 ELECTRICAL CHARACTERISTICS CONTINUED T J = − 40 ° C to 125 ° C, V I = 4 V to 6 V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Error amplifier open loop voltage gain 1 k Ω COMP to AGND (1) 90 110...
Page 5 - PWP PACKAGE; Terminal Functions; TERMINAL
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 5 1234 567891011121314 2827262524232221201918171615 AGND VSENSE COMP PWRGD BOOT PHPHPHPHPHPHPHPHPH RTSYNCSS/ENAVBIASVINVINVINVINVINPGNDPGNDPGNDPGNDPGND PWP PACKAGE (TOP VIEW) THERMAL PAD Terminal Functions TERMINAL DESCRIPTION NAME N...
Page 6 - FUNCTIONAL BLOCK DIAGRAM; RELATED DC/DC PRODUCTS
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 6 FUNCTIONAL BLOCK DIAGRAM Falling Edge Deglitch Enable Comparator 1.2 V VIN 3.8 V Hysteresis: 0.03 V 2.5 µ s Falling and Rising Edge Deglitch 2.5 µ s VIN UVLO Comparator Hysteresis: 0.16 V Internal/External Slow-Start (Internal Slow...
Page 7 - TYPICAL CHARACTERISTICS
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 7 TYPICAL CHARACTERISTICS Figure 1 0 10 20 30 40 50 60 − 40 − 15 10 35 60 85 110 135 V I = 5 V, I O = 8 A DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE T J − Junction Temperature − ° C Drain Source On-State Reststance − m ...
Page 8 - Figure 9. Application Circuit; Switching Frequency
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 8 APPLICATION INFORMATION Figure 9 shows the schematic diagram for a typical TPS54810 application. The TPS54810 (U1) can provideup to 8 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the Pow...
Page 9 - PCB LAYOUT
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 9 PCB LAYOUT Figure 10 shows a generalized PCB layout guide for the TPS54810 The VIN pins are connected together on the printed-circuit board (PCB) and bypassed with a low-ESR ceramic-bypass capacitor. Care should be taken tominimize...
Page 10 - Figure 10. PCB Layout
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 10 AGND BOOT VSENSE COMP PWRGD PH PH PH PH PH PH PH PH PH RT SYNC SS/ENA VBIAS VIN VIN VIN VIN VIN PGND PGND PGND PGND PGND VOUT PH VIN TOPSIDE GROUND AREA VIA to Ground Plane ANALOG GROUND TRACE EXPOSED POWERP AD AREA COMPENSA TION ...
Page 11 - any area available should be used when 8 A or greater; Figure 11. Recommended Land Pattern for the 28
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 11 LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog groundplane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended,though not manda...
Page 12 - PERFORMANCE GRAPHS (FROM APPLICATION CIRCUIT SHOWN IN FIGURE 9)
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 12 PERFORMANCE GRAPHS (FROM APPLICATION CIRCUIT SHOWN IN FIGURE 9) Figure 12 I O − Output Current − A Efficiency − % EFFICIENCY vs OUTPUT CURRENT 50 55 60 65 70 75 80 85 90 95 100 0 2 4 6 8 10 V I = 5 V V O = 1.8 V f s = 700 kHz Figu...
Page 13 - DETAILED DESCRIPTION; td; Voltage Reference; Oscillator and PWM Ramp; QUENCY; Error Amplifier
TPS54810 SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 www.ti.com 13 DETAILED DESCRIPTION Under Voltage Lock Out (UVLO) The TPS54810 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage(VIN) is insufficient. During power up, internal circuits areheld inac...
Page 15 - PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TPS54810PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS54810PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/...
Page 16 - TAPE AND REEL INFORMATION; PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TPS54810PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com ...
Page 17 - Device
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54810PWPR HTSSOP PWP 28 2000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2
Page 21 - IMPORTANT NOTICE; Products
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...