Page 2 - Introduction
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Contents 1 F280x, F2801x, C280x DSPs .............................................................................................
Page 4 - Migrating From F280x Devices to C280x Devices; Migration Issues; Revision History
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6.13 ROM Timing (C280x only) .............................................................................................. 132...
Page 9 - Digital Signal Processors; Check for; Features
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Digital Signal Processors Check for Samples: TMS320F2809 , TMS320F2808 , TMS320F2806 , TMS320F2802 , TMS320F2801 , TMS320C280...
Page 10 - Getting Started; SPRAAM0
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com • Package Options • Temperature Options: – Thin Quad Flatpack (PZ) – A: –40°C to 85°C (PZ, GGM, ZGM) – MicroStar BGA™ (GGM, ZGM...
Page 11 - Throughout
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 2 Introduction The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320F28015,TMS320F28016, TMS320C2802, a...
Page 14 - Pin Assignments; ball grid array (BGA) terminal assignments are shown in
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GPIO0/E...
Page 18 - Bottom View
4 C B A D E 2 1 3 K F G H J 5 7 6 9 8 10 Bottom View TRST TCK TDI TDO TMS EMU0 EMU1 V DD3VFL TEST1 TEST2 XCLKOUT XCLKIN X1 X2 XRS GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO9 GPIO8 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO2...
Page 19 - Signal Descriptions
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 2.2 Signal Descriptions Table 2-3 describes the signals on the 280x devices. All digital inputs are TTL-compatible. All outpu...
Page 24 - NOTE
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Signal Descriptions (continued) PIN NO. GGM/ NAME DESCRIPTION (1) PZ ZGM PIN # BALL # GPIO33 General-Purpose Input/Output 33 (I...
Page 25 - Functional Overview
INT[12:1] Real-Time JTAG (TDI, TDO, TRST, TCK, TMS, EMU0, EMU1) C28x CPU (100 MHz) NMI, INT13 Memory Bus INT14 SYSCLKOUT RS CLKIN 12-Bit ADC ADCSOCA/B SOCA/B 16 Channels 12 6 32 XCLKOUT XRS XCLKIN X1 X2 32 System Control (Oscillator, PLL, Peripheral Clocking, Low-Power Modes, Watchdog) ePWM1/2/3/4/5...
Page 26 - Memory Maps
ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ 0x00 0000 Block Start Address Data Space Prog Space M0 Vector − RAM (32 x 32) (Enabled if VMAP = 0) M1 SARAM (1K y 16) 0x00 0400 Peripheral Frame 0 0x00 0800 ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ 0x00 0D00 Peripheral Frame 1 (protected)...
Page 31 - Table 3-1. Addresses of Flash Sectors in F2809; Table 3-2. Addresses of Flash Sectors in F2808
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 3-1. Addresses of Flash Sectors in F2809 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3D 8000 – 0x3D BFFF Sector H (16K x 16)...
Page 32 - shows how to handle these memory locations.; Table 3-5. Impact of Using the Code Security Module
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Table 3-4. Addresses of Flash Sectors in F2801, F28015, F28016 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3F 4000 – 0x3F 4FFF Secto...
Page 34 - Brief Descriptions; Peripheral Bus
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 3.2 Brief Descriptions 3.2.1 C28x CPU The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x ...
Page 35 - ROM
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 3.2.4 Real-Time JTAG and Analysis The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x support...
Page 36 - Boot ROM; MODE
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 3.2.8 L0, L1, H0 SARAMs The F2809 and F2808 each contain an additional 16K x 16 of single-access RAM, divided into 3 blocks(L0-...
Page 40 - Register Map
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speedmeasurement using capture unit and high-spe...
Page 43 - Figure 3-7. External and PIE Interrupt Sources
XINT2 C28 CPU CPU TIMER 2 (Reserved for DSP/BIOS) CPU TIMER 0 Watchdog Peripherals (SPI, SCI, I2C, eCAN, ePWM, eCAP, eQEP, ADC) TINT0 Interrupt Control XNMICR(15:0) XINT1 Interrupt Control XINT1 XINT1CR(15:0) Interrupt Control XINT2 XINT2CR(15:0) GPIO MUX WDINT INT1 to INT12 INT13 INT14 NMI XINT1CTR...
Page 44 - Figure 3-8. Multiplexing of Interrupts Using the PIE Block
INT12 MUX INT11 INT2 INT1 CPU (Enable) (Flag) INTx INTx.8 PIEIERx(8:1) PIEIFRx(8:1) MUX INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 From Peripherals or External Interrupts (Enable) (Flag) IER(12:1) IFR(12:1) Global Enable INTM 1 0 PIEACKx (Enable/Flag) TMS320F2809, TMS320F2808, TMS320F2806TMS32...
Page 45 - Table 3-13. PIE Configuration and Control Registers; External Interrupts
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 3-13. PIE Configuration and Control Registers NAME ADDRESS SIZE (x16) DESCRIPTION (1) PIECTRL 0x0CE0 1 PIE, Control Reg...
Page 46 - System Control
PLL X1 X2 PowerModesControl Watchdog Block 28xCPU Peripheral Bus Low-Speed Peripherals SCI-A/B, SPI-A/B/C/D Peripheral Registers High-Speed Prescaler Low-Speed Prescaler Clock Enables GPIOMUX SystemControl Registers XCLKIN ADC Registers 12-Bit ADC 16 ADC inputs LSPCLK I/O Peripheral Reset SYSCLKOUT ...
Page 47 - OSC and PLL Block; shows the OSC and PLL block on the 280x.
X1 XCLKIN (3.3-V clock input) On chip oscillator X2 xor PLLSTS[OSCOFF] OSCCLK PLL VCOCLK 4-bit PLL Select (PLLCR) OSCCLK or VCOCLK CLKIN OSCCLK 0 PLLSTS[PLLOFF] n n ≠ 0 /2 PLLSTS[CLKINDIV] TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F2...
Page 48 - The three possible input-clock configurations are shown in; Figure 3-13. Using the Internal Oscillator; Fundamental mode, parallel resonant
External Clock Signal (Toggling 0 −V DDIO ) XCLKIN X2 NC X1 External Clock Signal (Toggling 0 −V DD ) XCLKIN X2 NC X1 C L1 X2 X1 Crystal C L2 XCLKIN TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DEC...
Page 49 - The PLL-based clock module provides two modes of operation:; Table 3-17. Possible PLL Configuration Modes; SYSCLKOUT
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 3.6.1.2 PLL-Based Clock Module The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessa...
Page 50 - Loss of Input Clock
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 3.6.1.3 Loss of Input Clock In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will st...
Page 51 - Watchdog Block; shows the various functional blocks within the watchdog module.
/512 OSCCLK WDCR (WDPS(2:0)) WDCLK WDCNTR(7:0) WDKEY(7:0) Good Key 1 0 1 WDCR (WDCHK(2:0)) BadWDCHKKey WDCR (WDDIS) Clear Counter SCSR (WDENINT) Watchdog Prescaler Generate Output Pulse (512 OSCCLKs) 8-Bit Watchdog Counter CLR WDRST WDINT Watchdog 55 + AA Key Detector XRS Core-reset WDRST (A) Intern...
Page 52 - Low-Power Modes Block; The low-power modes on the 280x are similar to the 240x devices.; The various low-power modes operate as follows:
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 3.7 Low-Power Modes Block The low-power modes on the 280x are similar to the 240x devices. Table 3-18 summarizes the various mo...
Page 53 - Digital I/O and shared pin functions
Borrow Reset Timer Reload SYSCLKOUT TCR.4 (Timer Start Status) TINT 16-Bit Timer Divide-Down TDDRH:TDDR 32-Bit Timer Period PRDH:PRD 32-Bit Counter TIMH:TIM 16-Bit Prescale Counter PSCH:PSC Borrow TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, ...
Page 54 - NAME
INT1 to INT12 INT14 C28x TINT2 TINT0 PIE CPU-TIMER 0 CPU-TIMER 2 (Reserved for DSP/BIOS) INT13 TINT1 CPU-TIMER 1 XINT13 TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com In the ...
Page 55 - The 280x device contains up to six enhanced PWM Modules (ePWM).; Figure 4-3. Multiple PWM Modules in a 280x System; shows the complete ePWM register set per module.
PIE TZ1 to TZ6 Peripheral Bus ePWM1 module ePWM2 module ePWMx module EPWM1SYNCI EPWM2SYNCI EPWM2SYNCO EPWMxSYNCI EPWMxSYNCO ADC GPIO MUX EPWM1SYNCI EPWM1SYNCO ADCSOCx0 EPWMxA EPWMxB EPWM2A EPWM2B EPWM1A EPWM1B EPWM1INT EPWM1SOC EPWM2INT EPWM2SOC EPWMxINT EPWMxSOC to eCAP1 module (sync in) TZ1 to TZ6...
Page 56 - Table 4-2. ePWM Control and Status Registers
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Table 4-2. ePWM Control and Status Registers SIZE (x16) / NAME ePWM1 ePWM2 ePWM3 ePWM4 ePWM5 ePWM6 DESCRIPTION #SHADOW TBCTL 0x...
Page 59 - Figure 4-5. eCAP Functional Block Diagram
TSCTR (counter−32 bit) RST CAP1 (APRD active) LD CAP2 (ACMP active) LD CAP3 (APRD shadow) LD CAP4 (ACMP shadow) LD Continuous / Oneshot Capture Control LD1 LD2 LD3 LD4 32 32 PRD [0−31] CMP [0−31] CTR [0−31] eCAPx Interrupt Trigger and Flag control to PIE CTR=CMP 32 32 32 32 32 ACMP shadow Event Pre-...
Page 60 - Table 4-3. eCAP Control and Status Registers; SIZE
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Table 4-3. eCAP Control and Status Registers SIZE NAME eCAP1 eCAP2 eCAP3 eCAP4 DESCRIPTION (x16) TSCTR 0x6A00 0x6A20 0x6A40 0x6...
Page 61 - Data bus; Figure 4-6. eQEP Functional Block Diagram
QWDTMR QWDPRD 16 QWDOG UTIME QUPRD QUTMR 32 UTOUT WDTOUT Quadrature capture unit (QCAP) QCPRDLAT QCTMRLAT 16 QFLG QEPSTS QEPCTL Registers used by multiple units QCLK QDIR QI QS PHE PCSOUT Quadrature decoder (QDU) QDECCTL 16 Position counter/ control unit (PCCU) QPOSLAT QPOSSLAT 16 QPOSILAT EQEPxAIN ...
Page 62 - Table 4-4. eQEP Control and Status Registers
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Table 4-4. eQEP Control and Status Registers eQEP1 eQEP1 eQEP2 NAME SIZE(x16)/ REGISTER DESCRIPTION ADDRESS ADDRESS #SHADOW QPO...
Page 63 - The digital value of the input analog voltage is derived by:; ePWM start of conversion
Digital Value + 0, Digital Value + 4096 Input Analog Voltage * ADCLO 3 when input ≤ 0 V when 0 V < input < 3 V when input ≥ 3 V Digital Value + 4095, TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBE...
Page 64 - Figure 4-7. Block Diagram of the ADC Module; shows the ADC pin connections for the 280x; signals is as follows:
Result Registers EPWMSOCB S/W GPIO/XINT2 _ADCSOC EPWMSOCA S/W Sequencer 2 Sequencer 1 SOC SOC ADC Control Registers 70B7h 70B0h 70AFh 70A8h Result Reg 15 Result Reg 8 Result Reg 7 Result Reg 1 Result Reg 0 Module ADC 12-Bit Analog MUX ADCINA0 ADCINA7 ADCINB0 ADCINB7 System Control Block High-Speed P...
Page 65 - shows the ADC pin-biasing for internal reference and; Figure 4-8. ADC Pin Connections With Internal Reference
ADCINA[7:0]ADCINB[7:0] ADCLO ADCREFIN ADC External Current Bias Resistor ADCRESEXT ADCREFP V DD1A18 V DD2A18 V SS1AGND V SS2AGND V DDAIO V SSAIO V DDA2 V SSA2 ADC Reference Positive Output ADCREFM ADC Reference Medium Output ADC Power ADC Analog and Reference I/O Power Analog input 0−3 V with respec...
Page 66 - Figure 4-9. ADC Pin Connections With External Reference; ADC Connections if the ADC Is Not Used
ADCINA[7:0]ADCINB[7:0] ADCLO ADCREFIN ADC External Current Bias Resistor ADCRESEXT ADCREFP V DD1A18 V DD2A18 V SS1AGND V SS2AGND V DDAIO V SSAIO V DDA2 V SSA2 ADC Reference Positive Output ADCREFM ADC Reference Medium Output ADC Analog Power ADC Analog and Reference I/O Power Analog input 0−3 V with...
Page 67 - ADC Registers
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 4.6.2 ADC Registers The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-5 . Table 4...
Page 69 - Figure 4-10. eCAN Block Diagram and Interface Circuit
Mailbox RAM (512 Bytes) 32-Message Mailbox of 4 × 32-Bit Words Memory Management Unit CPU Interface, Receive Control Unit, Timer Management Unit eCAN Memory (512 Bytes) Registers and Message Objects Control 32 32 Message Controller 32 32 32 32 32 32 eCAN Protocol Kernel Receive Buffer Transmit Buffe...
Page 75 - shows the SCI module block diagram.
TX FIFO _0 LSPCLK WUT Frame Format and Mode Even/Odd Enable Parity SCI RX Interrupt select logic BRKDT RXRDY SCIRXST.6 SCICTL1.3 8 SCICTL2.1 RX/BK INT ENA SCIRXD SCIRXST.1 TXENA SCI TX Interrupt select logic TX EMPTY TXRDY SCICTL2.0 TX INT ENA SCITXD RXENA SCIRXD RXWAKE SCICTL1.6 RX ERR INT ENA TXWA...
Page 76 - NOTE: All four pins can be used as GPIO, if the SPI module is not used.; Two operational modes: master and slave; Delayed transmit control
Baud rate = LSPCLK 4 LSPCLK (SPIBRR ) 1) when SPIBRR = 3 to 127 Baud rate = when SPIBRR = 0,1, 2 TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 4.9 Serial Peripheral Interfac...
Page 77 - through
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 The SPI port operation is configured and controlled by the registers listed in Table 4-10 through Table 4-13 . Table 4-10. SP...
Page 79 - is a block diagram of the SPI in slave mode.
S SPICTL.0 SPI INT FLAG SPI INT ENA SPISTS.6 S Clock Polarity Talk LSPCLK 4 5 6 1 2 3 0 0 1 2 3 SPI Bit Rate State Control SPIRXBUF Buffer Register Clock Phase Receiver Overrun Flag SPICTL.4 Overrun INT ENA SPICCR.3 − 0 SPIBRR.6 − 0 SPICCR.6 SPICTL.3 SPIDAT.15 − 0 SPICTL.1 M S M Master/Slave SPISTS....
Page 81 - Figure 4-15. I2C Peripheral Module Interfaces; The registers in
SYSRS Data[16] SYSCLKOUT Data[16] Addr[16] Control I2CINT1A I2CINT2A C28X CPU GPIO MUX I 2 C−A System Control Block I2CAENCLK PIE Block SDAA SCLA Peripheral Bus TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – O...
Page 83 - shows the GPIO
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1to enable 32-bit operatio...
Page 85 - Figure 4-17. Qualification Using Sampling Window
GPyCTRL Reg SYNC SYSCLKOUT Qualification Input Signal Qualified By 3 or 6 Samples GPIOx Time between samples GPxQSEL Number of Samples TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECE...
Page 86 - Device and Development Support Tool Nomenclature
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 5 Device Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs,includin...
Page 88 - Documentation Support; information on types of peripherals.; LITERATURE; The following documents are available on the TI website (; Peripheral Guides
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 5.2 Documentation Support Extensive documentation supports all of the TMS320™ DSP family generations of devices from productann...
Page 89 - describes
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 SPRU790 TMS320x280x, 2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) ModuleReference Guide describes the eQEP module, w...
Page 91 - Software; BSDL Models
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 methods described in this report can improve the absolute accuracy of the ADC to levelsbetter than 0.5%. This application rep...
Page 93 - Absolute Maximum Ratings
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6 Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions for t...
Page 94 - over recommended operating conditions (unless otherwise noted)
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Device...
Page 95 - Current Consumption
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.4 Current Consumption Table 6-1. TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT I D...
Page 99 - Reducing Current Consumption; SPI modules; Table 6-5. Typical Current Consumption by Various; PERIPHERAL; CURRENT; The baseline I; current (current when the core is executing a dummy loop with no; current for a given application,
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.4.1 Reducing Current Consumption 280x devices have a richer peripheral mix compared to the 281x family. While the McBSP has...
Page 100 - Current Consumption Graphs
0.0 50.0 100.0 150.0 200.0 250.0 10 20 30 40 50 60 70 80 90 100 SYSCLKOUT (MHz) Current (mA) IDD IDDA18 IDDIO IDD3VFL 3.3-V current 1.8-V current 0.0 100.0 200.0 300.0 400.0 500.0 600.0 10 20 30 40 50 60 70 80 90 100 SYSCLKOUT (MHz) Device Power (mW) TOTAL POWER TMS320F2809, TMS320F2808, TMS320F2806...
Page 101 - Current Vs SYSCLKOUT; rr; IDD; Device Power Vs SYSCLKOUT; ic; TOTAL POW ER
Current Vs SYSCLKOUT 0 20 40 60 80 100 120 140 160 180 200 10 20 30 40 50 60 70 80 90 10 SYSCLKOUT (MHz) C u rr e n t (m A ) IDD IDDA18 1.8v c urrent IDDIO IDD3VFL 3.3v c urrent Device Power Vs SYSCLKOUT 0.0 100.0 200.0 300.0 400.0 10 20 30 40 50 60 70 80 90 100 SYSCLKOUT (MHz) D e v ic e P o w e r ...
Page 102 - Emulator Connection Without Signal Buffering for the DSP; shows
EMU0 EMU1 TRST TMS TDI TDO TCK VDDIO DSP EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET 13 14 2 1 3 7 11 9 6 inches or less PD GND GND GND GND GND 5 4 6 8 10 12 JTAG Header VDDIO TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTO...
Page 103 - Transmission Line; Tester Pin Electronics; Data Sheet Timing Reference Point; Timing Parameter Symbology; Lowercase subscripts and their; General Notes on Timing Parameters
Transmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (Α) Tester Pin Electronics Data Sheet Timing Reference Point OutputUnderTest 42 Ω 3.5 nH Device Pin (B) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – ...
Page 104 - Device Clock Table; and
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6.6.3 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock opti...
Page 105 - Clock Requirements and Characteristics; Timing Requirements - PLL Enabled; The possible configuration modes are shown in
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.7 Clock Requirements and Characteristics Table 6-8. Input Clock Frequency PARAMETER MIN TYP MAX UNIT Resonator (X1/X2) 20 3...
Page 106 - Power Sequencing; Power Management and Supervisory Circuit Solutions; Table 6-12. Power Management and Supervisory Circuit Solutions; SUPPLIER
C4 C3 XCLKOUT (B) XCLKIN (A) C5 C9 C10 C1 C8 C6 TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. T...
Page 109 - Figure 6-10. Example of Effect of Writing Into PLLCR Register; PARAMETER
OSCCLK SYSCLKOUT Write to PLLCR OSCCLK * 2 (Current CPU Frequency) OSCCLK/2 (CPU Frequency While PLL is Stabilizing With the Desired Frequency. This Period (PLL Lock-up Time, t p ) is 131 072 OSCCLK Cycles Long.) OSCCLK * 4 (Changed CPU Frequency) GPIO t r(GPO) t f(GPO) TMS320F2809, TMS320F2808, TMS...
Page 111 - Sampling Window Width for Input Signals; Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD
GPIOxn XCLKOUT t w(GPI) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.9.3 Sampling Window Width for Input Signals The following section summarizes the sampling window wi...
Page 112 - Low-Power Mode Wakeup Timing; shows the timing requirements,; Table 6-16. IDLE Mode Timing Requirements
WAKE INT (A) XCLKOUT Address/Data (internal) t d(WAKE−IDLE) t w(WAKE−INT) TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6.9.4 Low-Power Mode Wakeup Timing Table 6-16 shows t...
Page 114 - Table 6-20. HALT Mode Timing Requirements; Table 6-21. HALT Mode Switching Characteristics
t d(IDLE−XCOL) X1/X2 or XCLKIN XCLKOUT HALT HALT Wake-up Latency Flushing Pipeline t d(WAKE−HALT) (A) (B) (C) (D) Device Status (E) (G) (F) PLL Lock-up Time Normal Execution t w(WAKE-GPIO) t p GPIOn Oscillator Start-up Time TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TM...
Page 115 - Enhanced Control Peripherals; shows the PWM timing requirements and; Table 6-23. ePWM Switching Characteristics
PWM (B) TZ XCLKOUT (A) t w(TZ) t d(TZ-PWM)HZ TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 6.10 Enhanced Control Peripherals 6.10.1 Enhanced Pulse Width Modulator (ePWM) T...
Page 116 - Table 6-27. eCAP Switching Characteristics; shows the eQEP timing requirement and; Table 6-29. eQEP Switching Characteristics
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com Table 6-25 shows the high-resolution PWM switching characteristics. Table 6-25. High-Resolution PWM Characteristics at SYSCLKOU...
Page 117 - Table 6-31. External Interrupt Timing Requirements
ADCSOCAO or ADCSOCBO t w(ADCSOCAL) XNMI, XINT1, XINT2 t w(INT) Interrupt Vector t d(INT) Address bus (internal) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 Table 6-30. E...
Page 118 - I2C Electrical Specification and Timing; TEST CONDITIONS; lists the timing (clock
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6.10.4 I2C Electrical Specification and Timing Table 6-33. I2C Timing TEST CONDITIONS MIN MAX UNIT f SCL SCL clock frequency I2...
Page 123 - MIN
20 15 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be Valid SPISOMI Data Is Valid 19 16 14 13 12 SPISTE (A) TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2...
Page 127 - Figure 6-25. ADC Analog Input Impedance Model
ac R s ADCIN0 C p 10 pF R on 1 k Ω 1.64 pF C h Switch Typical Values of the Input Circuit Components: Switch Resistance (R on ): 1 k Ω Sampling Capacitor (C h ): 1.64 pF Parasitic Capacitance (C p ): 10 pF Source Resistance (R s ): 50 Ω 28x DSP Source Signal TMS320F2809, TMS320F2808, TMS320F2806 TMS...
Page 128 - Table 6-41. Sequential Sampling Mode Timing; SAMPLE n
Analog Input on Channel Ax or Bx ADC Clock Sample and Hold SH Pulse SMODE Bit t dschx_n t dschx_n+1 Sample n Sample n+1 Sample n+2 t SH ADC Event Trigger from ePWM or Other Sources t d(SH) TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F280...
Page 129 - Figure 6-27. Simultaneous Sampling Mode Timing
Analog Input on Channel Ax Analog Input on Channel Bx ADC Clock Sample and Hold SH Pulse t SH t dschA0_n t dschB0_n t dschB0_n+1 Sample n Sample n+1 Sample n+2 t dschA0_n+1 t d(SH) ADC Event Trigger from ePWM or Other Sources SMODE Bit TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, ...
Page 130 - Detailed Descriptions; Integral Nonlinearity
N + (SINAD * 1.76) 6.02 TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 6.11 Detailed Descriptions Integral Nonlinearity Integral nonlinearity refers to the deviation of each ...
Page 131 - Table 6-43. Flash Endurance for A and S Temperature Material; Equation to compute the OTP wait-state in
+ ƪ ǒ t a(fp) t c(SCO) Ǔ * 1 ƫ (round up to the next highest integer) or 0, whichever is larger (round up to the next highest integer) or 1, whichever is larger + ƪ ǒ t a(fr) t c(SCO) Ǔ * 1 ƫ Flash Page Wait-State Flash Random Wait-State (round up to the next highest integer) or 1, whichever is larg...
Page 132 - Equations to compute the page wait-state and random wait-state in; Wait-States at Different Frequencies
+ ƪ ǒ t a(rp) t c(SCO) Ǔ * 1 ƫ (round up to the next highest integer) or 0, whichever is larger + ƪ ǒ t a(rr) t c(SCO) Ǔ * 1 ƫ (round up to the next highest integer) or 1, whichever is larger ROM Page Wait-State ROM Random Wait-State TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS...
Page 133 - The V; The PART-ID register value is different for Flash and ROM parts.
TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www.ti.com SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 7 Migrating From F280x Devices to C280x Devices 7.1 Migration Issues The migration issues to be considered while migrating fr...
Page 134 - Changed MIN N; LOCATION
TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L – OCTOBER 2003 – REVISED DECEMBER 2009 www.ti.com 8 Revision History This data sheet revision history highlights the technical changes made to the SPRS230K device-specificdata s...
Page 137 - PACKAGE OPTION ADDENDUM; PACKAGING INFORMATION
PACKAGE OPTION ADDENDUM www.ti.com 5-Nov-2010 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TMS320C2801GGMA ACTIVE BGA MICROSTAR GGM 100 TBD Call TI Call TI TMS...
Page 141 - MECHANICAL DATA; PLASTIC BALL GRID ARRAY; Seating Plane
MECHANICAL DATA MPBG028B FEBRUARY 1997 – REVISED MAY 2002 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GGM (S–PBGA–N100) PLASTIC BALL GRID ARRAY 0,08 0,10 1,40 MAX 0,85 0,55 0,45 0,450,35 0,95 4 C B A D E 2 1 3 K F G H J 5 7 6 9 8 10 Seating Plane SQ 9,90 10,10 7,20 TYP 0,40 0,40 A1 Corner Bottom ...
Page 143 - PLASTIC QUAD FLATPACK; Gage Plane
MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 4040149 /B 11/96 50 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 51 25 75 1 12,00 TYP 0,17 76 100 SQ SQ 15,80 16,20 13,80 1,35 1,45 1,60 MAX 14...
Page 144 - IMPORTANT NOTICE; Products
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...
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