Texas Instruments TMS320DM644x - Manuals

www.ti.com Related Documentation From Texas Instruments SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down ...

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features 1.3 Functional Block Diagram User's Guide SPRUE30B – September 2006 Multimedia Card (MMC)/Secure Digital (SD) Card Controller This document describes the multimedia card (MMC)/secure digital (SD) card controller in theTMS320DM644x Digital Med...

www.ti.com Status and registers DMA requests Interrupts ARM CPU FIFO MMC/SD interface CLK divider MMC/SDcardinterface 1.4 Supported Use Case Statement 1.5 Industry Standard(s) Compliance Statement 2 Peripheral Architecture Peripheral Architecture Figure 1. MMC/SD Card Controller Block Diagram The MM...

www.ti.com Native packets Nativesignals CMD CLK DAT0 or DAT0−3 MMC/SD controller ARM EDMA Memory MMCs or SD cards SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 MMC/SD controller MMC and SD (1−bit mode) CLK CMD DAT0 MMC/SD configuration MMC/SD controller SD_DATA0 SD_CMD SD_CLK DAT0 CMD SD card (4...

www.ti.com 2.1 Clock Control MMCCLK (CLKRT) Function clock for MMC/SD controller MMC/SD controller MMC/SD input clock card MMC/SD Memory clock on CLK pin Peripheral Architecture There are two clocks, the function clock and the memory clock, in the MMC/SD controller ( Figure 4 ). The function clock d...

www.ti.com 2.2 Signal Descriptions 2.3 Protocol Descriptions 2.3.1 MMC/SD Mode Write Sequence Peripheral Architecture Table 1 shows the MMC/SD controller pins that each mode uses. The MMC/SD protocol uses the clock, command (two-way communication between the MMC controller and memory card), and data...

www.ti.com 2 CRC bytes Busy low Start bit End bit Start bit End bit CMD Data CLK 2.3.2 MMC/SD Mode Read Sequence Peripheral Architecture Figure 5. MMC/SD Mode Write Sequence Timing Diagram Table 2. MMC/SD Mode Write Sequence Portion of theSequence Description WR CMD Write command: A 6-byte WRITE_BLO...

www.ti.com Start bit End bit CMD Data CLK 1 transfer source bit 2 CRC bytes 2.4 Data Flow in the Input/Output FIFO Peripheral Architecture Figure 6. MMC/SD Mode Read Sequence Timing Diagram Table 3. MMC/SD Mode Read Sequence Portion of theSequence Description RD CMD Read command: A 6-byte READ_SINGL...

www.ti.com ARM/EDMA reads/writes Write Read FIFO 8−bit x 32 (256−bit) FIFO EDMA event128 or 256 bit 128 or 256 bit EDMA event EDMA eventthe end of atransfer Pointer increment or decrease Pointer increment or decrease FIFO 16−bit DXR 16−bit DRR 16−bit DXR shifter 16−bit DRR shifter DXR DRR EDMA reque...

www.ti.com 2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) 1st 2nd 3rd 4th 3 4th 3rd 2nd 1st Support byten = ”1111” Support byten = ”0111” 3rd 2nd 1st 3 3rd 2nd 1st Support byten = ”0011” 1st 2nd 3 2nd 1st 0 Support byten = ”0001” 1st 3 1st 0 0 0 FIFO MMCDRR or MMCDXR registers Peripheral Ar...

www.ti.com 2.6 FIFO Operation During Card Read Operation 2.6.1 EDMA Reads 2.6.2 CPU Reads Peripheral Architecture The FIFO controller manages the activities of reading the data in from the card and issuing EDMA readevents. Each time an EDMA read event is issued, an EDMA read request interrupt genera...

www.ti.com FIFO Check1/Start FIFO full ? Counter =FIFOLEV ? Yes No Capture data, no DMA pending Increment counter No Yes Generate DMA Reset counter FIFO check 2 Yes No ? full FIFO No =FIFOLEV ? Counter Increment counter DMA Capture data, done ? DMA No Yes Yes Yes Generate DMA Reset counter Idle, DMA...

www.ti.com 2.7 FIFO Operation During Card Write Operation 2.7.1 EDMA Writes 2.7.2 CPU Writes Peripheral Architecture The FIFO controller manages the activities of accepting data from the CPU or EDMA and passing the datato the MMC/SD controller. The FIFO controller issues EDMA write events as appropr...

www.ti.com FIFO Check1/Start FIFO full ? Counter =FIFOLEV ? Yes No Capture data, no DMA pending Increment counter No Yes Generate DMA Reset counter FIFO check 2 Yes No ? full FIFO No =FIFOLEV ? Counter Increment counter DMA Capture data, done ? DMA No Yes Yes Yes Generate DMA Reset counter Idle, DMA...

www.ti.com 2.8 Reset Considerations 2.8.1 Software Reset Considerations 2.8.2 Hardware Reset Considerations 2.9 Initialization 2.9.1 MMC/SD Controller Initialization 2.9.2 Initializing the MMC Control Register (MMCCTL) Peripheral Architecture The MMC/SD peripheral has two reset sources: hardware res...

www.ti.com 2.9.7 Monitoring Activity in the MMC/SD Mode 2.9.7.1 Determining Whether New Data is Available in MMCDRR 2.9.7.2 Verifying that MMCDXR is Ready to Accept New Data 2.9.7.3 Checking for CRC Errors 2.9.7.4 Checking for Time-Out Events 2.9.7.5 Determining When a Response/Command is Done 2.9.7...

www.ti.com 2.10 Interrupt Support 2.10.1 Interrupt Events and Requests 2.10.2 Interrupt Multiplexing Peripheral Architecture The MMC/SD controller generates the interrupt requests described in Table 4 . When an interrupt event occurs, its flag bit is set in the MMC status register 0 (MMCST0). If the...

www.ti.com 3 Procedures for Common Operations 3.1 Card Identification Operation 3.1.1 MMC Card Identification Procedure Procedures for Common Operations Before the MMC/SD controller starts data transfers to or from memory cards in the MMC/SD native mode,it must first identify how many cards are pres...

www.ti.com 3.1.2 SD Card Identification Procedure Procedures for Common Operations Figure 12. MMC Card Identification Procedure The SD card identification procedure is: 1. Use the MMC command register (MMCCMD) to issue the GO_IDLE_STATE (CMD0) command to the MMC cards. Using MMCMD to issue the CMD0 ...

www.ti.com Procedures for Common Operations 6. Repeat step 4 and step 5 to identify and retrieve relative addresses from all remaining SD cards until no card responds to the CMD2 command. No card responding within 5 memory clock cycles indicatesthat all cards have been identified and the MMC card an...

www.ti.com 3.2 MMC/SD Mode Single-Block Write Operation Using CPU Procedures for Common Operations To perform a single-block write, the block length must be 512 bytes and the same length needs to be setin both the MMC/SD controller and the memory card. The procedure for this operation is: 1. Write t...

www.ti.com 3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA 3.4 MMC/SD Mode Single-Block Read Operation Using the CPU Procedures for Common Operations To perform a single-block write, the block length must be 512 bytes and the same length must be set inboth the MMC/SD controller and the c...

www.ti.com ARG HIGH RCA ADDRESS HIGH STATUS 0 NEXT DATA BYTE DATA TX MMC controller register content MMC controller register RCA ADDRESS LOW ARG LOW SEL/DESEL. CARD COMMAND Select one card with relativecard address (RCA) whilede−selecting the other cards. SET_BLOCKLEN BLK ADDRESS LOW BLK ADDRESS HIG...

www.ti.com 3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU Procedures for Common Operations To perform a multiple-block write, the same block length needs to be set in both the MMC/SD controllerand the card. Note: The procedure in this section uses a STOP_TRANSMISSION command to end the blo...

www.ti.com ARG HIGH RCA ADDRESS HIGH STATUS 0 NEXT DATA BYTE DATA TX MMC controller register content MMC controller register RCA ADDRESS LOW ARG LOW SEL/DESEL. CARD COMMAND Select one card with relativecard address (RCA) whilede−selecting the other cards. SET_BLOCKLEN BLK ADDRESS LOW BLK ADDRESS HIG...

www.ti.com 4 Registers Registers Table 5 lists the memory-mapped registers for the multimedia card/secure digital (MMC/SD) card controller. See the device-specific data manual for the memory address of these registers. Table 5. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers Offset...

www.ti.com 4.1 MMC Control Register (MMCCTL) Registers The MMC control register (MMCCTL) is used to enable or configure various modes of the MMC controller.Set or clear the DATRST and CMDRST bits at the same time to reset or enable the MMC controller. The MMC control register (MMCCTL) is shown in Fi...

www.ti.com 4.2 MMC Memory Clock Control Register (MMCCLK) Registers The MMC memory clock control register (MMCCLK) is used to: • Select whether the CLK pin is enabled or disabled (CLKEN bit). • Select how much the function clock is divided-down to produce the memory clock (CLKRT bits). Whenthe CLK p...

www.ti.com 4.3 MMC Status Register 0 (MMCST0) Registers The MMC status register 0 (MMCST0) records specific events or errors. The transition from 0 to 1 on eachbit in MMCST0 can cause an interrupt signal to be sent to the CPU. If an interrupt is desired, set thecorresponding interrupt enable bit in ...

www.ti.com 4.4 MMC Status Register 1 (MMCST1) Registers The MMC status register 1 (MMCST1) records specific events or errors. There are no interruptsassociated with these events or errors. The MMC status register 1 (MMCST1) is shown in Figure 21 and described in Table 9 . Figure 21. MMC Status Regis...

www.ti.com 4.5 MMC Interrupt Mask Register (MMCIM) Registers The MMC interrupt mask register (MMCIM) is used to enable (bit = 1) or disable (bit = 0) status interrupts.If an interrupt is enabled, the transition from 0 to 1 of the corresponding interrupt bit in the MMC statusregister 0 (MMCST0) can c...

www.ti.com 4.6 MMC Response Time-Out Register (MMCTOR) Registers Table 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions (continued) Bit Field Value Description 3 ETOUTRD Read-data time-out event (TOUTRD) interrupt enable. 0 Read-data time-out event interrupt is disabled. 1 Read-data time-o...

www.ti.com 4.8 MMC Block Length Register (MMCBLEN) Registers The MMC block length register (MMCBLEN) specifies the data block length in bytes. This value mustmatch the block length setting in the memory card. The MMC block length register (MMCBLEN) is shown in Figure 25 and described in Table 13 . F...

www.ti.com 4.9 MMC Number of Blocks Register (MMCNBLK) 4.10 MMC Number of Blocks Counter Register (MMCNBLC) Registers The MMC number of blocks register (MMCNBLK) specifies the number of blocks for a multiple-blocktransfer. The MMC number of blocks register (MMCNBLK) is shown in Figure 26 and describ...

www.ti.com 4.11 MMC Data Receive Register (MMCDRR) 4.12 MMC Data Transmit Register (MMCDXR) Registers The MMC data receive register (MMCDRR) is used for storing the received data from the MMC controller.The CPU or the DMA controller can read data from this register. MMCDRR expects the data inlittle-...

www.ti.com 4.13 MMC Command Register (MMCCMD) Registers Note: Writing to the MMC command register (MMCCMD) causes the MMC controller to send theprogrammed command. Therefore, the MMC argument register (MMCARGHL) must beloaded properly before a write to MMCCMD. The MMC command register (MMCCMD) speci...

www.ti.com Registers Table 18. MMC Command Register (MMCCMD) Field Descriptions (continued) Bit Field Value Description 12 STRMTP Stream enable. 0 If WDATX = 1, the data transfer is a block transfer. The data transfer stops after the movement of theprogrammed number of bytes (defined by the programm...

www.ti.com 4.14 MMC Argument Register (MMCARGHL) Registers Note: Do not modify the MMC argument register (MMCARGHL) while it is being used for anoperation. The MMC argument register (MMCARGHL) specifies the arguments to be sent with the commandspecified in the MMC command register (MMCCMD). Writing ...

www.ti.com 4.15 MMC Response Registers (MMCRSP0-MMCRSP7) Registers Each command has a preset response type. When the MMC controller receives a response, it is stored insome or all of the eight MMC response registers (MMCRSP7-MMCRSP0). The response registers areupdated as the responses arrive, even i...

www.ti.com 4.16 MMC Data Response Register (MMCDRSP) 4.17 MMC Command Index Register (MMCCIDX) Registers After the MMC controller sends a data block to a memory card, the return byte from the memory card isstored in the MMC data response register (MMCDRSP). The MMC data response register (MMCDRSP) i...

www.ti.com 4.18 MMC FIFO Control Register (MMCFIFOCTL) Registers The MMC FIFO control register (MMCFIFOCTL) is shown in Figure 39 and described in Table 25 . Figure 39. MMC FIFO Control Register (MMCFIFOCTL) 31 16 Reserved R-0 15 5 4 3 2 1 0 Reserved ACCWD FIFOLEV FIFODIR FIFORST R-0 R/W-0 R/W-0 R/W...

www.ti.com Appendix A Revision History Appendix A Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Additions/Modifications/Deletions Section 1.2 Changed third bullet. Added seventh bullet. Section 1.3 Added second sentence. ...