Texas Instruments TMS320DM643x - Manuals

Page 3 - Preface

Contents Preface ............................................................................................................................... 9 1 Introduction ............................................................................................................. 11 1.1 Introduction ...........

Page 9 - About This Manual; — TMS320DM643x DMP Peripherals Overview Reference Guide.

Preface SPRU978E – March 2008 Read This First About This Manual This document describes the DSP subsystem in the TMS320DM643x Digital Media Processor (DMP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the follow...

Page 11 - Chapter 1; Topic; Introduction

Chapter 1 SPRU978E – March 2008 Introduction Topic .................................................................................................. Page 1.1 Introduction .............................................................................. 12 1.2 Block Diagram ...............................

Page 12 - A set of I/O peripherals

www.ti.com 1.1 Introduction 1.2 Block Diagram JTAG Interface System Control PLLs/Clock Generator Input Clock(s) Power/Sleep Controller Pin Multiplexing DSP Subsystem C64x+ t DSP CPU 32 KB L1 Pgm 128 KB L2 RAM 80 KB L1 Data BT.656, Y/C,Raw (Bayer) Video Processing Subsystem (VPSS) CCD Controller Vide...

Page 15 - Chapter 2

Chapter 2 SPRU978E – March 2008 TMS320C64x+ Megamodule Topic .................................................................................................. Page 2.1 Introduction .............................................................................. 16 2.2 TMS320C64x+ CPU ...................

Page 16 - and Instruction Set Reference Guide

www.ti.com 2.1 Introduction 2.2 TMS320C64x+ CPU Introduction The C64x+ Megamodule ( Figure 2-1 ) consists of the following components: • TMS320C64x+ CPU • Internal memory controllers: – Level-1 program memory controller (L1P controller) – Level-1 data memory controller (L1D controller) – Level-2 uni...

Page 17 - IDMA; Hardware support for modulo loop operation to reduce code size

www.ti.com Cache control Memory protect Bandwidth mgmt L1P RAM/ cache 256 Bandwidth mgmt Memory protect Cache control 256 L2 256 RAM/ Cache ROM 256 Instruction fetch file A file B C64x+ CPU 256 Cache control Memory protect Bandwidth mgmt L1D 128 128 8 x 32 IDMA 256 256 128 256 Power down Interrupt c...

Page 18 - Memory Controllers; TMS320C64x+ DSP Cache User’s Guide; TMS320C64x+ DSP Cache User’s Guide

www.ti.com 2.3 Memory Controllers 2.3.1 L1P Controller Memory Controllers The C64x+ Megamodule implements a two-level internal cache-based memory architecture with externalmemory support. Level 1 memory is split into separate program memory (L1P memory) and data memory(L1D memory). Figure 2-2 shows ...

Page 21 - Refer to the; and to the; Refer to the internal DMA (IDMA) controller section in the

www.ti.com 2.3.4 External Memory Controller (EMC) 2.3.5 Internal DMA (IDMA) Memory Controllers The external memory controller (EMC) is the hardware interface between the external memory map(external memory and external registers) and the other controllers in the C64x+ Megamodule (forexample, L1P con...

Page 22 - Internal Peripherals; TMS320C64x+ DSP Megamodule Reference Guide; The DM643x DMP does not support dynamic power-down.

www.ti.com 2.4 Internal Peripherals 2.4.1 Interrupt Controller (INTC) 2.4.2 Power-Down Controller (PDC) Internal Peripherals This C64x+ Megamodule includes the following internal peripherals: • Interrupt controller (INTC) • Power-down controller (PDC) This section briefly describes the INTC and PDC....

Page 25 - Chapter 3; Memory Map

Chapter 3 SPRU978E – March 2008 System Memory Topic .................................................................................................. Page 3.1 Memory Map ............................................................................. 26 3.2 Memory Interfaces Overview ....................

Page 26 - Megamodule Reference Guide

www.ti.com 3.1 Memory Map 3.1.1 DSP Internal Memory (L1P, L1D, L2) 3.1.2 External Memory 3.1.3 Internal Peripherals 3.1.4 Device Peripherals Memory Map Refer to your device-specific data manual for memory-map information. This section describes the configuration of the DSP internal memory in the DM6...

Page 27 - Asynchronous EMIF Interface; Memory Interfaces Overview

www.ti.com 3.2 Memory Interfaces Overview 3.2.1 DDR2 External Memory Interface 3.2.2 External Memory Interface 3.2.2.1 Asynchronous EMIF Interface 3.2.2.2 NAND Interface Memory Interfaces Overview This section describes the different memory interfaces of DM643x DMP. The DM643x DMP supportsseveral me...

Page 29 - Chapter 4; Overview

Chapter 4 SPRU978E – March 2008 Device Clocking Topic .................................................................................................. Page 4.1 Overview .................................................................................. 30 4.2 Clock Domains ............................

Page 30 - Subsystem

www.ti.com 4.1 Overview 4.2 Clock Domains 4.2.1 Core Domains Overview The DM643x DMP requires one primary reference clock. The primary reference clock can be either crystalinput or driven by external oscillators. A 27 MHZ crystal at the MXI/CLKIN pin is recommended for thesystem PLLs, which generate...

Page 31 - SYSCLKBP; Clock Domains

www.ti.com DSP Subsystem SYSCLK1 SYSCLK3 SCR EDMA VPFE VPBE DACs DDR2 PHY DDR2 VTP DDR2 Memory controller PLLDIV2 (/10) PLLDIV1 (/2) BPDIV PLL Controller 2 PLL Controller 1 PLLDIV2 (/3) PLLDIV3 (/6) PLLDIV1 (/1) SYSCLK2 UARTs (x2) I2C Timers (x3) PWMs (x3) EMAC EMIFA VLYNQ HPI McASP0 McBSP0 GPIO McB...

Page 32 - Maximum device speed

www.ti.com 4.2.2 Core Frequency Flexibility Clock Domains The core frequency domain clocks are supplied by the PLL controller 1 (PLLC1). These domain clocks areflexible, to a degree, within the limitations specified in the device-specific data manual. All of the followingfrequency ranges and multipl...

Page 33 - clock to the DDR2 PHY interface.

www.ti.com 4.2.3 DDR2/EMIF Clock Clock Domains The DDR2 interface has a dedicated clock driven from PLL2. This is a separate clock system from thePLL1 clocks provided to other components of the system. This dedicated clock allows the reduction of thecore clock rates to save power while maintaining t...

Page 34 - exact I/O clock frequency supported on the device.; Peripheral

www.ti.com 4.2.4 I/O Domains Clock Domains The I/O domains refer to the frequencies of the peripherals that communicate through device pins. Inmany cases, there are frequency requirements for a peripheral pin interface that are set by an outsidestandard and must be met. It is not necessarily possibl...

Page 35 - The external clock domain can get its clock from 4 sources:

www.ti.com 4.2.5 Video Processing Back End 3 2 0 1 0 1 2 PLLDIV2 CLK54 PLL2 DDR_CLKx2 PCLK VPBECLK MXI CLK_VENC CLK_DAC 1 0 venc_sclk_enc CG OSD VENC DACs venc_div2 venc_sclk_osd VPSS VPSS_CLKCTL.MUXSEL CLK54 CLK_VENC CLK_DAC 0 27 MHz Off 27 MHz 1h 54 54 MHz 54 MHz 2h Off VPBECLK VPBECLK 3h Off PCLK...

Page 36 - Clocking Mode

www.ti.com Clock Domains Table 4-6. Possible Clocking Modes VPSS_CLKCTL.MUXSEL Bit Clocking Mode Description 0 MXI mode Both the VENC and the DAC get their clock from PLLC1 SYSCLKBP, whichdefaults to the MXI 27 MHZ crystal input divide by 1. 1h PLL2 mode The PLL2 (divided-down) generates a 54 MHZ cl...

Page 37 - Chapter 5; PLL Module

Chapter 5 SPRU978E – March 2008 PLL Controller Topic .................................................................................................. Page 5.1 PLL Module .............................................................................. 38 5.2 PLL1 Control ................................

Page 39 - PLL1 Control; PLLC1 Output Clock; to initialize the PLL.

www.ti.com PLLDIV1 (/1) PLLDIV3 (/6) PLLDIV2 (/3) SYSCLK1(CLKDIV1 Domain) SYSCLK3(CLKDIV6 Domain) SYSCLK2(CLKDIV3 Domain) 1 0 PLLM PLL 0 1 BPDIV CLKMODE CLKIN OSCIN PLLEN SYSCLKBP(VPSS-VPBRClock Source) OBSCLK(CLKOUT0 Pin) PLLOUT AUXCLK(CLKIN Domain) OSCDIV1 5.2.1 Device Clock Generation 5.2.2 Steps...

Page 40 - Initialization to PLL Mode from PLL Power Down; and SYSCLK3 divide values:

www.ti.com 5.2.2.1 Initialization to PLL Mode from PLL Power Down PLL1 Control If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must follow the procedure belowto change PLL1 frequencies. The recommendation is to stop all peripheral operation before changing thePLL1 frequency, wit...

Page 41 - Changing PLL Multiplier

www.ti.com 5.2.2.2 Changing PLL Multiplier PLL1 Control If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization timeis previously met (step 7 in Section 5.2.2.1 ), follow this procedure to change PLL1 multiplier. The recommendation is to stop all peripheral ...

Page 42 - Changing SYSCLK Dividers; Example 5-1. Calculating Number of Clock Cycles N

www.ti.com 5.2.2.3 Changing SYSCLK Dividers PLL1 Control This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK dividerchange sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit inPLLCMD) to initiate the divider change. The recom...

Page 43 - PLL2 Control; shows the customization of PLL2 in the; Output Clock

www.ti.com 5.3 PLL2 Control PLLDIV2 (/10) PLLDIV1 (/2) 1 0 PLLM PLL 0 1 BPDIV CLKMODE CLKIN OSCIN PLLEN PLL2_SYSCLK2(VPSS−VPBE) PLL2_SYSCLK1(DDR2 PHY) PLL2_SYSCLKBP(DDR2 VTP) PLLOUT 5.3.1 Device Clock Generation PLL2 Control PLL2 provides the clock from which the DDR2 memory controller and optional ...

Page 44 - DDR2 Considerations When Modifying PLL2 Frequency; TMS320DM643x DMP DDR2 Memory Controller User's Guide

www.ti.com 5.3.2 Steps for Changing PLL2 Frequency 5.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency 5.3.2.1.1 PLL2 Frequency Change Steps When DDR2 Memory Controller is In Reset 5.3.2.1.2 PLL2 Frequency Change Steps When DDR2 Memory Controller is Out of Reset PLL2 Control The PLLC2 is progr...

Page 45 - SYSCLK1 and SYSCLK2 are paused momentarily.

www.ti.com 5.3.2.2 Initialization to PLL Mode from PLL Power Down PLL2 Control If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must follow the procedure belowto change PLL2 frequencies. 1. Select the clock mode by programming the CLKMODE bit in PLLCTL.2. Before changing the PLL ...

Page 47 - Example 5-2. Calculating Number of Clock Cycles N

www.ti.com 5.3.2.4 Changing SYSCLK Dividers PLL2 Control This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK dividerchange sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit inPLLCMD) to initiate the divider change. 1. Check ...

Page 48 - PLL Controller Registers; lists the base address and end address for the PLL controllers.; Table 5-4. PLL and Reset Controller Registers

www.ti.com 5.4 PLL Controller Registers PLL Controller Registers Table 5-3 lists the base address and end address for the PLL controllers. Table 5-4 lists the memory-mapped registers for the PLL and reset controller. See the device-specific data manual for thememory address of these registers. Table...

Page 49 - The peripheral ID register (PID) is shown in

www.ti.com 5.4.1 Peripheral ID Register (PID) 5.4.2 Reset Type Status Register (RSTYPE) PLL Controller Registers The peripheral ID register (PID) is shown in Figure 5-3 and described in Table 5-5 . Figure 5-3. Peripheral ID Register (PID) 31 24 23 16 Reserved TYPE R-0 R-1h 15 8 7 0 CLASS REV R-8h R-...

Page 50 - The PLL control register (PLLCTL) is shown in; Bit

www.ti.com 5.4.3 PLL Control Register (PLLCTL) PLL Controller Registers The PLL control register (PLLCTL) is shown in Figure 5-5 and described in Table 5-7 . Figure 5-5. PLL Control Register (PLLCTL) 31 16 Reserved R-0 15 9 8 7 6 5 4 3 2 1 0 Reserved CLKMODE Reserved PLLENSRC PLLDIS PLLRST Rsvd PLLP...

Page 51 - The PLL multiplier control register (PLLM) is shown in

www.ti.com 5.4.4 PLL Multiplier Control Register (PLLM) 5.4.5 PLL Controller Divider 1 Register (PLLDIV1) PLL Controller Registers The PLL multiplier control register (PLLM) is shown in Figure 5-6 and described in Table 5-8 . Figure 5-6. PLL Multiplier Control Register (PLLM) 31 16 Reserved R-0 15 5...

Page 52 - The PLL controller divider 2 register (PLLDIV2) is shown in

www.ti.com 5.4.6 PLL Controller Divider 2 Register (PLLDIV2) 5.4.7 PLL Controller Divider 3 Register (PLLDIV3) PLL Controller Registers The PLL controller divider 2 register (PLLDIV2) is shown in Figure 5-8 and described in Table 5-10 . Divider 2 controls divider for SYSCLK2. Figure 5-8. PLL Control...

Page 53 - The oscillator divider 1 register (OSCDIV1) is shown in

www.ti.com 5.4.8 Oscillator Divider 1 Register (OSCDIV1) PLL Controller Registers The oscillator divider 1 register (OSCDIV1) is shown in Figure 5-10 and described in Table 5-12 . The oscillator divider 1 controls divider for OBSCLK, dividing down from the MXI/CLKIN clock. For PLLC1, theOBSCLK is co...

Page 54 - The bypass divider register (BPDIV) is shown in

www.ti.com 5.4.9 Bypass Divider Register (BPDIV) PLL Controller Registers The bypass divider register (BPDIV) is shown in Figure 5-11 and described in Table 5-13 . Bypass divider controls divider for SYSCLKBP, dividing down from the MXI/CLKIN clock. Figure 5-11. Bypass Divider Register (BPDIV) 31 16...

Page 55 - The PLL controller command register (PLLCMD) is shown in

www.ti.com 5.4.10 PLL Controller Command Register (PLLCMD) 5.4.11 PLL Controller Status Register (PLLSTAT) PLL Controller Registers The PLL controller command register (PLLCMD) is shown in Figure 5-12 and described in Table 5-14 . PLLCMD contains the command bit for the GO operation. Writes of 1 ini...

Page 56 - and described in

www.ti.com 5.4.12 PLL Controller Clock Align Control Register (ALNCTL) PLL Controller Registers The PLL controller clock align control register (ALNCTL) is shown in Figure 5-14 and described in Table 5-16 . ALNCTL indicates which SYSCLKs need to be aligned for proper device operation. You should not...

Page 57 - The PLLDIV ratio change status register (DCHANGE) is shown in

www.ti.com 5.4.13 PLLDIV Ratio Change Status Register (DCHANGE) PLL Controller Registers The PLLDIV ratio change status register (DCHANGE) is shown in Figure 5-15 and described in Table 5-17 . DCHANGE indicates if the SYSCLK divide ratio has been modified. Figure 5-15. PLLDIV Ratio Change Status Reg...

Page 58 - The clock enable control register (CKEN) is shown in

www.ti.com 5.4.14 Clock Enable Control Register (CKEN) PLL Controller Registers The clock enable control register (CKEN) is shown in Figure 5-16 and described in Table 5-18 . CKEN provides clock enable control for miscellaneous output clocks. CKEN is only applicable to PLLC1, notPLLC2. Figure 5-16. ...

Page 59 - The clock status register (CKSTAT) is shown in

www.ti.com 5.4.15 Clock Status Register (CKSTAT) PLL Controller Registers The clock status register (CKSTAT) is shown in Figure 5-17 and described in Table 5-19 . CKSTAT shows clock status for all clocks, except SYSCLK n . Figure 5-17. Clock Status Register (CKSTAT) 31 16 Reserved R-0 15 4 3 2 1 0 R...

Page 60 - The SYSCLK status register (SYSTAT) is shown in

www.ti.com 5.4.16 SYSCLK Status Register (SYSTAT) PLL Controller Registers The SYSCLK status register (SYSTAT) is shown in Figure 5-18 and described in Table 5-20 . Indicates SYSCLK on/off status. Actual default is determined by actual clock on/off status, which depends on theD[n]EN bit in PLLDIV[n]...

Page 61 - Chapter 6

Chapter 6 SPRU978E – March 2008 Power and Sleep Controller Topic .................................................................................................. Page 6.1 Introduction .............................................................................. 62 6.2 Power Domain and Module Topo...

Page 62 - The PSC includes the following features:

www.ti.com 6.1 Introduction dsp local reset dsp module reset dsp clock DSP dsp power peripheral power peripheral module reset MODx peripheral clock Always on domain PSC clks PLLC RESET VDD POR Emulation Introduction The Power and Sleep Controller (PSC) is responsible for managing transitions of syst...

Page 63 - Power Domain and Module Topology; pins of the; Table 6-1. DM643x DMP Default Module Configuration; Module Name

www.ti.com 6.2 Power Domain and Module Topology Power Domain and Module Topology The DM643x DMP includes one power domain--the AlwaysOn power domain. The AlwaysOn powerdomain is always on when the chip is on. The AlwaysOn domain is powered by the V DD pins of the DM643x DMP (see the device-specific ...

Page 64 - Power Domain and Module States; Max Reset. These states are defined in the following sections.; Module State; for more information on module reset.

www.ti.com 6.3 Power Domain and Module States 6.3.1 Power Domain States 6.3.2 Module States Power Domain and Module States Note: The effects of DSP local reset and DSP module reset have not been fully validated;therefore, these resets are not supported and should not be used. Instead, the POR orRESE...

Page 65 - Executing State Transitions

www.ti.com 6.3.3 Local Reset 6.4 Executing State Transitions 6.4.1 Power Domain State Transitions 6.4.2 Module State Transitions Executing State Transitions In addition to module reset (described in Section 6.3.2 ), the DSP CPU can be reset using a special local reset. When DSP local reset is assert...

Page 66 - IcePick Emulation Support in the PSC; that apply to the C64x+ CPU on the DM643x DMP.

www.ti.com 6.5 IcePick Emulation Support in the PSC 6.6 PSC Interrupts 6.6.1 Interrupt Events IcePick Emulation Support in the PSC The PSC supports IcePick commands that allow IcePick aware emulation tools to have some control overthe state of power domains and modules. On the DM643x DMP, this IcePi...

Page 67 - PSC Interrupts; can only occur in the scenario where an external host programs; for more information on the; See

www.ti.com 6.6.1.1 Module State Emulation Events 6.6.1.2 Local Reset Emulation Events 6.6.2 Interrupt Registers PSC Interrupts The DM643x DMP is a single-processor device. The C64x+ CPU must not program its own module state.The C64x+ CPU module state can only be programmed by an external host (for e...

Page 68 - PSC Registers; Offset

www.ti.com 6.6.3 Interrupt Handling 6.7 PSC Registers PSC Registers Handle the PSC interrupts as described in the following procedure: First, enable the interrupt. 1. Set the EMUIHBIE bit and the EMURSTIE bit in MDCTL39 to enable the interrupt events that you want. Note: The PSC interrupt PSCINT is ...

Page 70 - The module error pending register 1 (MERRPR1) is shown in

www.ti.com 6.7.3 Module Error Pending Register 1 (MERRPR1) 6.7.4 Module Error Clear Register 1 (MERRCR1) PSC Registers The module error pending register 1 (MERRPR1) is shown in Figure 6-4 and described in Table 6-8 . Only the C64x+ CPU (module 39) can have an error condition, as it is the only modul...

Page 71 - The power domain transition command register (PTCMD) is shown in

www.ti.com 6.7.5 Power Domain Transition Command Register (PTCMD) 6.7.6 Power Domain Transition Status Register (PTSTAT) PSC Registers The power domain transition command register (PTCMD) is shown in Figure 6-6 and described in Table 6-10 . Figure 6-6. Power Domain Transition Command Register (PTCMD...

Page 72 - The power domain status n register (PDSTAT0) is shown in

www.ti.com 6.7.7 Power Domain Status 0 Register (PDSTAT0) PSC Registers The power domain status n register (PDSTAT0) is shown in Figure 6-8 and described in Table 6-12 . PDSTAT0 applies to the AlwaysOn power domain. Figure 6-8. Power Domain Status 0 Register (PDSTAT0) 31 16 Reserved R-0 15 10 9 8 7 ...

Page 73 - The power domain control n register (PDCTL0) is shown in

www.ti.com 6.7.8 Power Domain Control 0 Register (PDCTL0) PSC Registers The power domain control n register (PDCTL0) is shown in Figure 6-9 and described in Table 6-13 . PDCTL0 applies to the AlwaysOn power domain. Figure 6-9. Power Domain Control 0 Register (PDCTL0) 31 16 Reserved R-0 15 1 0 Reserv...

Page 74 - The module status

www.ti.com 6.7.9 Module Status n Register (MDSTATn) PSC Registers The module status n register (MDSTAT0-MDSTAT39) is shown in Figure 6-10 and described in Table 6-14 . Figure 6-10. Module Status n Register (MDSTATn) 31 18 17 16 Reserved EMUIHB EMURST R-0 R-0 R-0 15 13 12 11 10 9 8 7 6 5 0 Reserved M...

Page 75 - The module control

www.ti.com 6.7.10 Module Control n Register (MDCTLn) PSC Registers The module control n register (MDCTL0-MDCTL39) is shown in Figure 6-11 and described in Table 6-15 . Figure 6-11. Module Control n Register (MDCTLn) 31 16 Reserved R-0 15 11 10 9 8 7 3 2 0 Reserved EMUIHBIE EMURSTIE LRST Reserved NEX...

Page 77 - Chapter 7

Chapter 7 SPRU978E – March 2008 Power Management Topic .................................................................................................. Page 7.1 Overview .................................................................................. 78 7.2 PSC and PLLC Overview ...................

Page 78 - Power Management Features

www.ti.com 7.1 Overview 7.2 PSC and PLLC Overview Overview In many applications, there may be specific requirements to minimize power consumption for both powersupply (or battery) and thermal considerations. There are two components to power consumption: activepower and leakage power. Active power i...

Page 79 - Clock Management

www.ti.com 7.3 Clock Management 7.3.1 Module Clock ON/OFF 7.3.2 Module Clock Frequency Scaling 7.3.3 PLL Bypass and Power Down Clock Management The module clock on/off feature allows software to disable clocks to module individually, in order to reducethe module's active power consumption to 0. The ...

Page 80 - DSP Module Clock ON; DSP Sleep Mode Management; for information on the

www.ti.com 7.4 DSP Sleep Mode Management 7.4.1 DSP Sleep Modes 7.4.2 DSP Module Clock ON/OFF 7.4.2.1 DSP Module Clock ON DSP Sleep Mode Management The C64x+ DSP supports sleep mode management to reduce power: • DSP clock can be completely shut off • C64x+ Megamodule can be put in sleep mode – C64x+ ...

Page 81 - DSP Module Clock Off; Video DAC Power Down; Reference Guide

www.ti.com 7.4.2.2 DSP Module Clock Off 7.5 3.3 V I/O Power Down 7.6 Video DAC Power Down 3.3 V I/O Power Down In the clock Disable state, the DSP’s module clock is disabled, while DSP reset remains de-asserted. Thisstate is typically used to disable the DSP clock to save power. As mentioned in Sect...

Page 83 - Chapter 8

Chapter 8 SPRU978E – March 2008 Interrupt Controller The C64x+ Megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The interruptcontroller interfaces the system events to the CPU's interrupt and exception inputs. The interrupt controllersupports up to 128 system events, and ...

Page 85 - Chapter 9

Chapter 9 SPRU978E – March 2008 System Module Topic .................................................................................................. Page 9.1 Overview .................................................................................. 86 9.2 Device Identification ......................

Page 87 - Peripheral Status and Control

www.ti.com 9.4 3.3 V I/O Power-Down Control 9.5 Peripheral Status and Control 9.5.1 Timer Control 9.5.2 VPSS Clock and DAC Control 9.5.3 DDR2 VTP Control 9.5.4 HPI Control 3.3 V I/O Power-Down Control The VDD3P3V_PWDN register controls power to the 3.3 V I/O cells. Some 3.3 V I/Os default to powerdo...

Page 88 - Bandwidth Management; MSTID

www.ti.com 9.6 Bandwidth Management 9.6.1 Bus Master DMA Priority Control Bandwidth Management In order to determine allowed connections between masters and slaves, each master request source musthave a unique master ID (mstid) associated with it. The master ID for each DM643x DMP master is shownin ...

Page 89 - EDMA Transfer Controller Configuration; Boot Control; Master; The System Module contains the following boot control registers:

www.ti.com 9.6.2 EDMA Transfer Controller Configuration 9.7 Boot Control Boot Control Each switched central resource (SCR) performs prioritization based on the priority level of the master thatsends the command. Each bus master's priority is programmed in the chip-level Bus Master PriorityControl Re...

Page 92 - Device Configurations at Reset; Type

www.ti.com 10.1 Overview 10.2 Reset Pins 10.3 Device Configurations at Reset Overview There are different types of reset in the TMS320DM643x DMP. The types of reset differ by how they areinitiated and/or by their effect on the chip. Each type is briefly described in Table 10-1 . Refer to the device-...

Page 93 - DSP Reset

www.ti.com 10.4 DSP Reset 10.4.1 DSP Local Reset 10.4.2 DSP Module Reset 10.4.2.1 Software Reset Disable (SwRstDisable) DSP Reset Note: The effects of DSP local reset and DSP module reset have not been fully validated;therefore, these resets are not supported and should not be used. Instead, the POR...

Page 94 - Execute the IDLE instruction.

www.ti.com 10.4.2.2 Synchronous Reset (SyncReset) DSP Reset • Host: Assert the DSP local reset (Optional) – Clear the LRST bit in MDCTL39 to 0. This step is optional. This step asserts the DSP local reset, andis included here so that the DSP does not start running immediately upon it is subsequently...

Page 95 - SPRAAG0

Chapter 11 SPRU978E – March 2008 Boot Modes The TMS320DM643x DMP can boot from either asynchronous EMIF/NOR Flash directly or from internalboot ROM, as determined by the setting of the device boot and configuration pins. The input states of theboot and configuration pins are sampled and latched into...

Page 97 - Appendix A; Reference

Appendix A SPRU978E – March 2008 Revision History Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Additions/Modifications/Deletions Figure 6-1 Added Note. Section 6.3 Added Note. Section 10.4 Added Note. SPRU978E – March 20...

Page 98 - IMPORTANT NOTICE; Products

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...