Texas Instruments TMS320C6747 DSP - Manuals

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Manual Texas Instruments TMS320C6747 DSP

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Page 3 - Contents; Preface

Contents Preface ........................................................................................................................................ 6 1 Introduction ......................................................................................................................... 7 1.1 P...

Page 6 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; Enter the literature number in the search box provided at; SPRUFE8; — TMS320C674x DSP CPU and Instruction Set Reference Guide.; SPRUFK4; — TMS320C674x DSP Megamodule Reference Guide.; SPRUFK9; Provides an

Preface SPRUFM8 – September 2008 Read This First About This Manual This document describes the universal serial bus OHCI host controller. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hex...

Page 7 - Introduction; Purpose of the Peripheral

1 Introduction 1.1 Purpose of the Peripheral User's Guide SPRUFM8 – September 2008 Universal Serial Bus OHCI Host Controller This document describes the universal serial bus OHCI host controller. The USB OHCI host controller (HC) is a single port controller that communicates with USB devices at theU...

Page 8 - USB1 Module Clock and Reset; Internal System Bus Clocks Needed by the USB1 Module; Architecture; Provide the 48 MHz clock externally, on the USB_REFCLKIN pin.

2 Architecture 2.1 USB1 Module Clock and Reset 2.1.1 Internal System Bus Clocks Needed by the USB1 Module 2.1.2 USB1 Module Local Bus Clock and Local Reset 2.1.3 USB1 Module Bus 48-MHz Reference Clock Architecture www.ti.com The USB1 module requires that several different clocks are present before i...

Page 9 - USB1 Module Open Host Controller Interface Functionality; OHCI Controller Overview; USB1 Module Differences From OHCI Specification for USB; Power Switching Output Pins Not Supported

2.2 USB1 Module Open Host Controller Interface Functionality 2.2.1 OHCI Controller Overview 2.3 USB1 Module Differences From OHCI Specification for USB 2.3.1 Power Switching Output Pins Not Supported 2.3.2 Overcurrent Protection Input Pins Not Supported 2.3.3 No Ownership Change Interrupt www.ti.com...

Page 10 - Implementation of OHCI Specification for USB; USB Host Controller Endpoint Descriptor (ED) List Head Pointers

2.4 Implementation of OHCI Specification for USB 2.4.1 USB Host Controller Endpoint Descriptor (ED) List Head Pointers 2.4.2 OHCI USB Suspend State Architecture www.ti.com The OHCI Specification for USB provides a specific sequence of operations for the host controller driver toperform when setting ...

Page 11 - Figure 1

2.5 OHCI Interrupts 2.6 USB Host Controller Access to System Memory 2.7 Physical Addressing Processor physical address Processor virtual address Processor MMU 00000000h FFFFFFFFh www.ti.com Architecture The USB1 host controller can be controlled either by the ARM or the DSP. It has the ability to in...

Page 12 - Registers; OHCI; Table 1. USB Host Controller Registers

3 Registers Registers www.ti.com Most of the host controller (HC) registers are OHCI operational registers, defined by the OHCI Specification for USB . Four additional registers not specified by the OHCI Specification for USB provide additional information about the USB host controller state. USB ho...

Page 13 - OHCI Revision Number Register (HCREVISION); The OHCI revision number register (HCREVISION) is shown in; Figure 3

3.1 OHCI Revision Number Register (HCREVISION) 3.2 HC Operating Mode Register (HCCONTROL) www.ti.com Registers The OHCI revision number register (HCREVISION) is shown in Figure 2 and described in Table 2 . Figure 2. OHCI Revision Number Register (HCREVISION) 31 16 Reserved R-0 15 8 7 0 Reserved REV ...

Page 14 - Table 3. HC Operating Mode Register (HCCONTROL) Field Descriptions

Registers www.ti.com Table 3. HC Operating Mode Register (HCCONTROL) Field Descriptions Bit Field Value Description 31-11 Reserved 0 Reserved 10 RWE 0-1 Remote wake-up enable. 9 RWC 0-1 Remote wake-up connected. 8 IR 0 Interrupt routing. The USB host controller does not provide an SMI interrupt. Thi...

Page 15 - HC Command and Status Register (HCCOMMANDSTATUS); Figure 4

3.3 HC Command and Status Register (HCCOMMANDSTATUS) www.ti.com Registers The HC command and status register (HCCOMMANDSTATUS) shows the current state of the hostcontroller and accepts commands from the host controller driver. HCCOMMANDSTATUS is shown in Figure 4 and described in Table 4 . Figure 4....

Page 16 - HC Interrupt and Status Register (HCINTERRUPTSTATUS); Figure 5; Figure 5. HC Interrupt and Status Register (HCINTERRUPTSTATUS)

3.4 HC Interrupt and Status Register (HCINTERRUPTSTATUS) Registers www.ti.com The HC interrupt and status register (HCINTERRUPTSTATUS) reports the status of the USB hostcontroller internal interrupt sources. HCINTERRUPTSTATUS is shown in Figure 5 and described in Table 5 . Figure 5. HC Interrupt and...

Page 17 - HC Interrupt Enable Register (HCINTERRUPTENABLE); Figure 6

3.5 HC Interrupt Enable Register (HCINTERRUPTENABLE) www.ti.com Registers The HC interrupt enable register (HCINTERRUPTENABLE) enables various OHCI interrupt sources togenerate interrupts to the level 2 interrupt controller. HCINTERRUPTENABLE is shown in Figure 6 and described in Table 6 . Figure 6....

Page 18 - HC Interrupt Disable Register (HCINTERRUPTDISABLE); Figure 7

3.6 HC Interrupt Disable Register (HCINTERRUPTDISABLE) Registers www.ti.com The HC interrupt disable register (HCINTERRUPTDISABLE) is used to clear bits in the HC interruptenable register (HCINTERRUPTENABLE). HCINTERRUPTDISABLE is shown in Figure 7 and described in Table 7 . Figure 7. HC Interrupt D...

Page 19 - HC Current Periodic Register (HCPERIODCURRENTED); Figure 8; Table 8. HC HCAA Address Register (HCHCCA) Field Descriptions; Figure 9

3.7 HC HCAA Address Register (HCHCCA) 3.8 HC Current Periodic Register (HCPERIODCURRENTED) www.ti.com Registers The HC HCAA address register (HCHCCA) defines the physical address of the beginning of the HCCA.HCHCCA is shown in Figure 8 and described in Table 8 . Figure 8. HC HCAA Address Register (H...

Page 20 - HC Head Control Register (HCCONTROLHEADED); and described in

3.9 HC Head Control Register (HCCONTROLHEADED) Registers www.ti.com The HC head control register (HCCONTROLHEADED) defines the physical address of the head endpointdescriptor (ED) on the control ED list. HCCONTROLHEADED is shown in Figure 10 and described in Table 10 . Figure 10. HC Head Control Reg...

Page 21 - and

3.10 HC Current Control Register (HCCONTROLCURRENTED) www.ti.com Registers The HC current control register (HCCONTROLCURRENTED) defines the physical address of the nextendpoint descriptor (ED) on the control ED list. HCCONTROLCURRENTED is shown in Figure 11 and described in Table 11 . Figure 11. HC ...

Page 22 - Table 12. HC Head Bulk Register (HCBULKHEADED) Field Descriptions

3.11 HC Head Bulk Register (HCBULKHEADED) 3.12 HC Current Bulk Register (HCBULKCURRENTED) Registers www.ti.com The HC head bulk register (HCBULKHEADED) defines the physical address of the head endpointdescriptor (ED) on the bulk ED list. HCBULKHEADED is shown in Figure 12 and described in Table 12 ....

Page 23 - Table 14. HC Head Done Register (HCDONEHEAD) Field Descriptions

3.13 HC Head Done Register (HCDONEHEAD) 3.14 HC Frame Interval Register (HCFMINTERVAL) www.ti.com Registers The HC head done register (HCDONEHEAD) defines the physical address of the current head of the doneTD queue. HCDONEHEAD is shown in Figure 14 and described in Table 14 . Figure 14. HC Head Don...

Page 24 - Table 17. HC Frame Number Register (HCFMNUMBER) Field Descriptions

3.15 HC Frame Remaining Register (HCFMREMAINING) 3.16 HC Frame Number Register (HCFMNUMBER) Registers www.ti.com The HC frame remaining register (HCFMREMAINING) reports the number of full-speed bit timesremaining in the current frame. HCFMREMAINING is shown in Figure 16 and described in Table 16 . F...

Page 30 - Figure 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1)

3.22 HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Registers www.ti.com The HC port 1 status and control register (HCRHPORTSTATUS1) reports and controls the state of USBhost port 1. HCRHPORTSTATUS1 is shown in Figure 23 and described in Table 23 . Figure 23. HC Port 1 Status and Control Re...

Page 32 - Figure 24. HC Port 2 Status and Control Register (HCRHPORTSTATUS2)

3.23 HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Registers www.ti.com The HC port 2 status and control register (HCRHPORTSTATUS2) reports and controls the state of USBhost port 2. HCRHPORTSTATUS2 is shown in Figure 24 and described in Table 24 . Figure 24. HC Port 2 Status and Control Re...

Page 34 - IMPORTANT NOTICE

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...