Page 3 - Floating-Point Digital Signal Processors; The UHPI is only available on the C6727.
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C6727 extends SDRAM support to 256M-bit and 512M-bit devices. Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash devic...
Page 5 - Functional Block Diagram; shows the functional block diagram of the C672x device.
www.ti.com 1.3 Functional Block Diagram Program/Data RAM 256K Bytes 256 256 Program/Data ROM Page0 256K Bytes 256 Program/Data ROM Page1 128K Bytes 32 32 DMP PMP CSP 32 256 32K Bytes Program Cache 64 D1 Data R/W R/W Data D2 64 256 Program Fetch INT I/O C67x+ CPU Memory Controller 32 High-Performance...
Page 7 - Device Overview; Device Characteristics; Table 2-1. Characteristics of the C672x Processors; HARDWARE FEATURES
www.ti.com 2 Device Overview 2.1 Device Characteristics TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-1 provides an overview of the C672x DSPs. The table shows significant features of each device, including the capac...
Page 9 - CPU Interrupt Assignments; INSTRUCTION
www.ti.com 2.3 CPU Interrupt Assignments TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-2. New Floating-Point Instructions for C67x+ CPU FLOATING-POINT INSTRUCTION IMPROVES OPERATION (1) MPYSPDP SP x DP → DP Faster th...
Page 10 - The internal memory organization is illustrated in
www.ti.com 2.4 Internal Program/Data ROM and RAM 00 20 27 07 2F 28 08 0F 3F 38 37 30 1F 18 10 17 3F 38 37 30 1F 18 17 10 2F 28 27 20 0F 08 00 07 Byte ROM Page 1Base Address0x0004 0000 ROM Page 0Base Address0x0000 0000 Bank 0 Bank 1 Bank 2 Bank 3 13 33 10 30 17 37 14 34 1B 3B 18 38 1F 3F 1C 3C RAM Pa...
Page 11 - Table 2-4. Program Cache Control Registers; REGISTER NAME; CACHE MODE; CAUTION
www.ti.com 2.5 Program Cache TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C672x DSP executes code directly from a large on-chip 32K-byte program cache. The program cachehas these key features: • Wide 256-bit path to int...
Page 12 - illustrates the connectivity of the crossbar switch.; Figure 2-4. Block Diagram of Crossbar Switch; As shown in
www.ti.com 2.6 High-Performance Crossbar Switch SYSCLK3 SYSCLK1 SYSCLK2 SYSCLK3 BR3 BR4 2 1 Priority EMIF External Memory SDRAM/ Flash Priority 2 1 3 4 T2 SYSCLK2 SYSCLK1 BR1 SYSCLK2 SYSCLK1 BR2 Program Master Port (PMP) CPU Slave Port (CSP) Data Master Port (DMP) Memory Controller M1 T1 M2 Priority...
Page 13 - Example 1: Simultaneous accesses without conflict; LABEL
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The five bus masters arbitrate for five different target groups: T1 On-chip memories through the CPU Slave Port (CSP). T2 Memories on the external memory interface (EM...
Page 14 - contains a description of the bits.; NAME
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-5 shows the bit layout of the device-level bridge control register (CFGBRIDGE) and Table 2-7 contains a description of the bits. 31 16 Reserved 15 1 0 Reserved...
Page 15 - Memory Map Summary; A high-level memory map of the C672x DSP appears in; DESCRIPTION
www.ti.com 2.7 Memory Map Summary TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 A high-level memory map of the C672x DSP appears in Table 2-8 . The base address of each region is listed. Any address past the end address must...
Page 16 - The ROM bootmodes include:; Table 2-9. Required Boot Pin Settings at Device Reset; BOOT MODE
www.ti.com 2.8 Boot Modes TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C672x DSP supports only one hardware bootmode option, this is to boot from the internal ROMstarting at address 0x0000 0000. Other bootmode options ar...
Page 17 - shows the bit layout of the CFGPIN0 register and
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-6 shows the bit layout of the CFGPIN0 register and Table 2-10 contains a description of the bits. 31 8 Reserved 7 6 5 4 3 2 1 0 PINCAP7 PINCAP6 PINCAP5 PINCAP...
Page 19 - Pin Maps; and
www.ti.com 2.9 Pin Assignments 2.9.1 Pin Maps SPI0_ENA /I2C1_ SDA SPI0_CLK /I2C0_ SCL DV DD V SS EM_RW EM_RAS V SS EM_BA[1] EM_A[0] V SS EM_A[3] EM_A[5] EM_A[7] EM_A[9] DV DD V SS DV DD EM_WE_ DQM[3] EM_A[11] EM_A[8] EM_A[6] EM_A[4] EM_A[2] EM_A[1] EM_A[10] EM_BA[0] EM_CS[0] EM_CS[2] EM_OE /I2C1_ SP...
Page 21 - Terminal Functions
www.ti.com 2.9.2 Terminal Functions TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12 , the Terminal Functions table, identifies the external signal names, the associated pin/ball numbers along with the mechanical pac...
Page 27 - provides a
www.ti.com C672x DSP: 672767266722 PREFIX DEVICE SPEED RANGE TMS 320 C6727 GDH 250 TMX = Experimental deviceTMP = Prototype deviceTMS = Qualified device DEVICE FAMILY 320 = TMS320 t DSP family PACKAGE TYPE ठGDH = 256-terminal plastic BGAZDH = 256-terminal Green plastic BGARFP = 144-pin PowerPAD ...
Page 29 - Optimizing
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 SPRAA69 Using the TMS320C672x Bootloader Application Report. This document describes thedesign details about the TMS320C672x bootloader. This document also addresses p...
Page 30 - Device Configuration Registers
www.ti.com 3 Device Configurations 3.1 Device Configuration Registers 3.2 Peripheral Pin Multiplexing Options TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C672x DSP includes several device-level configuration registers, ...
Page 31 - Peripheral Pin Multiplexing Control; lists the options for configuring the shared EMIF and UHPI pins.; While
www.ti.com 3.3 Peripheral Pin Multiplexing Control TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 3-3 lists the options for configuring the SPI1, McASP0, and McASP1 pins. Note that there are additional finer grain optio...
Page 32 - Table 3-5. Priority of Control of Data Output on Multiplexed Pins; PIN
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 3-5. Priority of Control of Data Output on Multiplexed Pins PIN FIRST PRIORITY SECOND PRIORITY THIRD PRIORITY SPI0_SOMI/I2C0_SDA SPI0_SOMI I2C0_SDA SPI0_CLK/I2C0_...
Page 33 - Peripheral and Electrical Specifications; Electrical Specifications; Over Operating Case Temperature Range (Unless Otherwise Noted); UNIT
www.ti.com 4 Peripheral and Electrical Specifications 4.1 Electrical Specifications 4.2 Absolute Maximum Ratings (1) (2) 4.3 Recommended Operating Conditions (1) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 This section pro...
Page 34 - Electrical Characteristics
www.ti.com 4.4 Electrical Characteristics TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Over Operating Case Temperature Range (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OH High Level Output Voltage ...
Page 35 - Parameter Information; Parameter Information Device-Specific Information; Tester Pin Electronics; Figure 4-1. Test Load Circuit for AC Timing Measurements; MIN for input clocks,; MAX and V; MIN for output clocks.; Figure 4-3. Rise and Fall Transition Time Voltage Reference Levels
www.ti.com 4.5 Parameter Information 4.5.1 Parameter Information Device-Specific Information Transmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see note) Tester Pin Electronics Data Sheet Timing Reference Point OutputUnderTest 42 Ω 3.5 nH Device Pin(see note) V ref = 1.5 V V ref = V IL MAX (or V OL MAX) V ...
Page 36 - Timing Parameter Symbology; Lowercase subscripts and their meanings:
www.ti.com 4.6 Timing Parameter Symbology TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Timing parameter symbols used in the timing requirements and switching characteristics tables arecreated in accordance with JEDEC Standar...
Page 38 - Reset Electrical Data/Timing; assumes testing over recommended operating conditions.; MIN
www.ti.com 4.8 Reset 4.8.1 Reset Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. TheRESET signal can be asser...
Page 39 - dMAX Device-Specific Information; shows a block diagram of the dMAX controller.
www.ti.com 4.9 Dual Data Movement Accelerator (dMAX) 4.9.1 dMAX Device-Specific Information TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The dMAX is a module designed to perform Data Movement Acceleration. The dMAX controll...
Page 40 - dMAX; Figure 4-4. dMAX Controller Block Diagram
www.ti.com Event Entry #0 Event Entry #k Event Entry #31 Transfer Entry #0 Transfer Entry #k Transfer Entry #7 Reserved Event Entry Table Transfer Entry Table HiMAX RAM R/W Control R/W HiMAX (MAX0) Event Encoder + Event and Interrupt Registers LoMAX(MAX1) Transfer Entry Table LoMAX RAM R/W Transfer ...
Page 41 - The dMAX controller comprises:
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The dMAX controller comprises: • Event and interrupt processing registers • Event encoder • High-priority event Parameter RAM (PaRAM) • Low-priority event Parameter RA...
Page 42 - Table 4-2. dMAX Peripheral Event Input Assignments; EVENT NUMBER
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-2 lists how the synchronization events are associated with event numbers in the dMAX controller. Table 4-2. dMAX Peripheral Event Input Assignments EVENT NUMBER...
Page 43 - is a list of the dMAX registers.; BYTE ADDRESS
www.ti.com 4.9.2 dMAX Peripheral Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-3 is a list of the dMAX registers. Table 4-3. dMAX Configuration Registers BYTE ADDRESS REGISTER NAME DESCRIPTIO...
Page 44 - External Interrupts
www.ti.com 4.10 External Interrupts TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C672x DSP has no dedicated general-purpose interrupt pins, but the dMAX can be used incombination with a McASP AMUTEIN signal to provide ex...
Page 49 - through; Table 4-5. EMIF SDRAM Interface Timing Requirements; Table 4-6. EMIF SDRAM Interface Switching Characteristics; PARAMETER
www.ti.com 4.11.3 EMIF Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-5 through Table 4-8 assume testing over recommended operating conditions (see Figure 4-7 through Figure 4-13 ). Table 4-5. E...
Page 50 - Table 4-7. EMIF Asynchronous Interface Timing Requirements
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-7. EMIF Asynchronous Interface Timing Requirements (1) (2) NO. MIN MAX UNIT Input setup time, read data valid on EM_D[31:0] before EM_CLK 28 t su(EM_DV-EM_CLKH)...
Page 53 - Figure 4-11. Asynchronous Write WE Strobe Mode
www.ti.com EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] SETUP STROBE HOLD 21 22 23 23 32 32 21 22 23 23 22 26 26 24 27 ASYNCHRONOUS WRITEWE STROBE MODE ADDRESS ADDRESS WRITE DATA 22 BYTE WRITE STROBES EM_CS[2] EM_WE_DQM[3:0] EM_OE EM_WE EM_RW EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] SETUP STROBE HOLD 22 2...
Page 55 - Figure 4-14. UHPI Strobe and Ready Interaction
www.ti.com 4.12 Universal Host-Port Interface (UHPI) [C6727 Only] 4.12.1 UHPI Device-Specific Information UHPI_HDS[2] UHPI_HDS[1] UHPI_HCS UHPI_HRDY Internal HSTROBE Internal HRDY TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 200...
Page 57 - Figure 4-16. UHPI Multiplexed Host Address/Data Fullword Mode
www.ti.com EM_D[31:16]/UHPI_HA[15:0] (A) UHPI_HCNTL[1:0] UHPI_HD[15:0] UHPI_HD[16]/HHWIL UHPI_HD[31:17] UHPI_HAS (B) UHPI_HBE[3:0] UHPI_HRW UHPI_HDS[2] UHPI_HDS[1] UHPI_HCS UHPI_HRDY AMUTE2/HINT NC A[x:y] (C) D[15:0] D[16] BE[3:0] (D) R/W WE (E) RD (E) CS RDY INTERRUPT DSP External Host MCU D[31:17]...
Page 59 - is a list of the UHPI registers.
www.ti.com 4.12.2 UHPI Peripheral Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-11 is a list of the UHPI registers. Table 4-11. UHPI Configuration Registers BYTE ADDRESS REGISTER NAME DESCRIP...
Page 62 - Table 4-15. UHPI Read and Write Timing Requirements
www.ti.com 4.12.3 UHPI Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.12.3.1 Universal Host-Port Interface (UHPI) Read and Write Timing Table 4-15 and Table 4-16 assume testing over recommended operati...
Page 63 - Table 4-16. UHPI Read and Write Switching Characteristics
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-16. UHPI Read and Write Switching Characteristics (1) (2) NO. PARAMETER MIN MAX UNIT Case 1. HPIC or HPIA read 1 15 Case 2. HPID read with no 9 * 2H + 20 (3) a...
Page 66 - Figure 4-23. Multiplexed Read Timings With UHPI_HAS Held High
www.ti.com UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HRW UHPI_HHWIL HSTROBE (A) UHPI_HD[15:0] UHPI_HRDY 16 15 37 13 14 16 15 37 13 3 1 2 3 1 2 38 7 4 6 TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 A. See Figure 4-14 . B. Depend...
Page 67 - Figure 4-24. Multiplexed Write Timings With UHPI_HAS Held High
www.ti.com UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HRW UHPI_HHWIL HSTROBE (A) UHPI_HD[15:0] UHPI_HRDY 34 5 17 18 17 18 34 5 4 38 37 13 16 15 14 13 16 15 37 35 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 A. See Figure 4-14 ....
Page 68 - Up to sixteen transmit or receive data pins and serializers
www.ti.com 4.13 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) Receive Logic Clock/Frame Generator State Machine Clock Check and Serializer 0 Serializer 1 Serializer y GIO Control DIT RAM 384 C384 U Optional Transmit Formatter Receive Formatter Transmit Logic Clock/Frame Generator Stat...
Page 69 - The three McASPs on C672x have different configurations (see; Table 4-17. McASP Configurations on C672x DSP; McASP; to use as a mute input.
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The three McASPs on C672x have different configurations (see Table 4-17 ). NOTE: McASP2 is not available on the C6722. Table 4-17. McASP Configurations on C672x DSP Mc...
Page 73 - shows the bit layout of the CFGMCASP0 register and
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-26 shows the bit layout of the CFGMCASP0 register and Table 4-19 contains a description of the bits. 31 8 Reserved 7 3 2 0 Reserved AMUTEIN0 R/W, 0 LEGEND: R/...
Page 75 - shows the bit layout of the CFGMCASP2 register and
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-28 shows the bit layout of the CFGMCASP2 register and Table 4-21 contains a description of the bits. 31 8 Reserved 7 3 2 0 Reserved AMUTEIN2 R/W, 0 LEGEND: R/...
Page 77 - Table 4-23. McASP Switching Characteristics
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-23. McASP Switching Characteristics (1) NO. PARAMETER MIN MAX UNIT Cycle time, AHCLKR internal, AHCLKR output 20 Cycle time, AHCLKR external, AHCLKR output 20 ...
Page 82 - is a list of the SPI registers.
www.ti.com 4.14.2 SPI Peripheral Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-24 is a list of the SPI registers. Table 4-24. SPIx Configuration Registers SPI0 SPI1 REGISTER NAME DESCRIPTION B...
Page 83 - Table 4-25. General Timing Requirements for SPIx Master Modes
www.ti.com 4.14.3 SPI Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.14.3.1 Serial Peripheral Interface (SPI) Timing Table 4-25 through Table 4-32 assume testing over recommended operating conditions ...
Page 84 - Table 4-26. General Timing Requirements for SPIx Slave Modes
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-26. General Timing Requirements for SPIx Slave Modes (1) NO. MIN MAX UNIT greater of 8P or 9 t c(SPC)S Cycle Time, SPIx_CLK, All Slave Modes 256P ns 100 ns grea...
Page 85 - SPI Master Timings, 4-Pin Chip Select Option
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-27. Additional (1) SPI Master Timings, 4-Pin Enable Option (2) (3) NO. MIN MAX UNIT Polarity = 0, Phase = 0, 3P + 15 to SPIx_CLK rising Polarity = 0, Phase = 1...
Page 87 - SPI Slave Timings, 4-Pin Chip Select Option
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-30. Additional (1) SPI Slave Timings, 4-Pin Enable Option (2) (3) NO. MIN MAX UNIT Polarity = 0, Phase = 0, P – 10 3P + 15 from SPIx_CLK falling Polarity = 0, ...
Page 94 - is a list of the I2C registers.
www.ti.com 4.15.2 I2C Peripheral Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-33 is a list of the I2C registers. Table 4-33. I2Cx Configuration Registers I2C0 I2C1 REGISTER NAME DESCRIPTION B...
Page 95 - Table 4-34. I2C Input Timing Requirements
www.ti.com 4.15.3 I2C Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.15.3.1 Inter-Integrated Circuit (I2C) Timing Table 4-34 and Table 4-35 assume testing over recommended operating conditions (see Fi...
Page 97 - contains a block diagram of the RTI module.
www.ti.com 4.16 Real-Time Interrupt (RTI) Timer With Digital Watchdog 4.16.1 RTI/Digital Watchdog Device-Specific Information McASP0,1,2Transmit/ReceiveDMA Events McASP0,1,2Transmit/ReceiveDMA Events Counter 0 32-Bit + 32-Bit Prescale (Used by DSP BIOS) Capture 0 32-Bit + 32-Bit Prescale Counter 1 3...
Page 98 - is a list of the RTI registers.
www.ti.com 4.16.2 RTI/Digital Watchdog Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The digital watchdog is disabled by default. Once enabled, a sequence of two 16-bit key values (0xE51Afollowed by 0...
Page 99 - shows the bit layout of the CFGRTI register and
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-36. RTI Registers (continued) BYTE ADDRESS REGISTER NAME DESCRIPTION 0x4200 0088 RTIINTFLAG Interrupt Flags. Interrupt pending bits. 0x4200 0090 RTIDWDCTRL Dig...
Page 100 - External Clock Input From Oscillator or CLKIN Pin; in; FREQUENCY
www.ti.com 4.17 External Clock Input From Oscillator or CLKIN Pin OSCV DD C 5 C 7 C 8 X 1 R S R B OSCIN OSCOUT C 6 OSCV SS CLKIN Clock Input From OSCIN to PLL On-Chip 1.2-V Oscillator (a) External 3.3-V LVCMOS-Compatible Clock Source (b) OSCV DD OSCIN OSCOUT OSCV SS CLKIN Clock Input From CLKIN to P...
Page 103 - Table 4-40. Allowed PLL Operating Conditions; ALLOWED SETTING OR RANGE; at the board level through an external filter, as
www.ti.com BOARD DV DD (3.3 V) EMI Filter 10 m F 0.1 m F PLLHV Place Filter and Capacitors as Close to DSP as Possible EMI Filter: TDK ACF451832−333, −223, −153, or −103, Panasonic EXCCET103U, or Equivalent + TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – M...
Page 105 - Application Example; for an overview of each major block.
www.ti.com 5 Application Example 256K Bytes RAM Bytes ROM 384K Memory Controller C67x+ DSP Core Program Cache Crossbar Switch EMIF UHPI dMAX McASP0 SPI1 McASP1 I2C0 I2C1 RTI SPIO McASP2 PLL OSC ASYNC FLASH 100 MHz SDRAM DSP Host Microprocessor Audio Zone 1 SPI or I2C Control (optional) Audio Zone 2 ...
Page 106 - Revision History; Corrected addresses of the XGBLCTL register in
www.ti.com 6 Revision History TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 This data sheet revision history highlights the technical changes made to the SPRS268D device-specificdata sheet to make it an SPRS268E revision. Sco...
Page 107 - Mechanical Data; Package Thermal Resistance Characteristics; Table 7-2. Thermal Characteristics for RFP Package
www.ti.com 7 Mechanical Data 7.1 Package Thermal Resistance Characteristics TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 7-1 and Table 7-2 provide the thermal characteristics for the recommended package types used on ...
Page 108 - PowerPAD Thermally Enhanced Package Technical Brief; Figure 7-1. Standoff Height Measurement on 144-Pin RFP Package
www.ti.com 7.2 Supplementary Information About the 144-Pin RFP PowerPAD™ Package 7.2.1 Standoff Height Standoff Height TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 This section highlights a few important details about the 14...
Page 109 - PowerPADTM PCB Footprint; Packaging Information; Figure 7-2. Soldermask Opening Should Match Size of DSP Thermal Pad; On the 144-pin RFP package, the actual size of the Thermal Pad is 5.4 mm
www.ti.com 7.2.2 PowerPAD™ PCB Footprint Thermal Pad on Top Copper should be as large as Possible. Soldermask opening should be smaller and match the size of the thermal pad on the DSP. 7.3 Packaging Information TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E ...
Page 111 - PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TMX320C6722RFP OBSOLETE HTQFP RFP 144 TBD Call TI Call TI TMX320C6726RFP OBSOLETE HTQFP RFP 144 TBD Call TI Call TI TMX320C6727GDH OBSOLETE BGA GDH 256 TBD ...
Page 114 - IMPORTANT NOTICE; Products
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...
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