Texas Instruments TMS320C6452 DSP - Manuals

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Manual Texas Instruments TMS320C6452 DSP

Summary

Page 3 - Contents; Preface

Contents Preface ............................................................................................................................... 6 1 Introduction ................................................................................................................ 9 1.1 Purpose of the Peri...

Page 6 - Read This First; About This Manual; This document uses the following conventions.; Related Documents From Texas Instruments; . Tip: Enter the literature number in the search box; Data Manual—; and electrical characteristics of the device.; CPU—

Preface SPRUF85 – October 2007 Read This First About This Manual This document describes the operation of the DDR2 Memory Controller in the TMS320C6452. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following ...

Page 9 - Introduction; Purpose of the Peripheral; Figure 1

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features 1.3 Functional Block Diagram User's Guide SPRUF85 – October 2007 DSP DDR2 Memory Controller This document describes the DDR2 memory controller in the device. The DDR2 memory controller is used to interface with JESD79D-2A standard compliant D...

Page 10 - Industry Standard(s) Compliance Statement; Figure 1. DDR2 Memory Controller Block Diagram

www.ti.com L1 S1 M1 D1 Data path A Register file A Register file B D2 Data path B S2 M2 L2 L1 data memory controller Cache control Memory protection Interrupt and exception controller Power control Instruction decode 16/32−bit instruction dispatch Instruction fetch SPLOOP buffer C64x+ CPU IDMA Bandw...

Page 11 - Clock Control; Peripheral Architecture; Section 3

www.ti.com 2 Peripheral Architecture 2.1 Clock Control 2.2 Memory Map 2.3 Signal Descriptions Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices andsupports such features as self-refresh mode and prioritized refresh. In addition, it provid...

Page 12 - Figure 2. DDR2 Memory Controller Signals; Pin

www.ti.com DDR_D[31:0] DDR2 memory controller DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_DQS[3:0] DDR_A[13:0] DDR_VREF DDR_DQGATE[3:0] DDR_DQS[3:0] DDR_ODT[1:0] Peripheral Architecture Figure 2. DDR2 Memory Controller Signals Table 1. DDR2 Memory Controller Si...

Page 13 - Table 2; Table 2. DDR2 SDRAM Commands; Command; Table 3. Truth Table for DDR2 SDRAM Commands

www.ti.com 2.4 Protocol Description(s) Peripheral Architecture The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2 . Table 3 shows the signal truth table for the DDR2 SDRAM commands. Table 2. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row. DCA...

Page 14 - Refresh Mode; Figure 3; Figure 3. DDR2 MRS and EMRS Command; Figure 4

www.ti.com 2.4.1 Mode Register Set (MRS and EMRS) COL MRS/EMRS BANK DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_CAS DDR_BA[2:0] DDR_A[13:0] 2.4.2 Refresh Mode Peripheral Architecture DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory foroperation. These registe...

Page 15 - Figure 4. Refresh Command; is incurred before; Figure 5. ACTV Command

www.ti.com REFR DDR_CLKDDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:0] 2.4.3 Activation (ACTV) ACTV BANK ROW DDR_CLKDDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:0] Peripheral Architecture Figure 4. Refresh Command The DDR2 memory ...

Page 16 - Figure 6; Figure 6. DCAB Command; Figure 7; Figure 7. DEAC Command

www.ti.com 2.4.4 Deactivation (DCAB and DEAC) DCAB DDR_CLKDDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:11, 9:0] DDR_A[10] DEAC DDR_CLKDDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:11, 9:0] DDR_A[10] Peripheral Architecture The prec...

Page 17 - READ Command; Figure 8; Figure 8. DDR2 READ Command

www.ti.com 2.4.5 READ Command DDR_D[31:0] DDR_DQS[3:0] COL BANK DDR_A[10] CAS Latency D0 D1 D2 D3 D4 D5 D6 D7 DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:0] Peripheral Architecture Figure 8 shows the DDR2 memory controller performing a read burst from DDR2...

Page 18 - Memory Width and Byte Alignment; Figure 9; Figure 9. DDR2 WRT Command; Table 4; Table 4. Addressable Memory Ranges; Memory Width

www.ti.com 2.4.6 Write (WRT) Command DDR_D[31:0] DDR_DQS[3:0] COL BANK DQM7 Sample D0 D1 D2 D3 D4 D5 D6 D7 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8 Write Latency DDR_A[10] DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:0] 2.5 Memory Width and Byte Alignment Periphe...

Page 19 - DDR2 memory controller data bus; Address Mapping; right aligned on the data bus.; Figure 10. Byte Alignment; Table 5; Table 5. Bank Configuration Register Fields for Address Mapping; Bit Field; and

www.ti.com DDR2 memory controller data bus DDR_D[31:24] (Byte Lane 3) DDR_D[23:16] (Byte Lane 2) DDR_D[15:8] (Byte Lane 1) DDR_D[7:0] (Byte Lane 0) 32-bit memory device 16-bit memory device 2.6 Address Mapping Peripheral Architecture Figure 10 shows the byte lanes used on the DDR2 memory controller....

Page 22 - DDR2 Memory Controller Interface; Table 6; Table 6. DDR2 Memory Controller FIFO Description; FIFO

www.ti.com 0 1 2 3 M Bank 0 Row 0 Row 1 Row 2 Row N C o l l C o l C o l C o Row 0 Row N Row 1 Row 2 C C Bank 1 l l 0 2 1 o o C C l l 3 M o o Row 0 Row N Row 1 Row 2 C C Bank 2 l l 0 2 1 o o l l l l Row N Row 2 Row 0 Row 1 Bank P 0 1 2 3 M C C l l 3 M o o o C o C o C o C 2.7 DDR2 Memory Controller In...

Page 23 - Command Ordering and Scheduling, Advanced Concept; Figure 15. DDR2 Memory Controller FIFO Block Diagram; Selects the oldest command

www.ti.com Command/Data Scheduler Command FIFO Write FIFO Read FIFO Registers Commandto Memory Write Datato Memory Read DatafromMemory CommandData EDMA BUS 2.7.1 Command Ordering and Scheduling, Advanced Concept Peripheral Architecture Figure 15. DDR2 Memory Controller FIFO Block Diagram The DDR2 me...

Page 24 - Command Starvation; reached

www.ti.com 2.7.2 Command Starvation Peripheral Architecture Next, the DDR2 memory controller examines each of the commands selected by the individual mastersand performs the following reordering: • Among all pending reads, selects reads to rows already open. Among all pending writes, selects writest...

Page 25 - Possible Race Condition; Refresh Scheduling; Table 7; Table 7. Refresh Urgency Levels; Urgency Level

www.ti.com 2.7.3 Possible Race Condition 2.8 Refresh Scheduling Peripheral Architecture A race condition may exist when certain masters write data to the DDR2 memory controller. For example,if master A passes a software message via a buffer in DDR2 memory and does not wait for indication thatthe wri...

Page 26 - Reset Considerations; Table 8; Table 8. Reset Sources; Reset Signal; Figure 16. DDR2 Memory Controller Reset Block Diagram

www.ti.com 2.9 Self-Refresh Mode 2.10 Reset Considerations Hard reset from PLLCTL1 DDR PSC DDR2 memory controller registers State machine VRST VCTL_RST Peripheral Architecture Setting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the DDR2memory controller to pla...

Page 27 - DDR2 SDRAM Memory Initialization; DDR2 SDRAM Device Mode Register Configuration Values; Table 9. DDR2 SDRAM Mode Register Configuration

www.ti.com 2.11 DDR2 SDRAM Memory Initialization 2.11.1 DDR2 SDRAM Device Mode Register Configuration Values Peripheral Architecture DDR2 SDRAM devices contain mode and extended mode registers that configure the mode of operationfor the device. These registers control parameters such as burst type, ...

Page 28 - Interrupt Support; value needed to meet the DDR2 SDRAM device timings.

www.ti.com 2.11.2 DDR2 SDRAM Initialization After Reset 2.11.3 DDR2 SDRAM Initialization After Register Configuration 2.12 Interrupt Support 2.13 EDMA Event Support 2.14 Emulation Considerations Peripheral Architecture Table 10. DDR2 SDRAM Extended Mode Register 1 Configuration (continued) Mode Mode...

Page 29 - Connecting the DDR2 Memory Controller to DDR2 SDRAM; Using the DDR2 Memory Controller; show a high-level view of the three memory topologies

www.ti.com 3 Using the DDR2 Memory Controller 3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM Using the DDR2 Memory Controller The following sections show various ways to connect the DDR2 memory controller to DDR2 memorydevices. The steps required to configure the DDR2 memory controller for ...

Page 30 - Figure 17. Connecting to Two 16-Bit DDR2 SDRAM Devices

www.ti.com CK CK CKE CS WE RAS CAS LDM UDM LDQS UDQS BA[2:0] A[12:0] DQ[15:0] VREF DDR2 memory x16−bit LDQS UDQS DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR_DQM0 DDR_CAS DDR_DQM1 DDR_DQS0 DDR_DQS0 DDR_DQS1 DDR_DQS1 DDR_BA[2:0] DDR_A[13:0] DDR_D[15:0] DDR_DQM2 DDR_DQM3 DDR_DQS2 DDR_DQS3 DDR_D[3...

Page 31 - Figure 18. Connecting to a Single 16-Bit DDR2 SDRAM Device

www.ti.com DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR_CAS DDR_DQM0 DDR_DQM1 DDR_DQS0 DDR_DQS1 DDR_BA[2:0] DDR_A[13:0] DDR_D[15:0] DDR_VREF DDR_ODT0 DDR_DQS0 DDR_DQS1 CK CK CKE CS WE RAS CAS LDM UDM LDQS UDQS BA[2:0] A[12:0] DQ[15:0] ODT VREF LDQS UDQS DDR2 memory x16−bit VREF DDR2 memory cont...

Page 32 - Figure 19. Connecting to Two 8-Bit DDR2 SDRAM Devices

www.ti.com CK CK CKE CS WE RAS CAS DM DQS BA[2:0] A[13:0] DQ[7:0] VREF DDR2 memory x8−bit DQS RDQS DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR_DQM0 DDR_CAS DDR_DQS0 DDR_DQS0 DDR_BA[2:0] DDR_A[13:0] DDR_D[7:0] DDR_DQM1 DDR_DQS1 DDR_D[15:8] DDR_VREF DDR2 memory controller ODT DDR_ODT0 DDR_ODT1 D...

Page 33 - , where each device has the; Table 11. SDCFG Configuration; Field; memory refresh period

www.ti.com 3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications 3.2.1 Programming the SDRAM Configuration Register (SDCFG) 3.2.2 Programming the SDRAM Refresh Control Register (SDRFC) Using the DDR2 Memory Controller The DDR2 memory controller allows a high degree of pr...

Page 34 - Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2); displays the DDR2-533 refresh rate specification.; Table 12. DDR2 Memory Refresh Specification; shows the resulting SDRFC configuration.; Table 13. SDRFC Configuration; Table 14. SDTIM1 Configuration

www.ti.com 3.2.3 Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2) Using the DDR2 Memory Controller Table 12 displays the DDR2-533 refresh rate specification. Table 12. DDR2 Memory Refresh Specification Symbol Description Value t REF Average Periodic Refresh Interval 7.8 μ s Therefore, the valu...

Page 35 - Configuring the DDR2 Memory Controller Control Register (DMCCTL); Table 15. SDTIM2 Configuration

www.ti.com 3.2.4 Configuring the DDR2 Memory Controller Control Register (DMCCTL) Using the DDR2 Memory Controller Table 15. SDTIM2 Configuration DDR2 SDRAM Data Register Field Sheet Parameter Data Sheet Formula (Register Field Name Name Description Value Field Must Be ≥ ) Value T_ODT t AOND t AOND ...

Page 36 - DDR2 Memory Controller Registers; manual for the memory address of these registers.; Table 17. DDR2 Memory Controller Registers; Offset

www.ti.com 4 DDR2 Memory Controller Registers DDR2 Memory Controller Registers Table 17 lists the memory-mapped registers for the DDR2 memory controller. See the device-specific data manual for the memory address of these registers. Table 17. DDR2 Memory Controller Registers Offset Acronym Register ...

Page 37 - DDR2 Memory Controller Status Register (DMCSTAT); The Module ID and Revision register (MIDR) is shown in; Table 18. Module ID and Revision Register (MIDR) Field Descriptions; The DDR2 memory controller status register (DMCSTAT) is shown in

www.ti.com 4.1 Module ID and Revision Register (MIDR) 4.2 DDR2 Memory Controller Status Register (DMCSTAT) DDR2 Memory Controller Registers The Module ID and Revision register (MIDR) is shown in Figure 20 and described in Table 18 . Figure 20. Module ID and Revision Register (MIDR) 31 30 29 16 Reser...

Page 38 - controller. The SDCFG is shown in; Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions; Bit

www.ti.com 4.3 SDRAM Configuration Register (SDCFG) DDR2 Memory Controller Registers The SDRAM configuration register (SDCFG) contains fields that program the DDR2 memory controller tomeet the specification of the DDR2 memory. These fields configure the DDR2 memory controller to matchthe data bus wi...

Page 40 - The SDRFC is shown in

www.ti.com 4.4 SDRAM Refresh Control Register (SDRFC) DDR2 Memory Controller Registers The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to: • Enter and Exit the self-refresh state. • Meet the refresh requirement of the attached DDR2 device by programming the...

Page 41 - and described in; Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions

www.ti.com 4.5 SDRAM Timing 1 Register (SDTIM1) DDR2 Memory Controller Registers The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the ACtiming specification of the DDR2 memory. Note that DDR_CLK is equal to the period of the DDR_CLKsignal. See the DDR2 memor...

Page 43 - Table 23. SDRAM Timing 2 Register (SDTIM2) Field Descriptions

www.ti.com 4.6 SDRAM Timing 2 Register (SDTIM2) DDR2 Memory Controller Registers Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (SDTIM2) also configures theDDR2 memory controller to meet the AC timing specification of the DDR2 memory. See the DDR2memory data sheet for informa...

Page 45 - DDR2 Memory Controller Control Register (DMCCTL)

www.ti.com 4.8 DDR2 Memory Controller Control Register (DMCCTL) DDR2 Memory Controller Registers The DDR2 memory controller control register (DMCCTL) resets the interface logic of the DDR2 memorycontroller. The DMCCTL is shown in Figure 27 and described in Table 25 . Figure 27. DDR2 Memory Controlle...

Page 46 - IMPORTANT NOTICE; Products

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