Texas Instruments TMS320C642x DSP - Manuals

Page 3 - Contents

Contents Preface ............................................................................................................................... 6 1 Introduction ................................................................................................................ 7 1.1 Purpose of the Peri...

Page 6 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; Enter the literature number in the search box; SPRUEM3; — TMS320C642x DSP Peripherals Overview Reference Guide.

Preface SPRUEM4A – November 2007 Read This First About This Manual This document describes the DDR2 memory controller in the TMS320C642x Digital Signal Processor(DSP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example,...

Page 7 - Introduction; Purpose of the Peripheral

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRUEM4A – November 2007 DDR2 Memory Controller This document describes the DDR2 memory controller in the TMS320C642x Digital Signal Processor(DSP). The DDR2 memory controller is used to interface with JESD79D-2A standard complia...

Page 8 - Figure 1; Figure 1. Data Paths to DDR2 Memory Controller; Section 3

www.ti.com 1.3 Functional Block Diagram SCR DDR2 memory controller BUS BUS ExternalDDR2 SDRAM DSP Master peripherals EDMA VPSS 1.4 Supported Use Case Statement 1.5 Industry Standard(s) Compliance Statement Introduction The DDR2 memory controller is the main interface to external DDR2 memory. Figure ...

Page 9 - Clock Control; Clock Source; memory; Peripheral Architecture; Figure 2. DDR2 Memory Controller Clock Block Diagram

www.ti.com 2 Peripheral Architecture 2.1 Clock Control 2.1.1 Clock Source DDR2 memory controller /2 PLLC2 /3 PLLC1 X2_CLK VCLK DDR_CLK DDR_CLK PLL2_SYSCLK1 SYSCLK2 Peripheral Architecture This section describes the architecture of the DDR2 memory controller as well as how it is structured andhow it ...

Page 10 - Memory Map; Table 1; Table 1. PLLC2 Configuration; PLL Multiplier; are all on the VCLK domain. From this, you can see that VCLK drives

www.ti.com 2.1.2 Clock Configuration 2.1.3 DDR2 Memory Controller Internal Clock Domains 2.2 Memory Map Peripheral Architecture The frequency of PLL2_SYSCLK1 is configured by selecting the appropriate PLL multiplier and dividerratio. The PLL multiplier and divider ratio are selected by programming r...

Page 11 - Signal Descriptions; The DDR2 memory controller signals are shown in; Figure 3. DDR2 Memory Controller Signals

www.ti.com 2.3 Signal Descriptions DDR_D[31:0] DDR2 memory controller DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_DQS[3:0] DDR_A[12:0] DDR_ZN DDR_ZP 200 Ω 200 Ω Peripheral Architecture The DDR2 memory controller signals are shown in Figure 3 and described in Ta...

Page 12 - Table 3; Table 3. DDR2 SDRAM Commands; Command; Table 4. Truth Table for DDR2 SDRAM Commands

www.ti.com 2.4 Protocol Description(s) Peripheral Architecture The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 3 . Table 4 shows the signal truth table for the DDR2 SDRAM commands. Table 3. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row. DCA...

Page 13 - Refresh Mode; RFR; Figure 4; Figure 4. Refresh Command

www.ti.com 2.4.1 Refresh Mode DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[12:0] DDR_BA[2:0] DDR_DQM[3:0] RFR DDR_CLK Peripheral Architecture The DDR2 memory controller issues refresh commands to the DDR2 SDRAM memory ( Figure 4 ). REFR is automatically preceded by a DCAB command, ensuring th...

Page 14 - DCAB; Figure 5; Figure 5. DCAB Command

www.ti.com 2.4.2 Deactivation (DCAB and DEAC) DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WE DDR_A[12,11, 9:0] DDR_BA[2:0] DDR_DQM[3:0] DCAB DDR_A[10] DDR_CAS DDR_CLK Peripheral Architecture The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller orfollowing the initia...

Page 15 - DEAC; Figure 6; Figure 6. DEAC Command

www.ti.com DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WE DDR_A[12,11, 9:0] DDR_BA[2:0] DDR_DQM[3:0] DEAC DDR_A[10] DDR_CAS DDR_CLK Peripheral Architecture The DEAC command closes a single bank of memory specified by the bank select signals. Figure 6 shows the timings diagram for a DEAC command. Figure 6. DE...

Page 16 - is incurred before; Figure 7. ACTV Command

www.ti.com 2.4.3 Activation (ACTV) DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WE DDR_BA[2:0] DDR_DQM[3:0] ACTV DDR_A[12:0] DDR_CAS BANK ROW DDR_CLK Peripheral Architecture The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write toa closed row of memory. The ACTV co...

Page 17 - READ Command; Figure 8; Figure 8. DDR2 READ Command

www.ti.com 2.4.4 READ Command DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_CAS DDR_DQM[3:0] DDR_D[31:0] DDR_A[12:0] DDR_RAS DDR_DQS[3:0] COL BANK DDR_A[10] DDR_BA[2:0] CAS Latency D0 D1 D2 D3 D4 D5 D6 D7 DDR_CLK Peripheral Architecture Figure 8 shows the DDR2 memory controller performing a read burst from DDR2...

Page 18 - Figure 9; Figure 9. DDR2 WRT Command

www.ti.com 2.4.5 Write (WRT) Command DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_CAS DDR_DQM[3:0] DDR_D[31:0] DDR_A[12:0] DDR_RAS DDR_DQS[3:0] COL BANK DDR_A[10] DDR_BA[2:0] DQM7 Sample D0 D1 D2 D3 D4 D5 D6 D7 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8 Write Latency DDR_CLK Peripheral Architecture Prior to a WRT comm...

Page 19 - shows the timing for an MRS and EMRS command.; Figure 10. DDR2 MRS and EMRS Command

www.ti.com 2.4.6 Mode Register Set (MRS and EMRS) DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WE DDR_BA[2:0] COL MRS/EMRS DDR_A[12:0] DDR_CAS BANK DDR_CLK Peripheral Architecture DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory foroperation. These registers control burst ty...

Page 20 - Memory Width and Byte Alignment; DDR2 memory controller data bus; Table 5; Table 5. Addressable Memory Ranges; Memory Width

www.ti.com 2.5 Memory Width and Byte Alignment DDR2 memory controller data bus DDR_D[31:24] DDR_D[23:16] DDR_D[15:8] DDR_D[7:0] 32-bit memory device 16-bit memory device Peripheral Architecture The DDR2 memory controller supports memory widths of 16 bits and 32 bits. Table 5 summarizes the addressab...

Page 21 - Endianness Support; Table 6

www.ti.com 2.6 Endianness Support Peripheral Architecture The DDR2 memory controller supports both big-endian and little-endian operating modes. The endiannessmode selection at the time of an access determines the order in which data on the internal data bus iswritten to or read from devices that ar...

Page 22 - Address Mapping; Table 8; Table 8. Bank Configuration Register Fields for Address Mapping; Bit Field; As stated in

www.ti.com 2.7 Address Mapping Peripheral Architecture The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. Thisstatement is true regardless of the number of external physical devices mapped to a given chip selectspace. The DDR2 memory controller receives DDR2 memo...

Page 26 - DDR2 Memory Controller Interface; Scheduler; describes the purpose of each FIFO.; Table 11. DDR2 Memory Controller FIFO Description; FIFO; Figure 14. DDR2 Memory Controller FIFO Block Diagram

www.ti.com 2.8 DDR2 Memory Controller Interface Command/Data Scheduler Command FIFO Write FIFO Read FIFO Registers Commandto Memory Write Datato Memory Read DatafromMemory CommandData Peripheral Architecture To move data efficiently from on-chip resources to external DDR2 SDRAM memory, the DDR2 memo...

Page 27 - Command Ordering and Scheduling, Advanced Concept

www.ti.com 2.8.1 Command Ordering and Scheduling, Advanced Concept Peripheral Architecture The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieveefficient transfers with maximum throughput. The goal is to maximize the utilization of the data, address,and comm...

Page 29 - Refresh Scheduling; . Whenever the refresh level of urgency is reached, the DDR2 memory; Table 12. Refresh Urgency Levels; Urgency Level

www.ti.com 2.9 Refresh Scheduling 2.10 Self-Refresh Mode Peripheral Architecture The DDR2 memory controller issues autorefresh (REFR) commands to DDR2 SDRAM devices at a ratedefined in the refresh rate (RR) bit field in the SDRAM refresh control register (SDRCR). A refresh intervalcounter is loaded ...

Page 30 - Reset Considerations; memory controller input clocks.; Table 13. Reset Sources; Reset Signal; Figure 15. DDR2 Memory Controller Reset Block Diagram

www.ti.com 2.11 Reset Considerations DDR2 memory controller registers Hard Reset from PLLC1 State machine VRST VCTL_RST DDR PSC Peripheral Architecture Once in self-refresh mode, the DDR2 memory controller input clocks (VCLK and X2_CLK) may be gatedoff or changed in frequency. Stable clocks must be ...

Page 31 - VTP IO Buffer Calibration; Figure 3

www.ti.com 2.12 VTP IO Buffer Calibration 2.13 Auto-Initialization Sequence Peripheral Architecture The DDR2 memory controller is able to control the impedance of the output IO. This feature allows theDDR2 memory controller to tune the output impedance of the IO to match that of the PCB board. Contr...

Page 32 - Initializing Configuration Registers; Table 14. DDR2 SDRAM Configuration by MRS Command; the desired value as well as clearing the DLLPWRDN bit to 0.

www.ti.com 2.13.1 Initializing Configuration Registers Peripheral Architecture Table 14. DDR2 SDRAM Configuration by MRS Command DDR2 MemoryController DDR2 SDRAM Address Bus Value Register Bit DDR2 SDRAM Field Function Selection DDR_A[12] 0 12 Power Down Exit Fast exit DDR_A[11:9] t_WR 11:9 Write Re...

Page 33 - Initializing Following Device Power Up and Device RESET; CAUTION; TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide

www.ti.com 2.13.2 Initializing Following Device Power Up and Device RESET Peripheral Architecture CAUTION The following power-up sequence is preliminary and is documented toreflect the intended-use case. This power-up sequence may change at afuture date. Following device power up, the DDR2 memory co...

Page 34 - Gating input clocks to the module off; Figure 16. DDR2 Memory Controller Power Sleep Controller Diagram

www.ti.com 2.14 Interrupt Support 2.15 DMA Event Support 2.16 Power Management PLLC2 CLKSTOP_REQ DDR PSC CLKSTOP_ACK MODCLK MODRST LRST DDR2 memory controller VCLKSTOP_REQVCLKSTOP_ACK VCLKVRSTVCTL_RST X2_CLK /2 SYSCLK2 PLL2_SYSCLK1 Peripheral Architecture The DDR2 memory controller supports two addr...

Page 35 - DDR2 Memory Controller Clock Stop Procedure; Emulation Considerations

www.ti.com 2.16.1 DDR2 Memory Controller Clock Stop Procedure 2.17 Emulation Considerations Peripheral Architecture CAUTION The following clock stop procedures are preliminary and are documentedto reflect the intended-use cases. These clock stop procedures maychange at a future date. Note: If an acc...

Page 36 - Connecting the DDR2 Memory Controller to DDR2 Memory; Supported Use Cases; displays a

www.ti.com 3 Supported Use Cases 3.1 Connecting the DDR2 Memory Controller to DDR2 Memory 3.2 Configuring Memory-Mapped Registers to Meet DDR2-400 Specification Supported Use Cases The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. Theprogrammability inhere...

Page 38 - Data bus width = 32 bits; Table 16. SDRAM Bank Configuration Register (SDBCR) Configuration; RR = DDR2 clock frequency; Table 17. DDR2 Memory Refresh Specification; Therefore, the following assumes a 133-MHZ DDR2 clock frequency:; Table 18. SDRAM Refresh Control Register (SDRCR) Configuration

www.ti.com 3.2.1 Configuring SDRAM Bank Configuration Register (SDBCR) 3.2.2 Configuring SDRAM Refresh Control Register (SDRCR) Supported Use Cases The SDRAM bank configuration register (SDBCR) contains register fields that configure the DDR2memory controller to match the data bus width, CAS latency...

Page 39 - Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2); and

www.ti.com 3.2.3 Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2) Supported Use Cases The SDRAM timing register (SDTIMR) and SDRAM timing register 2 (SDTIMR2) configure the DDR2memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field inSDTIMR and SDTI...

Page 40 - Configuring DDR PHY Control Register (DDRPHYCR); Register Field Name

www.ti.com 3.2.4 Configuring DDR PHY Control Register (DDRPHYCR) Supported Use Cases The DDR PHY control register (DDRPHYCR) contains a read latency (READLAT) field that helps theDDR2 memory controller determine when to sample read data. The READLAT field should beprogrammed to a value equal to CAS ...

Page 41 - DDR2 Memory Controller Registers; for more information regarding big-endian

www.ti.com 4 DDR2 Memory Controller Registers DDR2 Memory Controller Registers Table 22 lists the memory-mapped registers related to the DDR2 memory controller. See the device-specific data manual for the memory addresses of these registers. The DDR2 memory controller peripheral interfaces to the CP...

Page 42 - The SDRAM status register (SDRSTAT) is shown in; Bit

www.ti.com 4.1 SDRAM Status Register (SDRSTAT) DDR2 Memory Controller Registers The SDRAM status register (SDRSTAT) is shown in Figure 19 and described in Table 25 . Figure 19. SDRAM Status Register (SDRSTAT) 31 30 16 BE Reserved R-x R-4000h 15 3 2 1 0 Reserved PHYRDY Reserved R-0 R-0 R-0 LEGEND: R/...

Page 43 - SDRAM Bank Configuration Register (SDBCR); and described in

www.ti.com 4.2 SDRAM Bank Configuration Register (SDBCR) DDR2 Memory Controller Registers The SDRAM bank configuration register (SDBCR) contains fields that program the DDR2 memorycontroller to meet the specification of the attached DDR2 memory. These fields configure the DDR2memory controller to ma...

Page 45 - Enable and disable MCLK, stopping when in the self-refresh state.

www.ti.com 4.3 SDRAM Refresh Control Register (SDRCR) DDR2 Memory Controller Registers The SDRAM refresh control register (SDRCR) is used to configure the DDR2 memory controller to: • Enter and Exit the self-refresh state. • Enable and disable MCLK, stopping when in the self-refresh state. • Meet th...

Page 47 - Table 29. SDRAM Timing Register 2 (SDTIMR2) Field Descriptions

www.ti.com 4.5 SDRAM Timing Register 2 (SDTIMR2) DDR2 Memory Controller Registers Like the SDRAM timing register (SDTIMR), the SDRAM timing register 2 (SDTIMR2) also configures theDDR2 memory controller to meet the AC timing specification of the DDR2 memory. The SDTIMR2 registeris programmable only ...

Page 48 - Peripheral Bus Burst Priority Register (PBBPR)

www.ti.com 4.6 Peripheral Bus Burst Priority Register (PBBPR) DDR2 Memory Controller Registers The peripheral bus burst priority register (PBBPR) helps prevent command starvation within the DDR2memory controller. To avoid command starvation, the DDR2 memory controller momentarily raises thepriority ...

Page 51 - Table 33. Interrupt Mask Set Register (IMSR) Field Descriptions

www.ti.com 4.9 Interrupt Mask Set Register (IMSR) DDR2 Memory Controller Registers The interrupt mask set register (IMSR) enables the DDR2 memory controller interrupt. The IMSR is shownin Figure 27 and described in Table 33 . Note: If the LTMSET bit in IMSR is set concurrently with the LTMCLR bit in...

Page 52 - Table 34. Interrupt Mask Clear Register (IMCR) Field Descriptions

www.ti.com 4.10 Interrupt Mask Clear Register (IMCR) DDR2 Memory Controller Registers The interrupt mask clear register (IMCR) disables the DDR2 memory controller interrupt. Once an interruptis enabled, it may be disabled by writing a 1 to the IMCR bit. The IMCR is shown in Figure 28 and described i...

Page 53 - Table 35. DDR PHY Control Register (DDRPHYCR) Field Descriptions

www.ti.com 4.11 DDR PHY Control Register (DDRPHYCR) DDR2 Memory Controller Registers The DDR PHY control register (DDRPHYCR) configures the DDR2 memory controller DLL for operationand determines whether the DLL is in reset, whether it is powered up, and the read latency. TheDDRPHYCR is shown in Figu...

Page 54 - Table 36. VTP IO Control Register (VTPIOCR) Field Descriptions

www.ti.com 4.12 VTP IO Control Register (VTPIOCR) DDR2 Memory Controller Registers The VTP IO control register (VTPIOCR) is used to control the calibration of the DDR2 memory controllerIOs with respect to voltage, temperature, and process (VTP). The voltage, temperature, and processinformation is us...

Page 55 - Table 38. DDR VTP Enable Register (DDRVTPER) Field Descriptions

www.ti.com 4.13 DDR VTP Register (DDRVTPR) 4.14 DDR VTP Enable Register (DDRVTPER) DDR2 Memory Controller Registers The DDR VTP register (DDRVTPR) is used in conjunction with the VTP IO control register (VTPIOCR) tocalibrate the output impedance of the DDR2 memory controller IOs with respect to volt...

Page 56 - Appendix A Revision History; Appendix A; Reference

www.ti.com Appendix A Revision History Appendix A Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Additions/Modifications/Deletions Global Changed DDR_CLKO to DDR_CLK in text, figures, and tables. Global Changed DDR_CLKO to...

Page 57 - IMPORTANT NOTICE; Products

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the l...