Texas Instruments TMS320C3x - Manuals

Page 2 - IMPORTANT NOTICE; Copyright

IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue anysemiconductor product or service without notice, and advises its customers to obtain the latestversion of relevant information to verify, before placing orders, that the information being ...

Page 3 - iii; Preface; Read This First; About This Manual; This document uses the following conventions.; of the special; bold version; of the

iii Preface Read This First About This Manual This user’s guide serves as an applications reference book for the TMS320C3xgeneration of digital signal processors (DSPs). These include the TMS320C30,TMS320C31, TMS320LC31, and TMS320C32. Throughout the book, all refer-ences to ’C3x refer collectively ...

Page 4 - LALK

Notational Conventions iv - In syntax descriptions, the instruction, command, or directive is in boldtypeface and parameters are in an italic typeface. Portions of a syntax that are in bold must be entered as shown; portions of a syntax that are in italics describe the type of information that must ...

Page 5 - Information About Cautions; This book contains cautions.; This is an example of a caution statement.; Related Documentation From Texas Instruments; If You; TMS320C3x/C4x Assembly Language Tools User’s Guide (literature

Information About Cautions / Related Documentation from Texas Instruments v Read This First Information About Cautions This book contains cautions. This is an example of a caution statement. A caution statement describes a situation that could potentiallydamage your software or equipment. The inform...

Page 6 - Related Documentation from Texas Instruments / References; TMS320C3x C Source Debugger User’s Guide (literature number; References; General Digital Signal Processing; Digital Signal Processing Design. Salt Lake

Related Documentation from Texas Instruments / References vi TMS320C3x C Source Debugger User’s Guide (literature number SPRU053) tells you how to invoke the ’C3x emulator, evaluation module,and simulator versions of the C source debugger interface. This bookdiscusses various aspects of the debugger...

Page 7 - Speech

References vii Read This First Digital Signal Processing Applications with the TMS320 Family, Vol. III.Texas Instruments, 1990; Prentice-Hall, Inc., 1990. Gold, Bernard, and Rader, C.M. , Digital Processing of Signals. New York, NY: McGraw-Hill Company, Inc., 1969. Hamming, R.W., Digital Filters. En...

Page 8 - Image Processing

References viii Parsons, Thomas., Voice and Speech Processing. New York, NY: McGraw Hill Company, Inc., 1987. Rabiner, Lawrence R., and Schafer, R.W., Digital Processing of Speech Signals. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. Shaughnessy, Douglas., Speech Communication. Reading, MA: Addi...

Page 9 - Array Signal Processing; Array Signal

References ix Read This First - Array Signal Processing Haykin, S., Justice, J.H., Owsley, N.L., Yen, J.L., and Kak, A.C. Array Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1985. Hudson, J.E. Adaptive Array Principles. New York, NY: John Wiley and Sons, 1981. Monzingo, R.A., and Mil...

Page 10 - If You Need Assistance; North America, South America, Central America

If You Need Assistance x If You Need Assistance . . . - World-Wide Web Sites TI Online http://www.ti.com Semiconductor Product Information Center (PIC) http://www.ti.com/sc/docs/pic/home.htm DSP Solutions http://www.ti.com/dsps 320 Hotline On-line t http://www.ti.com/sc/docs/dsps/support.htm Microco...

Page 11 - Documentation; Trademarks; HPGL is registered trademark of Hewlett Packard Company.

If You Need Assistance / Trademarks xi Read This First - Documentation When making suggestions or reporting errors in documentation, please include the following information that is on the titlepage: the full title of the book, the publication date, and the literature number. Mail: Texas Instruments...

Page 12 - Contents; Introduction

Contents xiii Contents 1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A general description of the TMS320C30, TMS320C31, and TMS320C32, their key features,and typical applications. 1.1 TMS32...

Page 13 - CPU Registers

Contents xiv 3 CPU Registers 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of the registers in the CPU register file. 3.1 CPU Multiport Register File 3-2 . . . . . . . . . . . . . . . . . . . . . ...

Page 14 - Addressing Modes

Contents xv Contents 5.3.3 Single-Precision Floating-Point Format 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Extended-Precision Floating-Point Format 5-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 Determining the Decimal Equivalent of a TMS320C...

Page 15 - Pipeline Operation

Contents xvi 7.1.4 RPTS Instruction 7-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.5 Repeat-Mode Restrictions 7-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.6 RC Register Value After Rep...

Page 16 - 0 TMS320C32 Enhanced External Memory Interface

Contents xvii Contents 9 TMS320C30 and TMS320C31 External-Memory Interface 9-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of primary and expansion interfaces for the ’C30 and ’C31; external interface timingdiagrams; programmable wait-states and bank switching. 9.1 Overview 9...

Page 17 - 2 Peripherals

Contents xviii 11.1.3 TMS320C31 Boot-Loading Sequence 11-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.4 TMS320C31 Boot Data Stream Structure 11-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.5 Interrupt and Trap-Vector Mapping 11-11 . . . . . . . . . . . ....

Page 18 - 3 Assembly Language Instructions

Contents xix Contents 12.3.5 TMS320C32 DMA Internal Priority Schemes 12-62 . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.6 CPU and DMA Controller Arbitration 12-63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.7 DMA and Interrupts 12-64 . . . . . . . . . . . . . . . ....

Page 19 - Figures

Figures xx Figures 1–1 TMS320C3x Devices Block Diagram 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 TMS320C30 Block Diagram 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 TMS320C31 Blo...

Page 25 - Tables

Tables xxvi Tables 1–1 TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison 1-5 . . . . . . . . . . . . 1–2 Typical Applications of the TMS320 Family 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Primary CPU Registers 2-9 . . . . . . . . . . . . . . . . ...

Page 27 - Examples

Examples xxviii Examples 4–1 Pipeline Effects of Modifying the Cache Control Bits 4-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Positive Number 5-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 Ne...

Page 29 - CPU Transfer With Serial Port Transmit Polling Method

Examples xxx 12–3 Serial-Port Register Setup #1 12-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 Serial-Port Register Setup #1 12-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5 Seri...

Page 30 - Topic; Typical Applications; Chapter 1

1-1 Introduction The TMS320C3x generation of digital signal processors (DSPs) are high-performance CMOS 32-bit floating-point devices in the TMS320 family ofsingle-chip DSPs. The ’C3x generation integrates both system control and math-intensive functionson a single controller. This system integratio...

Page 32 - Figure 1–1. TMS320C3x Devices Block Diagram; TMS320C3x Key Specifications

TMS320C3x Devices 1-3 Introduction Figure 1–1. TMS320C3x Devices Block Diagram Primary port memory interface Data access 32-bit (’C30-’C31) 8/16/32-bit (’C32) Program access 32-bit (’C30-’C31) 16/32-bit (’C32) RDYHOLDHOLDASTRB (’C30-’C31) R/W D31-0A23-0 STRB0_B3-0 (’C32)STRB1_B3-0 (’C32) IOSTRB (’C3...

Page 36 - Table 1–2. Typical Applications of the TMS320 Family

Typical Applications 1-7 Introduction 1.2 Typical Applications The TMS320 family’s versatility, realtime performance, and multiple functionsoffer flexible design approaches in a variety of applications, which are shownin Table 1–2. Table 1–2. Typical Applications of the TMS320 Family General-Purpose...

Page 37 - Architectural Overview; Chapter 2

2-1 Architectural Overview This chapter provides an architectural overview of the ’C3x processor. It includesa discussion of the CPU, memory interface, boot loader, peripherals, and directmemory access (DMA) of the ’C3x processor. Topic Page 2.1 Overview 2-2 . . . . . . . . . . . . . . . . . . . . ....

Page 38 - Overview

Overview 2-2 2.1 Overview The ’C3x architecture responds to system demands that are based on sophisti-cated arithmetic algorithms that emphasize both hardware and software solu-tions. High performance is achieved through the precision and wide dynamicrange of the floating-point units, large on-chip ...

Page 44 - Arithmetic Logic Unit (ALU) and Internal Buses; Data Formats and Floating-Point; Auxiliary Register Arithmetic Units (ARAUs); Addressing

Central Processing Unit (CPU) 2-8 2.2.1 Floating-Point/Integer Multiplier The multiplier performs single-cycle multiplications on 24-bit integer and 32-bitfloating-point values. The ’C3x implementation of floating-point arithmetic allowsfor floating-point or fixed-point operations at speeds up to 33...

Page 45 - CPU Primary Register File; CPU Registers, for more; Table 2–1. Primary CPU Registers; Assigned Function

CPU Primary Register File 2-9 Architectural Overview 2.3 CPU Primary Register File The ’C3x provides 28 registers in a multiport register file that is tightly coupledto the CPU. Table 2–1 lists the register names and functions. All of the primary registers can be operated upon by the multiplier and ...

Page 46 - Page; Index register 1; Data Formats and

CPU Primary Register File 2-10 Table 2–1. Primary CPU Registers (Continued) Page Section Assigned Function RegisterName IR1 Index register 1 3.1.4 3-4 BK Block-size register 3.1.5 3-4 SP System-stack pointer 3.1.6 3-4 ST Status register 3.1.7 3-5 IE CPU/DMA interrupt-enable regis-ter 3.1.8 3-9 IF CP...

Page 47 - push performs a preincrement a pop performs a postdecre-

CPU Primary Register File 2-11 Architectural Overview The ARAU uses the 32-bit block size register (BK) in circular addressing tospecify the data block size. The system-stack pointer (SP) is a 32-bit register that contains the addressof the top of the system stack. The SP always points to the last e...

Page 48 - Other Registers; The

Other Registers 2-12 2.4 Other Registers The program-counter (PC) is a 32-bit register containing the address of the next instruction to fetch. Although the PC is not part of the CPU register file,it is a register that can be modified by instructions that modify the program flow. The instruction reg...

Page 49 - Memory Organization; 2 bits. Each RAM and ROM block is capable of supporting two CPU

Memory Organization 2-13 Architectural Overview 2.5 Memory Organization The total memory space of the ’C3x is 16M (million) 32-bit words. Program,data, and I/O space are contained within this 16M-word address space, allowingthe storage of tables, coefficients, program code, or data in either RAM orR...

Page 50 - Figure 2–5. Memory Organization of the TMS320C30

Memory Organization 2-14 Figure 2–5. Memory Organization of the TMS320C30 RDY HOLD HOLDA STRB R/W D31–D0 A23–A0 XRDYMSTRBIOSTRBXR/WXD31–XD0XA12–XA0 DMAADDR bus DMADATA bus DADDR2 bus DADDR1 bus DDATA bus PADDR bus PDATA bus Program counter/ instruction register CPU DMA controller 32 24 24 32 24 24 3...

Page 51 - Figure 2–6. Memory Organization of the TMS320C31

Memory Organization 2-15 Architectural Overview Figure 2–6. Memory Organization of the TMS320C31 RDY HOLD HOLDA STRB R/W D31–D0 A23–A0 DMAADDR bus DMADATA bus DADDR2 bus DADDR1 bus DDATA bus PADDR bus PDATA bus Program counter/ instruction register CPU DMA controller 32 24 24 32 24 24 32 32 24 32 24...

Page 52 - Figure 2–7. Memory Organization of the TMS320C32; Memory and the Instruction Cache, for more information.

STRB0_B3/A-1 HOLD HOLDA PRGW R/W D31 – D0 A23 – A0 DMAADDR bus DMADATA bus DADDR2 bus DADDR1 bus DDATA bus PADDR bus PDATA bus Program counter/ instruction register CPU DMA controller 32 24 24 32 24 24 32 32 24 32 24 24 32 24 32 Peripheral bus Multiplexer Multiplexer Cache (64 32) RAM block 0 (256 3...

Page 53 - Memory Addressing Modes; Addressing Modes, for more; Parallel instruction addressing modes:; Indirect. Same as for general addressing mode.; Branch instruction addressing modes:; Register. Same as for general addressing mode.

Memory Organization 2-17 Architectural Overview 2.5.2 Memory Addressing Modes The ’C3x supports a base set of general-purpose instructions as well as arithmetic-intensive instructions that are particularly suited for digital signal processing andother numeric-intensive applications. See Chapter 6, A...

Page 54 - Internal Bus Operation; Program buses: PADDR and PDATA

Internal Bus Operation 2-18 2.6 Internal Bus Operation Much of the ’C3x’s high performance is due to internal busing and parallelism.Separate buses allow for parallel program fetches, data accesses, and DMAaccesses: - Program buses: PADDR and PDATA - Data buses: DADDR1, DADDR2, and DDATA - DMA buses...

Page 55 - External Memory Interface; External Memory Interface, covers external bus operation.

External Memory Interface 2-19 Architectural Overview 2.7 External Memory Interface The ’C30 provides two external interfaces: the primary bus and the expansionbus. The ’C31 provides one external interface: the primary bus. The ’C32 pro-vides one enhanced external interface with three independent mu...

Page 57 - Interrupts

Interrupts 2-21 Architectural Overview 2.8 Interrupts The ’C3x supports four external interrupts (INT3–INT0), a number of internalinterrupts, and a nonmaskable external RESET signal. These can be used tointerrupt either the DMA or the CPU. When the CPU responds to the interrupt,the IACK pin can be u...

Page 58 - Peripherals; Figure 2–9. Peripheral Modules

Peripherals 2-22 2.9 Peripherals All ’C3x peripherals are controlled through memory-mapped registers on a dedi-cated peripheral bus. This peripheral bus is composed of a 32-bit data bus anda 24-bit address bus. This peripheral bus permits straightforward communica-tion to the peripherals. The ’C3x p...

Page 59 - Timers; Peripherals, for more information about timers.; Serial Ports

Peripherals 2-23 Architectural Overview 2.9.1 Timers The two timer modules are general-purpose 32-bit timer/event counters withtwo signaling modes and internal or external clocking. They can signal internallyto the ’C3x or externally to the outside world at specified intervals or they cancount exter...

Page 61 - Figure 2–10. DMA Controller

Direct Memory Access (DMA) 2-25 Architectural Overview Figure 2–10. DMA Controller DMAADDR bus DMADATA bus DMA controller Global-control register Source-address register Destination-address register Transfer-counter register Peripheral address bus Peripheral data bus

Page 63 - Table 2–2. Feature Set Comparison; Feature

TMS320C30, TMS320C31, and TMS320C32 Differences 2-27 Architectural Overview Table 2–2. Feature Set Comparison Feature ’C30 ’C31 ’C32 External bus Two buses: - Primary bus:32-bit data24-bit addressSTRB active for0h–7FFFFFh and80A000h–FFFFFFh - Expansion bus:32-bit data13-bit addressMSTRB active for80...

Page 64 - CPU Multiport Register File; Chapter 3

3-1 CPU Registers The central processing unit (CPU) register file contains 28 registers that canbe operated on by the multiplier and arithmetic logic unit (ALU). Included in theregister file are the auxiliary registers, extended-precision registers, and indexregisters. Three registers in the ’C32 CP...

Page 65 - Table 3–1. CPU Registers; Assigned Function Name

CPU Multiport Register File 3-2 3.1 CPU Multiport Register File The ’C3x provides 28 registers in a multiport register file that is tightly coupled tothe CPU. The program counter (PC) is not included in the 28 registers. All of theseregisters can be operated on by the multiplier and the ALU and can ...

Page 66 - Figure 3–1. Extended-Precision Register Floating-Point Format

CPU Multiport Register File 3-3 CPU Registers The registers also have some special functions for which they are particularlyappropriate. For example, the eight extended-precision registers are especiallysuited for maintaining extended-precision floating-point results. The eight auxiliaryregisters su...

Page 67 - for more information.

CPU Multiport Register File 3-4 3.1.2 Auxiliary Registers (AR7–AR0) The CPU can access the eight 32-bit auxiliary registers (AR7–AR0), and thetwo auxiliary register arithmetic units (ARAUs) can modify them. The primaryfunction of the auxiliary registers is the generation of 24-bit addresses. However...

Page 69 - Table 3–2. Status Register Bits; Bit Name

CPU Multiport Register File 3-6 Table 3–2. Status Register Bits Bit Name Reset Value Name Description C 0 Carry flag Carry condition flag V 0 Overflow flag Overflow condition flag Z 0 Zero flag Zero condition flag N 0 Negative flag Negative condition flag UF 0 Floating-point under-flow flag Floating...

Page 73 - Table 3–3. IE Bits and Functions; Abbreviation

CPU Multiport Register File 3-10 Table 3–3. IE Bits and Functions Abbreviation Reset Value Description EINT0 (CPU) 0 CPU external interrupt 0 enable EINT1 (CPU) 0 CPU external interrupt 1 enable EINT2 (CPU) 0 CPU external interrupt 2 enable EINT3 (CPU) 0 CPU external interrupt 3 enable EXINT0 (CPU) ...

Page 76 - Table 3–4. IF Bits and Functions; Function

CPU Multiport Register File 3-13 CPU Registers Table 3–4. IF Bits and Functions BitName ResetValue Function INT0 0 External interrupt 0 flag INT1 0 External interrupt 1 flag INT2 0 External interrupt 2 flag INT3 0 External interrupt 3 flag XINT0 0 Serial port 0 transmit flag RINT0 0 Serial port 0 re...

Page 77 - Interrupts, on page 7-26 for more information on interrupt

CPU Multiport Register File 3-14 3.1.9.1 Interrupt-Trap Table Pointer (ITTP) Similar to the rest of the ‘C3x device family, the ’C32’s reset vector locationremains at address 0. However, the interrupt and trap vectors are relocatable.This is achieved by the interrupt-trap table pointer (ITTP) bit fi...

Page 78 - Figure 3–11. Interrupt and Trap Vector Locations

CPU Multiport Register File 3-15 CPU Registers Figure 3–11. Interrupt and Trap Vector Locations EA (ITTP) + 3Fh EA (ITTP) + 3Eh EA (ITTP) + 3Dh EA (ITTP) + 3Ch EA (ITTP) + 3Bh EA (ITTP) + 20h TRAP0 EA (ITTP) + 1Fh EA (ITTP) + 0Dh DINT1 EA (ITTP) + 0Ch DINT0 EA (ITTP) + 0Bh TINT1 EA (ITTP) + 0Ah TINT...

Page 79 - Table 3–5. IOF Bits and Functions; Data input on XF0. A write has no effect.

CPU Multiport Register File 3-16 3.1.10 I/O Flag (IOF) Register The I/O flag (IOF) register is shown in Figure 3–12 and controls the functionof the dedicated external pins, XF0 and XF1. These pins can be configured forinput or output. The pins can also be read from and written to. At reset, 0 iswrit...

Page 82 - Reserved Bits and Compatibility

Reserved Bits and Compatibility 3-19 CPU Registers 3.3 Reserved Bits and Compatibility To retain compatibility with future members of the ’C3x family of microprocessors,reserved bits that are read as 0 must be written as 0. You must not modify thecurrent value of a reserved bit that has an undefined...

Page 83 - Memory and the Instruction Cache; 2 bits each (available; Memory; Chapter 4

4-1 Memory and the Instruction Cache The ’C3x provides a total memory space of 16M (million) 32-bit words that containprogram, data, and I/O space. Two RAM blocks of 1K 32 bits each (available on the ’C30 and ’C31) or two RAM blocks of 256 32 bits (available on the ’C32) and a ROM block of 4K 32 bit...

Page 84 - RAM blocks 0 and 1 are each 1K; Memory Maps; Microprocessor Mode

Memory 4-2 4.1 Memory The ’C3x accesses a total memory space of 16M (million) 32-bit words of pro-gram, data, and I/O space and allows tables, coefficients, program code, ordata to be stored in either RAM or ROM. In this way, you can maximize memoryusage and allocate memory space as desired. RAM blo...

Page 85 - Microcomputer Mode; Peripheral Bus Memory Map, on page 4-9 describes the peripheral

Memory 4-3 Memory and the Instruction Cache - Microcomputer Mode In microcomputer mode, the 4K on-chip ROM is mapped into locations0h–0FFFh. There are 192 locations (0h–0BFh) within this block for interruptvectors, trap vectors, and a reserved space (’C30). Locations 1000h–7FFFFFh are accessed over ...

Page 87 - branches (see Figure 4–2 on page

Memory 4-5 Memory and the Instruction Cache 4.1.1.2 TMS320C31 Memory Map The memory map depends on whether the processor is running in micropro-cessor mode (MCBL/MP = 0) or microcomputer mode (MCBL/MP = 1). Thememory maps for these modes are similar (see Figure 4–2 on page 4-6).Locations 800000h–807...

Page 91 - Peripheral Bus Memory Map; TMS320C30 Peripheral Bus Memory Map

Memory 4-9 Memory and the Instruction Cache 4.1.2 Peripheral Bus Memory Map The following sections describe the peripherial bus memory maps for the ’C30,’C31, and ’C32. 4.1.2.1 TMS320C30 Peripheral Bus Memory Map The ’C30 memory-mapped peripheral registers are located starting at address808000h. Fig...

Page 92 - Figure 4–4. TMS320C30 Peripheral Bus Memory-Mapped Registers

Memory 4-10 Figure 4–4. TMS320C30 Peripheral Bus Memory-Mapped Registers Serial port 1 data transmit 808064h Primary-bus control 808060h Expansion-bus control 80804Ch Serial port 0 data receive 808048h Serial port 0 data transmit FSR/DR/CLKR serial port 0 control 808046h Serial port 0 R/X timer peri...

Page 93 - TMS320C31 Peripheral Bus Memory Map; Figure 4–5. TMS320C31 Peripheral Bus Memory-Mapped Registers

Memory 4-11 Memory and the Instruction Cache 4.1.2.2 TMS320C31 Peripheral Bus Memory Map The ’C31 memory-mapped peripheral registers are located starting at address808000h. Figure 4–5 shows the peripheral bus memory map. The shadedblocks are reserved. Figure 4–5. TMS320C31 Peripheral Bus Memory-Mapp...

Page 94 - TMS320C32 Peripheral Bus Memory Map

Memory 4-12 4.1.2.3 TMS320C32 Peripheral Bus Memory Map The ’C32’s memory-mapped peripheral and external-bus control registers arelocated starting at address 808000h, as shown in Figure 4–6 on page 4-13. Theshaded blocks are reserved.

Page 95 - Figure 4–6. TMS320C32 Peripheral Bus Memory-Mapped Registers

Memory 4-13 Memory and the Instruction Cache Figure 4–6. TMS320C32 Peripheral Bus Memory-Mapped Registers 8097FFh 808068h STRB1 bus control 808064h STRB0 bus control 808060h IOSTRB bus control 80804Ch Serial port data receive 808048h Serial port data transmit FSR/DR/CLKR serial port control 808046h ...

Page 96 - ’C30 and ’C31 Microprocessor and Microcomputer Modes; branch instructions to; ’C32 Microprocessor and Microcomputer/Boot-Loader Mode

Reset/Interrupt/Trap Vector Map 4-14 4.2 Reset/Interrupt/Trap Vector Map The addresses for the reset, interrupt, and trap vectors are 00h–3Fh, as shownin Figure 4–7 and Figure 4–8. The reset vector contains the address of the resetroutine. - ’C30 and ’C31 Microprocessor and Microcomputer Modes In th...

Page 97 - Traps 28–31 are reserved do not use them.

Reset/Interrupt/Trap Vector Map 4-15 Memory and the Instruction Cache Figure 4–7. Reset, Interrupt, and Trap Vector Locations for the TMS320C30 Microprocessor Mode RESET 00h INT0 01h INT1 02h INT2 03h INT3 04h XINT0 05h RINT0 06h XINT1 07h RINT1 08h TINT0 09h TINT1 0Ah DINT 0Bh 0Ch 1Fh TRAP 0 20h D ...

Page 100 - Figure 4–10. Interrupt and Trap Vector Locations for TMS320C32

Reset/Interrupt/Trap Vector Map 4-18 Figure 4–10. Interrupt and Trap Vector Locations for TMS320C32 EA (ITTP) + 3Fh EA (ITTP) + 3Eh EA (ITTP) + 3Dh EA (ITTP) + 3Ch EA (ITTP) + 3Bh EA (ITTP) + 20h TRAP0 EA (ITTP) + 1Fh EA (ITTP) + 0Dh DINT1 EA (ITTP) + 0Ch DINT0 EA (ITTP) + 0Bh TINT1 EA (ITTP) + 0Ah ...

Page 101 - Instruction Cache; Instruction-Cache Architecture; P = 1: the word is already present in cache memory; Figure 4–11. Address Partitioning for Cache Control Algorithm

Instruction Cache 4-19 Memory and the Instruction Cache 4.3 Instruction Cache A 64 × 32-bit instruction cache speeds instruction fetches and lowers system cost by caching program fetches from external memory. The instruction cacheallows the use of slow, external memories while still achieving single...

Page 102 - Figure 4–12. Instruction-Cache Architecture

Instruction Cache 4-20 Figure 4–12. Instruction-Cache Architecture Segment start address registers Segment words LRU Stack SSA register 0 Segment word 0 Segment word 1 Segment word 30 Segment word 31 Segment word 0 Segment word 1 Segment word 30 Segment word 31 MRU segment number LRU segment number ...

Page 103 - Instruction-Cache Algorithm; cache hit or a cache miss.

Instruction Cache 4-21 Memory and the Instruction Cache 4.3.2 Instruction-Cache Algorithm When the ’C3x requests an instruction word from external memory, one of twopossible actions occurs: a cache hit or a cache miss. - Cache Hit. The cache contains the requested instruction, and the followingactio...

Page 104 - Using Self-Modifying Code; align directive when coding assembly; Cache Control Bits; Three cache control bits are located in the CPU status register:

Instruction Cache 4-22 Only instructions may be fetched from the program cache. All reads and writesof data in memory bypass the cache. Program fetches from internal memorydo not modify the cache and do not generate cache hits or misses. The pro-gram cache is a single-access memory block. Dummy prog...

Page 105 - Table 4–1. Combined Effect of the CE and CF Bits

Instructions may be fetched beforecache is enabledor frozen. Cache cleared Instructions may be fetched beforecache cleared. Instruction Cache 4-23 Memory and the Instruction Cache Table 4–1. Combined Effect of the CE and CF Bits CE CF Effect 0 0 Cache not enabled 0 1 Cache not enabled 1 0 Cache enab...

Page 106 - Data Formats and Floating-Point Operation; Chapter 5

5-1 Data Formats and Floating-Point Operation In the ’C3x architecture, data is organized into three fundamental types: integer,unsigned integer, and floating-point. The terms integer and signed integer areequivalent. The ’C3x supports short and single-precision formats for signed andunsigned intege...

Page 107 - Integer Formats; si; Single-Precision Integer Format; integer format, is – 2; Figure 5–2. Single-Precision Integer Format

Integer Formats 5-2 5.1 Integer Formats The ’C3x supports two integer formats: a 16-bit short-integer format and a32-bit single-precision integer format. Note: When extended-precision registers are used as integer operands, only bits31–0 are used; bits 39–32 remain unchanged. 5.1.1 Short-Integer For...

Page 108 - Unsigned-Integer Formats; Short Unsigned-Integer Format; Figure 5–3. Short Unsigned-Integer Format and Zero Fill; sp

Unsigned-Integer Formats 5-3 Data Formats and Floating-Point Operation 5.2 Unsigned-Integer Formats The ’C3x supports two unsigned-integer formats: a 16-bit short format and a32-bit single-precision format. Note: In extended-precision registers, the unsigned-integer operands use only bits31– 0; bits...

Page 109 - Floating-Point Formats; Figure 5–5. General Floating-Point Format

Floating-Point Formats 5-4 5.3 Floating-Point Formats The ’C3x supports four floating-point formats: - A short floating-point format for immediate floating-point operands, consistingof a 4-bit exponent, a sign bit, and an 11-bit fraction - (’C32 only) A short floating-point format for use with 16-bi...

Page 110 - Short Floating-Point Format

Floating-Point Formats 5-5 Data Formats and Floating-Point Operation The exponent field is a 2s-complement number that determines the factor of 2by which the number is multiplied. Essentially, the exponent field shifts thebinary point in the mantissa. If the exponent is positive, then the binary poi...

Page 111 - TMS320C32 Short Floating-Point Format for External 16-Bit Data; in the short floating-point format is given by:

Floating-Point Formats 5-6 The following examples illustrate the range and precision of the short floating-point format: Most positive: x = (2 – 2 –11 ) × 2 7 = 2.5594 × 10 2 Least positive: x = 1 × 2 –7 = 7.8125 × 10 –3 Least negative: x = (–1– 2 –11 ) × 2 –7 = –7.8163 × 10 –3 Most negative: x = –2...

Page 113 - x is given by

Floating-Point Formats 5-8 You must use the following reserved values to represent 0 in the single-precisionfloating-point format: e = – 128s = 0f = 0 The following examples illustrate the range and precision of the single-precisionfloating-point format: Most positive: x = (2 – 2 – 23 ) × 2 127 = 3....

Page 114 - Step 1: Convert the exponent field to its decimal representation.; Rewrite the mantissa as:; Mantissa; If the sign bit is set (; Fraction

Floating-Point Formats 5-9 Data Formats and Floating-Point Operation The following examples illustrate the range and precision of the extended-precision floating-point format: Most positive: x = (2 – 2 – 23 ) × 2 127 = 3.4028234 × 10 38 Least positive: x = 1 × 2 –127 = 5.8774717541 × 10 38 Least neg...

Page 115 - and the; Example 5–1. Positive Number

Floating-Point Formats 5-10 Rewrite the mantissa as: Mantissa 1 0 . 1 0 1 0 0 0 0 0 0 0 0 Step 3: Shift the decimal point of the mantissa according to the value of the exponent. If the exponent is positive, shift the binary point to the right by the valueof the exponent. If the exponent is negative,...

Page 116 - Example 5–2. Negative Number

Floating-Point Formats 5-11 Data Formats and Floating-Point Operation Example 5–2. Negative Number 0 1 C 0 0 0 0 0 Hex value 0000 0001 1100 0000 0000 0000 0000 0000 Binary value Exponent = 0000 0001 2 = 1 Sign = 1 Fraction = .10000 2 Value = 10.1 2 × 2 1 = 101 2 . = –3 Fraction Implied Sign Example ...

Page 117 - Conversion Between Floating-Point Formats; Floating-Point Format

Floating-Point Formats 5-12 5.3.6 Conversion Between Floating-Point Formats Floating-point operations assume several different formats for inputs and out-puts. These formats often require conversion from one floating-point format toanother (for example, short floating-point format to extended-precis...

Page 118 - to Extended-Precision Floating-Point Format; The 8 LSBs of the mantissa field are filled with 0s.; to Single-Precision Floating-Point Format; The 8 LSBs of the mantissa field are truncated.

Floating-Point Formats 5-13 Data Formats and Floating-Point Operation Figure 5–12. Converting from Single-Precision Floating-Point Format to Extended-Precision Floating-Point Format Single-precision floating-point format Extended-precision floating-point format 0 y x x y y y x x 31 24 23 22 0 39 32 ...

Page 120 - Differentiating Symbols for IEEE and TMS320C3x Formats; If these values are present

Floating-Point Conversion (IEEE Std. 754) 5-15 Data Formats and Floating-Point Operation Figure 5–15. TMS320C3x Single-Precision 2s-Complement Floating-Point Format e f 31 23 22 0 24 s Note: Same format as for the ’C4x In comparison, Figure 5–15 shows the the ‘C3x 2s-complement floating-pointformat....

Page 122 - are not treated and, if present, will give erroneous results.

Floating-Point Conversion (IEEE Std. 754) 5-17 Data Formats and Floating-Point Operation 5.4.1.1 IEEE-to-TMS320C3x Floating-Point Format Conversion Example 5–4 shows the fast conversion from IEEE to ’C3x floating-point format.It properly handles the general case when 0 < e < 255, and also hand...

Page 126 - This conversion is performed according to the following table:; FFh; Case 1 maps a 2s-complement 0 to a positive IEEE 0.

Floating-Point Conversion (IEEE Std. 754) 5-21 Data Formats and Floating-Point Operation 5.4.2 Converting 2s-Complement TMS320C3x Floating-Point Format to IEEE Format This conversion is performed according to the following table: Table 5–2. Converting 2s-Complement Floating-Point Format to IEEE Form...

Page 131 - Floating-Point Multiplication

Floating-Point Multiplication 5-26 5.5 Floating-Point Multiplication A floating-point number α can be written in floating-point format as in the following formula, where α ( man) is the mantissa and α ( exp) is the exponent: α = α ( man) × 2 α ( exp) The product of α and b is c, defined as: c = α × ...

Page 132 - If

Floating-Point Multiplication 5-27 Data Formats and Floating-Point Operation - If c(exp) has overflowed (step 11) in the positive direction, then step 14 sets c(exp) to the most positive extended-precision format value. If c(exp) has overflowed in the negative direction, then step 14 sets c(exp) to ...

Page 133 - Figure 5–16. Flowchart for Floating-Point Multiplication

Floating-Point Multiplication 5-28 Figure 5–16. Flowchart for Floating-Point Multiplication α ( man) b(man) α ( exp) b(exp) (1) (2) Multiply mantissas Add exponents c(man) = α ( man) x b(man) (50-bit result) c(exp) = α ( exp) + b(exp) Put c(man) in extended pre- cision floating-point format Test for...

Page 134 - and

Floating-Point Multiplication 5-29 Data Formats and Floating-Point Operation Example 5–8 through Example 5–12 illustrate how floating-point multiplicationis performed on the ’C3x. For these examples, the implied most significantnonsign bit is made explicit. Example 5–8. Floating-Point Multiply (Both...

Page 136 - Example 5–12. Floating-Point Multiply by 0; All multiplications by a floating-point 0 yield a result of 0 (

Floating-Point Multiplication 5-31 Data Formats and Floating-Point Operation Example 5–11. Floating-Point Multiply Between Positive and Negative Numbers Let: α = 1.0 x 2 α ( exp) = 01.00000000000000000000000 x 2 α ( exp) b = –2.0 x 2 b( exp) = 10.00000000000000000000000 x 2 b( exp) Then: 01.00000000...

Page 137 - Floating-Point Addition and Subtraction

Floating-Point Addition and Subtraction 5-32 5.6 Floating-Point Addition and Subtraction In floating-point addition and subtraction, two floating-point numbers α and b can be defined as: α = α ( man) × 2 α ( exp) b = b(man) × 2 b( exp) The sum (or difference) of α and b can be defined as: c = α ± b ...

Page 138 - Figure 5–17. Flowchart for Floating-Point Addition

Floating-Point Addition and Subtraction 5-33 Data Formats and Floating-Point Operation Figure 5–17. Flowchart for Floating-Point Addition α ( man) b(man) α ( exp) b(exp) (3) (2) Align mantissas Subtract exponents α ( man) = α ( man) > > d Discard LSBs to keep α ( man) in extended- precision fl...

Page 139 - In the case of two normalized numbers to be summed, let

Floating-Point Addition and Subtraction 5-34 The following examples describe the floating-point addition and subtractionoperations. It is assumed that the data is in the extended-precision floating-point format. Example 5–13. Floating-Point Addition In the case of two normalized numbers to be summed...

Page 140 - Example 5–14. Floating-Point Subtraction; A subtraction is performed in this example. Let:

Floating-Point Addition and Subtraction 5-35 Data Formats and Floating-Point Operation Example 5–14. Floating-Point Subtraction A subtraction is performed in this example. Let: α = 01.0000000000000000000000000000001 × 2 0 b = 01.0000000000000000000000000000000 × 2 0 The operation performed is α – b....

Page 142 - Normalization Using the NORM Instruction; Example 5–17. NORM Instruction; Assume that an extended-precision register contains the value:

Normalization Using the NORM Instruction 5-37 Data Formats and Floating-Point Operation 5.7 Normalization Using the NORM Instruction The NORM instruction normalizes an extended-precision floating-point numberthat is assumed to be unnormalized (see Example 5–17). Since the number isassumed to be unno...

Page 143 - Figure 5–18. Flowchart for NORM Instruction Operation

Normalization Using the NORM Instruction 5-38 Figure 5–18. Flowchart for NORM Instruction Operation Test for special cases of c (man) c(exp) = –128 (1) α ( man) = 0 Test for special cases of c (exp) (6) c (exp) underflow (7) c (exp) in range c (exp) = –128No change to c (man) Set c to final result c...

Page 144 - tion is performed first.

Rounding (RND Instruction) 5-39 Data Formats and Floating-Point Operation 5.8 Rounding (RND Instruction) The RND instruction rounds a number from the extended-precision floating-point format to the single-precision floating-point format. Rounding is similar tofloating-point addition. Given the numbe...

Page 146 - does not overflow if

Floating-Point to Integer Conversion (FIX Instruction) 5-41 Data Formats and Floating-Point Operation 5.9 Floating-Point to Integer Conversion (FIX Instruction) Using the FIX instruction, you can convert an extended-precision floating-point number to a single-precision integer in a single cycle. The...

Page 149 - Fast Logarithms on a Floating-Point Device

Fast Logarithms on a Floating-Point Device 5-44 5.11 Fast Logarithms on a Floating-Point Device The following TMS320C30/C40 function calculates the log base two of a numberin about half the time of conventional algorithms. Furthermore, the method caneasily be scaled for faster execution if less accu...

Page 150 - Exp

Fast Logarithms on a Floating-Point Device 5-45 Data Formats and Floating-Point Operation N * log2(mant_old) = EXP_new + log2(mant_new) log2(mant_old) = EXP_new/N + log2(mant_new)/N This last equation shows that the logarithm of mant_old is indeed related toEXP_new. And as shown earlier, EXP_new can...

Page 151 - Mant; Figure 5–22. Tabulated Values for Mantissa; The fractional part is the same at the endpoints.

Fast Logarithms on a Floating-Point Device 5-46 are equivalent to the seven MSBs of the logarithm. If the exponent could holdall the bits needed for full accuracy, then it would be possible to continue the op-eration for all 24 bits of the mantissa. Since there are only eight bits in the expo-nent a...

Page 153 - Figure 5–23. Fast Logarithm for FFT Displays; MPYF

Fast Logarithms on a Floating-Point Device 5-48 Figure 5–23. Fast Logarithm for FFT Displays **************************************************************** ** FAST Logarithm for FFT displays ** >>>> NEED ONLY ADD ONE INSTRUCTION IN MANY CASES <<<< **************************...

Page 154 - Chapter 6

6-1 Addressing Modes The ’C3x supports five groups of powerful addressing modes. Six types ofaddressing that allow data access from memory, registers, and the instructionword can be used within the groups. This chapter describes the operation,encoding, and implementation of the addressing modes. It ...

Page 155 - Addressing Types; Register addressing . A CPU register contains the operand.

Addressing Types 6-2 6.1 Addressing Types You can access data from memory, registers, and the instruction word by usingfive types of addressing: - Register addressing . A CPU register contains the operand. - Direct addressing . The data address is formed by concatenating theeight least significant b...

Page 156 - Register Addressing; Table 6–1. CPU Register Address/Assembler Syntax and Function; Register Name

Register Addressing 6-3 Addressing Modes 6.2 Register Addressing In register addressing, a CPU register contains the operand, as shown in thisexample: ABSF R1 ; R1 = |R1| The syntax for the CPU registers, the assembler syntax, and the assignedfunction for those registers are listed in Table 6–1. Tab...

Page 157 - Direct Addressing; address = DP concatenated with expr; Figure 6–1. Direct Addressing; Before Instruction

Direct Addressing 6-4 6.3 Direct Addressing In direct addressing, the data address is formed by the concatenation of theeight LSBs of the data-page pointer (DP) with the 16 LSBs of the instructionword (expr). This results in 256 pages (64K words per page), allowing you toaccess a large address space...

Page 158 - Indirect Addressing; Example 6–2. Auxiliary Register Indirect; An auxiliary register (AR

Indirect Addressing 6-5 Addressing Modes 6.4 Indirect Addressing Indirect addressing specifies the address of an operand in memory through thecontents of an auxiliary register, optional displacements, and index registers asshown in Example 6–2. Only the 24 LSBs of the auxiliary registers and indexre...

Page 159 - Figure 6–2. Indirect Addressing Operand Encoding; Auxiliary Register; The auxiliary register (AR

Indirect Addressing 6-6 Figure 6–2. Indirect Addressing Operand Encoding LSB MSB 5 bits mod ARn disp 3 bits 0, 5, or 8 bits Note: Auxiliary Register The auxiliary register (AR n) is encoded in the instruction word according to its binary representation n (for example, AR3 is encoded as 11 2 ), not i...

Page 160 - Table 6–2. Indirect Addressing

Indirect Addressing 6-7 Addressing Modes Table 6–2. Indirect Addressing (a) Indirect addressing with displacement Mod Field Syntax Operation Description 00000 *+AR n(disp) addr = AR n + disp With predisplacement add 00001 *– AR n(disp) addr = AR n – disp With predisplacement subtract 00010 *++AR n(d...

Page 162 - Example 6–3. Indirect Addressing With Predisplacement Add; contained in the instruction word or an implied value of 1.; Example 6–4. Indirect Addressing With Predisplacement Subtract; n – disp

Indirect Addressing 6-9 Addressing Modes Example 6–3. Indirect Addressing With Predisplacement Add The address of the operand to fetch is the sum of an auxiliary register (AR n) and the displacement ( disp). The displacement is either an 8-bit unsigned integer contained in the instruction word or an...

Page 163 - operand address = AR

Indirect Addressing 6-10 Example 6–5. Indirect Addressing With Predisplacement Add and Modify The address of the operand to fetch is the sum of an auxiliary register (AR n) and the displacement ( disp). The displacement is either an 8-bit unsigned integer contained in the instruction word or an impl...

Page 164 - After the operand is fetched, the displacement (

Indirect Addressing 6-11 Addressing Modes Example 6–7. Indirect Addressing With Postdisplacement Add and Modify The address of the operand to fetch is the contents of an auxiliary register (AR n). After the operand is fetched, the displacement ( disp) is added to the auxiliary register. The displace...

Page 166 - Example 6–11. Indirect Addressing With Preindex Add; if; Example 6–12. Indirect Addressing With Preindex Subtract; n – IRm

Indirect Addressing 6-13 Addressing Modes Example 6–11. Indirect Addressing With Preindex Add The address of the operand to fetch is the sum of an auxiliary register (AR n) and an index register (IR0 or IR1). Operation: operand address = AR n + IRm Assembler Syntax: *+ AR n(IRm) Modification Field: ...

Page 167 - Example 6–13. Indirect Addressing With Preindex Add and Modify

Indirect Addressing 6-14 Example 6–13. Indirect Addressing With Preindex Add and Modify The address of the operand to fetch is the sum of an auxiliary register (AR n) and an index register (IR0 or IR1). After the data is fetched, the auxiliary register isupdated with the generated address. Operation...

Page 168 - Example 6–15. Indirect Addressing With Postindex Add and Modify; to the auxiliary register.

Indirect Addressing 6-15 Addressing Modes Example 6–15. Indirect Addressing With Postindex Add and Modify The address of the operand to fetch is the contents of an auxiliary register(AR n). After the operand is fetched, the index register (IR0 or IR1) is added to the auxiliary register. Operation: o...

Page 171 - Immediate Addressing; expr; PC

Immediate Addressing 6-18 6.5 Immediate Addressing In immediate addressing, the operand is a 16-bit (short) or 24-bit (long) immediatevalue contained in the 16 or 24 LSBs of the instruction word (expr). Dependingon the data types assumed for the instruction, the short-immediate operand canbe a 2s-co...

Page 172 - PC-Relative Addressing; src (a label or address) specified by the user and generates; BU

PC-Relative Addressing 6-19 Addressing Modes 6.6 PC-Relative Addressing Program counter (PC)-relative addressing is used for branching. It adds thecontents of the 16 or 24 LSBs of the instruction word to the PC register. Theassembler takes the src (a label or address) specified by the user and gener...

Page 174 - Circular Addressing

Circular Addressing 6-21 Addressing Modes 6.7 Circular Addressing Many DSP algorithms, such as convolution and correlation, require a circularbuffer in memory. In convolution and correlation, the circular buffer acts as asliding window that contains the most recent data to process. As new data isbro...

Page 175 - Example 6–23. Examples of Formula; Length of Buffer

Circular Addressing 6-22 Figure 6–6. Logical and Physical Representation of Circular Buffer after Writing Eight Values Start End a) Logical representation value6 value7 value2 value6 value2 value7 b) Physical representation value5 value3 value4 value3 value4 value5 Start End To implement a circular ...

Page 176 - Figure 6–7. Circular Buffer Implementation

Circular Addressing 6-23 Addressing Modes In circular addressing, index refers to the K LSBs (from the K-bit boundary criteria) of the auxiliary register selected, and step is the quantity being added to or subtracted from the auxiliary register. Follow these two rules when you use cir-cular address...

Page 177 - Example 6–24. Circular Addressing; Figure 6–8. Data Structure for FIR Filters

Circular Addressing 6-24 Example 6–24. Circular Addressing *AR0 ++ (5)% ; AR0 = 0 (0 value) *AR0 ++ (2)% ; AR0 = 5 (1st value) *AR0 – – (3)% ; AR0 = 1 (2nd value) *AR0++(6)% ; AR0 = 4 (3rd value) *AR0 – – % ; AR0 = 4 (4th value) *AR0 ; AR0 = 3 (5th value) Element 0 Element 1 Element 2 Element 3 Elem...

Page 178 - Example 6–25. FIR Filter Code Using Circular Addressing

Circular Addressing 6-25 Addressing Modes Example 6–25. FIR Filter Code Using Circular Addressing * Impulse Response .sect ”Impulse_Resp” H .float 1.0.float 0.99.float 0.95....float 0.1 * Input Buffer X .usect ”Input_Buf”,128 .data HADDR .word H XADDR .word X N .word 128 * Initialization * LDP HADDR...

Page 179 - Bit-Reversed Addressing; Size of the buffer/table must be less than or equal to 64K (16 bits)

Bit-Reversed Addressing 6-26 6.8 Bit-Reversed Addressing The ’C3x can implement fast Fourier transforms (FFT) with bit-reversed ad-dressing. Whenever data in increasing sequence order is transformed by anFFT, the resulting data is presented in bit-reversed order. To recover this datain the correct o...

Page 180 - Table 6–3. Index Steps and Bit-Reversed Addressing; Step

Bit-Reversed Addressing 6-27 Addressing Modes Example 6–26. Bit-Reversed Addressing *AR2++(IR0)B ; AR2 = 0110 0000 (0th value) *AR2++(IR0)B ; AR2 = 0110 1000 (1st value) *AR2++(IR0)B ; AR2 = 0110 0100 (2nd value) *AR2++(IR0)B ; AR2 = 0110 1100 (3rd value) *AR2++(IR0)B ; AR2 = 0110 0010 (4th value) *...

Page 181 - Aligning Buffers With the TMS320 Floating-Point DSP Assembly

Aligning Buffers With the TMS320 Floating-Point DSP Assembly 6-28 6.9 Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language Tools To align buffers to a K-bit boundary, you can use the .sect or .usect assemblydirectives to define a section in conjunction with the align memory allocati...

Page 182 - System and User Stack Management; Stack; Figure 6–9. System Stack Configuration

System and User Stack Management 6-29 Addressing Modes 6.10 System and User Stack Management The ’C3x provides a dedicated system-stack pointer (SP) for building stacksin memory. The auxiliary registers can also be used to build a variety of moregeneral linear lists. This section discusses the imple...

Page 183 - System and User Stack Management

System and User Stack Management 6-30 6.10.2 Stacks Stacks can be built from low to high memory or high to low memory. Two casesfor each type of stack are shown. Stacks can be built using the preincrement/decrement and postincrement/decrement modes of modifying the auxiliaryregisters (AR). Stack gro...

Page 185 - Program Flow Control; Chapter 7

7-1 Program Flow Control The TMS320C3x provides a complete set of constructs that facilitate softwareand hardware control of the program flow. Software control includes repeats,branches, calls, traps, and returns. Hardware control includes reset operation,interrupts, and power management. You can se...

Page 186 - Repeat Modes; Register; RS; RE

Repeat Modes 7-2 7.1 Repeat Modes The repeat modes of the ’C3x can implement zero-overhead looping. For manyalgorithms, most execution time is spent in an inner kernel of code. Using therepeat modes allows these time-critical sections of code to be executed in theshortest possible time. The ’C3x pro...

Page 187 - Repeat-Mode Control Bits; Two bits are important to the operation of RPTB and RPTS:; Repeat-Mode Operation; Maximum Number of Repeats; ) The maximum number of repeats occurs when RC = 8000 0000h. This

Repeat Modes 7-3 Program Flow Control 7.1.1 Repeat-Mode Control Bits Two bits are important to the operation of RPTB and RPTS: - RM bit. The repeat-mode (RM) flag bit in the status register specifieswhether the processor is running in the repeat mode. J RM = 0: Fetches are not made in repeat mode. J...

Page 188 - Example 7–1. Repeat-Mode Control Algorithm; RPTB Instruction; The number of times to repeat the block is the RC (repeat; Example 7–2. RPTB Operation

Repeat Modes 7-4 Example 7–1. Repeat-Mode Control Algorithm if RM == 1 ; If in repeat mode (RPTB or RPTS) if S == 1 ; If RPTS if first time through ; If this is the first fetch fetch instruction from memory ; Fetch instruction from memory else ; If not the first fetch fetch instruction from IR ; Fet...

Page 189 - RPTS Instruction

Repeat Modes 7-5 Program Flow Control All block repeats initiated by RPTB can be interrupted. When RPTB src (source) instruction executes, it performs the following sequence: 1) Load the start address of the block into repeat-start-address register (RS). This is the next address following the instru...

Page 190 - Repeat-Mode Restrictions; size 1) cannot be a B; Example 7–3. Incorrectly Placed Standard Branch

Repeat Modes 7-6 The RPTS instruction loads all registers and mode bits necessary for the opera-tion of the single-instruction repeat mode. Step 1 loads the start address of theblock into RS. Step 2 loads the end address into the RE (end address of theblock). Since this is a repeat of a single instr...

Page 191 - Example 7–4. Incorrectly Placed Delayed Branch; RC Register Value After Repeat Mode Completes; Number of Repetitions; Example 7–5. Pipeline Conflict in an RPTB Instruction

Repeat Modes 7-7 Program Flow Control Example 7–4. Incorrectly Placed Delayed Branch LDI 15,RC ; Load repeat counter with 15 RPTB ENDLOOP ; Execute block of code STLOOP ; from STLOOP to ENDLOOP 16; times ...BRD OOPS ; This branch violates rule 2 ADDFMPYF ENDLOOP SUBF 7.1.6 RC Register Value After Re...

Page 192 - Nested Block Repeats; Saving/Restoring Registers in Correct Order

Repeat Modes 7-8 7.1.7 Nested Block Repeats Block repeats (RPTB) can be nested. Since the registers RS, RE, RC, andST control the repeat-mode status, these registers must be saved and restoredin order to nest block repeats. For example, if you write an interrupt service routinethat requires the use ...

Page 193 - Delayed Branches; Incorrect Use of Delayed Branches

Delayed Branches 7-9 Program Flow Control 7.2 Delayed Branches The ’C3x offers three main types of branching: standard, delayed, and condi-tional delayed. Standard branches empty the pipeline before performing the branch, ensuringcorrect management of the program counter and resulting in a ’C3x bran...

Page 194 - Example 7–6. Incorrectly Placed Delayed Branches

Delayed Branches 7-10 Example 7–6. Incorrectly Placed Delayed Branches B1: BD L1 NOPNOP B2: B L2 ; This branch is incorrectly placed. NOPNOPNOP... For faster execution, it might still be advantageous to use a delayed branchfollowed by NOP instructions by trading increased program size for fasterspee...

Page 195 - RETS

Calls, Traps, and Returns 7-11 Program Flow Control 7.3 Calls, Traps, and Returns Calls and traps provide a means of executing a subroutine or function whileproviding a return to the calling routine. The CALL, CALL cond, and TRAPcond instructions store the value of the PC on the stack before changin...

Page 196 - RETI; that RETI; Figure 7–1. CALL Response Timing

Calls, Traps, and Returns 7-12 - RETI cond returns from traps or calls like the RETScond, with the addition that RETI cond also sets the GIE bit of the status register, which enables all interrupts whose enabling bit is set to 1. The conditions for RETI cond are the same as for the CALL cond instruc...

Page 197 - Interlocked Operations; Table 7–2. Interlocked Operations; Mnemonic

Interlocked Operations 7-13 Program Flow Control 7.4 Interlocked Operations One of the most common parallel processing configurations is the sharing ofglobal memory by multiple processors. For multiple processors to access thisglobal memory and share data in a coherent manner, some sort of arbitrati...

Page 198 - Timing Diagrams for LDFI and LDII; int

Interlocked Operations 7-14 The LDFI and LDII instructions perform the following actions: 1) Simultaneously set XF0 to 0 and begin a read cycle. The timing of XF0 is similar to that of the address bus during a read cycle. 2) Execute an LDF or LDI instruction and extend the read cycle until XF1 is se...

Page 199 - Timing Diagrams for SIGI; Interrupting Interlocked Operations; or; Using Interlocked Operations; Incorrect Use of Interlock Instructions; STFI

Interlocked Operations 7-15 Program Flow Control Note: Timing Diagrams for SIGI The timing diagrams for SIGI shown in the data sheets depict a zero waitstate condition. Since the device idles until one cycle after XF1 is signaled,the data sheets show the XF1 signal sampled one H1/H3 cycle before set...

Page 200 - Example 7–9 shows how a location COUNT may contain a; Example 7–9. Multiprocessor Counter Manipulation

Interlocked Operations 7-16 Example 7–8 shows the implementation of a busy-waiting loop. If locationLOCK is the interlock for a critical section of code, and a nonzero means thelock is busy, the algorithm for a busy-waiting loop can be used as shown. Example 7–8. Busy-Waiting Loop LDI 1,R0 ; Put 1 i...

Page 201 - Figure 7–2. Multiple TMS320C3xs Sharing Global Memory; else S – 1

Interlocked Operations 7-17 Program Flow Control Figure 7–2. Multiple TMS320C3xs Sharing Global Memory Global memory Arbitration logic ’C3x #2 XF0 XF1 Local memory Local memory ’C3x #1 XF0 XF1 (X)A (X)D CTRL (X)A (X)D CTRL Lock, count, or S ADDR CTRL DA T A Sometimes it may be necessary for several ...

Page 202 - Figure 7–3. Zero-Logic Interconnect of TMS320C3x Devices

Interlocked Operations 7-18 The ’C3x code for V(S) is shown in Example 7–10; code for P(S) is shown inExample 7–11. Compare the code in Example 7–11 to the code in Example 7–9,which does not use semaphores. Example 7–10. Implementation of V(S) V: LDII @S,R0 ; Interlocked read of S begins (XFO = 0); ...

Page 203 - Pipeline Effects of Interlocked Instructions

Interlocked Operations 7-19 Program Flow Control Example 7–12. Code to Synchronize Two TMS320C3x Devices at the Software Level N Code for ’C3x #2 Code for ’C3x #1 Time O (WAIT) SIGI SIGI Synchronization occurs 7.4.3 Pipeline Effects of Interlocked Instructions Before performing an interlocked instru...

Page 204 - Example 7–13. Pipeline Delay of XF Pin Configuration

XF0 set as anoutput pin andXF1 set as aninput pin XF1 sampled XF0 driven lowand XF1 sampled XF0 pindriven high XF1 pinsampled XF0 pindriven low Interlocked Operations 7-20 Example 7–13. Pipeline Delay of XF Pin Configuration Pipeline Operation PC Fetch Decode Read Execute n LDI 2h, IOF n+1 NOP LDI 2...

Page 205 - Reset Operation; Table 7–3. TMS320C3x Pin Operation at Reset; Device

Reset Operation 7-21 Program Flow Control 7.5 Reset Operation The ’C3x supports a nonmaskable external reset signal (RESET), which isused to perform system reset. This section discusses the reset operation. At start-up, the state of the ’C3x processor is undefined. You can use the RESETsignal to pla...

Page 209 - ’C30 and ’C31 External-Memory

Reset Operation 7-25 Program Flow Control At system reset, the following additional operations are performed: - The peripherals are reset. This is a synchronous operation. Peripheral resetis described in Chapter 12, Peripherals. - The external bus control registers are reset. The reset values of the...

Page 212 - Microcomputer Boot Mode

Interrupts 7-28 Table 7–5. Reset, Interrupt, and Trap-Branch Locations for the TMS320C31 Microcomputer Boot Mode Address Name Function 809FC1 INT0 External reset signal input 809FC2 INT1 External interrupt on the INT0 pin 809FC3 INT2 External interrupt on the INT1 pin 809FC4 INT3 External interrupt ...

Page 214 - Table 7–6. Interrupt and Trap-Vector Locations for the TMS320C32

Interrupts 7-30 Table 7–6. Interrupt and Trap-Vector Locations for the TMS320C32 Address Name Function EA[ITTP] + 00h Reserved EA[ITTP] + 01h INT0 External interrupt on the INT0 pin EA[ITTP] + 02h INT1 External interrupt on the INT1 pin EA[ITTP] + 03h INT2 External interrupt on the INT2 pin EA[ITTP]...

Page 215 - Interrupt Prioritization; Table 7–7. Reset and Interrupt Vector Priorities; Priority

Interrupts 7-31 Program Flow Control 7.6.3 Interrupt Prioritization When two interrupts occur in the same clock cycle or when two previouslyreceived interrupts are waiting to be serviced, one interrupt is serviced beforethe other. The CPU handles this prioritization by servicing the interrupt with t...

Page 216 - CPU Interrupt Control Bits; n is still low when the interrupt acknowledge

Interrupts 7-32 7.6.4 CPU Interrupt Control Bits Three CPU registers contain bits that control interrupt operation: - Status (ST) register The CPU global interrupt-enable bit (GIE) located in the CPU status register(ST) controls all maskable CPU interrupts. When this bit is set to 1, the CPUresponds...

Page 217 - Figure 7–5. IF Register Modification; Correct; IF Register Load Priority; Interrupt Processing; For a CPU interrupt to occur, at least two conditions must be met:

Interrupts 7-33 Program Flow Control Figure 7–5. IF Register Modification Correct Incorrect LDI @MASK, R0 LDI IF, R1 AND R0, IF AND @MASK, R1 LDI R1, IF Note: IF Register Load Priority If a load of the IF register occurs simultaneously with a set or reset of a flagby an interrupt pulse, the loading ...

Page 218 - Figure 7–6. CPU Interrupt Processing; CPU and DMA Interrupts

Interrupts 7-34 Figure 7–6. CPU Interrupt Processing DMA proceeds according to SYNC bits If enabled,interrupt is a DMA interrupt Clear interrupt flag DMA continues CPU starts executing ISR routine Complete all fetched instructions PC ← interrupt vector PC → *(++SP) Clear interrupt flag Disable inter...

Page 219 - CPU Interrupt Latency

Interrupts 7-35 Program Flow Control If you wish to make the interrupt service routine interruptible, you can set theGIE bit to 1 after entering the ISR. The interrupt acknowledge (IACK) instruction can be used to signal externally thatan interrupt has been serviced. If external memory is specified ...

Page 220 - Table 7–8. Interrupt Latency; External Interrupts

Interrupts 7-36 Table 7–8. Interrupt Latency Cycle Description Fetch Decode Read Execute 1 Recognize interrupt in single-cycle fetched(prog a + 1) instruction prog a + 1 prog a prog a–1 prog a–2 2 Clear GIE bit. Clear interrupt flag — interrupt prog a prog a–1 3 Read the interrupt vector table — — i...

Page 221 - Figure 7–7. Interrupt Logic Functional Diagram

Interrupts 7-37 Program Flow Control Figure 7–7. Interrupt Logic Functional Diagram INTn Tocontrolsection Internal interrupt set signal Interrupt flag (n) Internal interrupt processor Internal interrupt clear/acknowledge signal EINTn(DMA) EINTn(CPU) H1 H3 H1 D CLK D CLK D CLK Set RESET GIE(CPU) Q Q ...

Page 222 - DMA Interrupts; in START bits. DMA reset clears the interrupt internal latch.; DMA Interrupt Control Bits; a description of the IE.

DMA Interrupts 7-38 7.7 DMA Interrupts Interrupts can also trigger DMA read and write operations. This is calledDMA synchronization. The DMA interrupt processing cycle is similar to that ofthe CPU. After the pertinent interrupt flag is cleared, the DMA coprocessorproceeds according to the status of ...

Page 223 - DMA Interrupt Processing; Figure 7–8. DMA Interrupt Processing

DMA Interrupts 7-39 Program Flow Control 7.7.2 DMA Interrupt Processing Figure 7–8 shows the general flow of interrupt processing by the DMA coprocessor. Figure 7–8. DMA Interrupt Processing DMA proceeds according to DMA control register SYNC bits Is an enabled interrupt set ? If enabled in the IE r...

Page 224 - Figure 7–9. Parallel CPU and DMA Interrupt Processing

DMA Interrupts 7-40 7.7.3 CPU/DMA Interaction If the DMA is not using interrupts for synchronization of transfers, it is notaffected by the processing of the CPU interrupts. Detected interrupts areresponded to by the CPU and DMA on instruction fetch boundaries only.Since instruction fetches are halt...

Page 225 - TMS320C3x Interrupt Considerations; read and decode phases in the pipeline. However,

DMA Interrupts 7-41 Program Flow Control 7.7.4 TMS320C3x Interrupt Considerations Give careful consideration to ’C3x interrupts, especially if you make modificationsto the status register when the global interrupt-enable (GIE) bit is set. This canresult in the GIE bit being erroneously set or reset ...

Page 227 - Use the following to reset the GIE:; Example 7–15. Pending Interrupt

DMA Interrupts 7-43 Program Flow Control One solution is to use an instruction that is uninterruptible such as RPTS asfollows to set the GIE: RPTS 0 AND 2000h, ST ; Set GIE=1 Use the following to reset the GIE: RPTS 0 AND 0DFFFh, ST ; Set GIE=0 Another alternative incorporates the following code fra...

Page 228 - TMS320C30 Interrupt Considerations

DMA Interrupts 7-44 7.7.5 TMS320C30 Interrupt Considerations The ’C30 silicon revisions earlier than 4.0 have two unique exceptions to theinterrupt operation. This does not apply to ’C30 silicon revision 4.0 or greater,any ’C31 silicon, or any ’C32 silicon. On ’C30 silicon revisions earlier than 4.0...

Page 229 - Insert two NOP instructions immediately before the TRAP

DMA Interrupts 7-45 Program Flow Control Insert two NOP instructions immediately before the TRAP cond instruction. One NOP is insufficient in some cases, as illustrated in the second bulleteditem, above. This eliminates the opportunity for any pipeline conflicts in theimmediately preceding instructi...

Page 231 - Traps; Initialization of Traps and Interrupts; Traps and interrupts are triggered differently in the ’C3x:; Traps are always triggered by a software mechanism, by the TRAP; cond; Operation of Traps; Figure 7–10. Flow of Traps

Traps 7-47 Program Flow Control 7.8 Traps A trap is the equivalent of a software-triggered interrupt. In the ’C3x, traps andinterrupts are treated identically, except in the way in which they are triggered. 7.8.1 Initialization of Traps and Interrupts Traps and interrupts are triggered differently i...

Page 232 - The RETI; cond provides a return from a trap or interrupt.

Traps 7-48 The RETI cond instruction manipulates the status flags as shown in block (3) in Figure 7–10. RETI cond provides a return from a trap or interrupt. The ’C3x supports 32 different traps. When a TRAP cond n instruction is executed, the ’C3x jumps to the address stored in the memory location ...

Page 233 - Power Management Modes; IDLE2 Power-Down Mode

Power Management Modes 7-49 Program Flow Control 7.9 Power Management Modes The following ’C3x devices have been enhanced by the addition of two power-down modes: IDLE2 and LOPOWER: - ’C30 silicon version 7.0 or greater - ’LC31 - ’C31 silicon revision 5.0 or greater - ’C32 7.9.1 IDLE2 Power-Down Mod...

Page 234 - Delayed Branch; Idle 2 execution

Power Management Modes 7-50 - The interrupt service routine (ISR) must have been set up before placingthe device in IDLE2 mode, because the instruction following the IDLE2instruction is not executed until the RETI (return from interrupt) instructionis executed. - When the device is in emulation mode...

Page 235 - Figure 7–12. Interrupt Response Timing After IDLE2 Operation; LOPOWER

Power Management Modes 7-51 Program Flow Control Figure 7–12. Interrupt Response Timing After IDLE2 Operation 1st address Vector address Data ADDR INT0 Flag INT3 to INT0 INT3 to H1 H3 Fetch first instruction of service routing Interrupt vector read Clocks driven CLKIN 7.9.2 LOPOWER In the LOPOWER (l...

Page 236 - Figure 7–13. LOPOWER Timing; Figure 7–14. MAXSPEED Timing; CLKIN

Power Management Modes 7-52 Figure 7–13. LOPOWER Timing 32 CLKIN H1 H3 CLKIN LOPOWER read Figure 7–14. MAXSPEED Timing H1 H3 CLKIN MAXSPEED read 32 CLKIN

Page 237 - Pipeline Structure; Chapter 8

8-1 Pipeline Operation Pipeline Operation Two characteristics of the’C3x that contribute to its high performance are: - Pipelining - Concurrent I/O and CPU operation The following four functional units control ’C3x operation: - Fetch - Decode - Read - Execute Pipelining is the overlapping or paralle...

Page 238 - n registers in the indirect; CYCLE

Perfectoverlap Pipeline Structure 8-2 8.1 Pipeline Structure The following list describes the four major units of the ‘C3x pipeline structure andtheir functions: Fetch unit (F) Fetches the instruction words from memoryand updates the program counter (PC). Decode unit (D) Decodes the instruction word...

Page 240 - Pipeline Conflicts; Branch conflicts; Branch Conflicts; Dummy Fetch

Pipeline Conflicts 8-4 8.2 Pipeline Conflicts Pipeline conflicts in the ’C3x can be grouped into the following categories: Branch conflicts Branch conflicts involve most of those instructions oroperations that read and/or modify the PC. Register conflicts Register conflicts involve delays that can o...

Page 241 - Example 8–1. Standard Branch

3 PC Fetch held for new PC value Pipeline Conflicts 8-5 Pipeline Operation Example 8–1. Standard Branch BR THREE ; Unconditional branch MPYF ; Not executed ADD ; Not executed SUBF ; Not executed AND ; Not executed ...THREE OR ; Fetched after BR is taken STI ... Pipeline Operation PC Fetch Decode Rea...

Page 242 - Example 8–2. Delayed Branch; Register Conflicts; The registers comprise the following three functional groups:; Group 1; If an instruction writes to one of these three groups,

Noexecutedelay 3 PC Pipeline Conflicts 8-6 Example 8–2. Delayed Branch BRD THREE ; Unconditional delayed branch MPYF ; Executed ADD ; Executed SUBF ; Executed AND ; Not executed ... THREE MPYF ; Fetched after SUBF is fetched ... Pipeline Operation PC Fetch Decode Read Execute n BRD — — — n+1 MPYF BR...

Page 243 - Example 8–3. Write to an AR Followed by an AR for Address Generation; LDI

Decode/addressgeneration helduntil AR write iscompleted ARs written Pipeline Conflicts 8-7 Pipeline Operation is loaded, and a different auxiliary register is used on the next instruction. Sincethe decode stage needs the result of the write to the auxiliary register, thedecode of this second instruc...

Page 244 - Example 8–4. A Read of ARs Followed by ARs for Address Generation; ADDI; Memory Conflicts; Memory Access for Maximum Performance,

Decode/addressgeneration helduntil AR is read ARs read Pipeline Conflicts 8-8 In Example 8–4, two auxiliary registers are added together, with the result goingto an extended-precision register. The next instruction uses a different auxiliaryregister as an address register. Example 8–4. A Read of ARs...

Page 245 - Memory pipeline conflicts consist of the following four types:; Program wait; A program fetch is prevented from beginning.; Program fetch Incomplete A program fetch has begun but is not yet; Two conditions can prevent the program fetch from beginning:

Pipeline Conflicts 8-9 Pipeline Operation Memory pipeline conflicts consist of the following four types: Program wait A program fetch is prevented from beginning. Program fetch Incomplete A program fetch has begun but is not yet complete. Execute only An instruction sequence requires three CPUdata a...

Page 246 - Example 8–5. Program Wait Until CPU Data Access Completes

Fetch helduntil dataaccesscompletes Data accessed Pipeline Conflicts 8-10 Example 8–5. Program Wait Until CPU Data Access Completes ADDF3 *AR0,*AR1,R0FIXMPYFADDF3NEGB Pipeline Operation PC Fetch Decode Read Execute n ADDF3 — — — n+1 FIX ADDF3 — — n+2 (wait) FIX ADDF3 — n+2 MPYF (nop) FIX ADDF3 n+3 A...

Page 247 - Example 8–6. Program Wait Due to Multicycle Access; Program Fetch Incomplete

2-cycle DMA access Pipeline Conflicts 8-11 Pipeline Operation Example 8–6. Program Wait Due to Multicycle Access ADDF ; code in internal memory MPY ; code in internal memory SUBF ; code in internal memory CALL ; code in external memory Pipeline Operation PC Fetch Decode Read Execute n ADDF — — — n+1...

Page 248 - Example 8–7. Multicycle Program Memory Fetches; Execute Only

1 wait state required Pipeline Conflicts 8-12 Example 8–7. Multicycle Program Memory Fetches Pipeline Operation PC Fetch Decode Read Execute n MPYF — — — n+1 ADDF MPYF — — n+2 RDY SUBF ADDF MPYF — n+2 RDY SUBF (nop) ADDF MPYF n+3 ADDI SUBF (nop) ADDF Note: PC = program counter 8.2.3.3 Execute Only T...

Page 249 - Example 8–8. Single Store Followed by Two Reads; STF R

Write mustcompletebefore thetwo reads cancomplete 2 readsperformed Pipeline Conflicts 8-13 Pipeline Operation Example 8–8. Single Store Followed by Two Reads STF R 0,*AR1 ; R0 → *AR1 LDF *AR2,R1 ; *AR2 → R1 in parallel with  LDF *AR3,R2 ; *AR3 → R2 Pipeline Operation PC Fetch Decode Read Execute n...

Page 250 - Example 8–9. Parallel Store Followed by Single Read; STF

Read must wait until the writes arecompleted Writes performed Pipeline Conflicts 8-14 Example 8–9 shows a parallel store followed by a single load or read. Sincetwo parallel stores are required, the next CPU data-memory read must waitone cycle before beginning. One program-memory refetch can occur. ...

Page 251 - Example 8–10. Interlocked Load; NOT; Hold Everything; An external load takes more than one cycle.

XF1 = 1,read must wait XF1 = 0,read operationis complete Pipeline Conflicts 8-15 Pipeline Operation Example 8–10. Interlocked Load NOT R1,R0 LDII 300h,AR 2ADDI *AR2,R2 CMPI R0,R2 Pipeline Operation PC XF1 Fetch Decode Read Execute n 1 NOT — — — n+1 1 LDII NOT — — n+2 1 ADDI LDII NOT — n+3 1 CMPI ADD...

Page 252 - write access; Example 8–11. Busy External Port

write access 2-cycle external bus Pipeline Conflicts 8-16 Example 8–11. Busy External Port STF R0,@DMA1 LDF @DMA2,R0 Pipeline Operation PC Fetch Decode Read Execute n STF — — — n+1 LDF STF — — n+2 W LDF STF — n+2 W LDF (nop) STF n+2 W LDF (nop) (nop) n+3 X W LDF (nop) n+4 Y X W LDF Note: W, X, Y = I...

Page 253 - read access; Example 8–12. Multicycle Data Reads; LDF

2-cycle external bus read access Pipeline Conflicts 8-17 Pipeline Operation Example 8–12. Multicycle Data Reads LDF @DMA,R0 Pipeline Operation PC Fetch Decode Read Execute n LDF — — — n+1 I LDF — — n+2 J I LDF — n+3 K(dummy) I LDF — n+3 K 2 J I LDF Note: I, J, K = Instruction representations The fin...

Page 254 - Example 8–13. Conditional Calls and Traps

PC store cycle Pipeline Conflicts 8-18 Example 8–13. Conditional Calls and Traps Pipeline Operation PC Fetch Decode Read Execute n CALL cond — — — n+1 I CALL cond — — n+1 (nop) (nop) CALL cond — n+1 (nop) (nop) (nop) CALL cond n+1 (nop) (nop) (nop) CALL cond n+2/CALLaddr I (nop) (nop) (nop) Note: I ...

Page 255 - Resolving Register Conflicts; Generation

ARs read Resolving Register Conflicts 8-19 Pipeline Operation 8.3 Resolving Register Conflicts If the auxiliary registers (AR7–AR0), the index registers (IR1–IR0), data-pagepointer (DP), or stack pointer (SP) are accessed for any reason other thanaddress generation, pipeline conflicts associated wit...

Page 256 - Pipeline Conflict

AR2 read AR2 written Resolving Register Conflicts 8-20 Example 8–15. Write to an AR Followed by an AR for Address Generation Without a Pipeline Conflict LDI @TABLE,AR2 MPYF @VALUE,R1 ADDF R2,R1 MPYF *AR2++,R1 SUBFSTF Pipeline Operation PC Fetch Decode Read Execute n LDI — — — n+1 MYPF LDI — — n+2 AD...

Page 257 - LDP

DP read DP written Resolving Register Conflicts 8-21 Pipeline Operation Example 8–16. Write to DP Followed by a Direct Memory Read Without a Pipeline Conflict LDP TABLE_ADDR POP R0 LDF *–AR3(2),R1 LDI @TABLE_ADDR,AR0 PUSHF R6PUSH R4 Pipeline Operation PC Fetch Decode Read Execute n LDP — — — n+1 POP...

Page 258 - Memory Access for Maximum Performance

Memory Access for Maximum Performance 8-22 8.4 Memory Access for Maximum Performance If program fetches and data accesses are performed so that the resourcesbeing used cannot provide the necessary bandwidth, the pipeline is stalleduntil the data accesses are complete. Certain configurations of progr...

Page 260 - Clocking Memory Accesses; Figure 8–2. Minor Clock Periods; Program Fetches; Four types of instructions perform loads, memory reads, and stores:

Clocking Memory Accesses 8-24 8.5 Clocking Memory Accesses This section discusses the role of internal clock phases (H1 and H3) and howthe ’C3x handles multiple-memory accesses. The previous section discussesthe interaction between sequences of instructions; this section discusses theflow of data on...

Page 261 - -Operand Instruction Memory Accesses; In the case of a data store, bits 15–0 represent the; -Operand Instruction Memory Reads; src1 and src2, come from either registers; If only one of the source operands is from memory (either

Clocking Memory Accesses 8-25 Pipeline Operation See Chapter 6, Addressing Modes, for more information. As discussed in Chapter 7, the number of bus cycles for external memoryaccesses differs in some cases from the number of CPU execution cycles. Forexternal reads, the number of bus cycles and CPU e...

Page 263 - Example 8–17. Dummy sr2 Read; STI

2-cycle dummy load of src2 R0, *AR6 until the store is complete actual read of src2 and src1 Clocking Memory Accesses 8-27 Pipeline Operation Example 8–17. Dummy sr2 Read STI R0,*AR6 ; AR6 points to MSTRB space ADDI3 *AR1,*AR3,R0 ; AR3 points to on-chip RAM ( src1) ; AR1 points to MSTRB space ( src2...

Page 264 - Example 8–18. Operand Swapping Alternative

2-cycle store The read of src2 cannot start until the store is complete 2-cycle read of src1 and src2 Clocking Memory Accesses 8-28 Example 8–18. Operand Swapping Alternative Switch the operands of the 3-operand instruction so that the internal read isperformed first. STI R0,*AR6 ; AR6 points to MST...

Page 265 - Operations with Parallel Stores; Figure 8–5. Multiply or CPU Operation With a Parallel Store

Clocking Memory Accesses 8-29 Pipeline Operation 8.5.2.3 Operations with Parallel Stores The next class of instructions includes every instruction that has a store in parallelwith another instruction. Bits 31 and 30 for these instructions are equal to 1 1. The instruction word format for operations ...

Page 266 - Parallel Multiplies and Adds; Figure 8–7. Parallel Multiplies and Adds

Clocking Memory Accesses 8-30 - If dst1 and dst2 are both written to external memory, a single CPU cycle is still all that is necessary to complete the stores. In this case, four buscycles are required. 1) In the first cycle, both dst1 and dst2 are written to the port, and the ex- ternal-bus access ...

Page 267 - External-Memory Interface; Enhanced External-Memory Interface, for detailed information on; Chapter 9

9-1 TMS320C30 and TMS320C31 External-Memory Interface This chapter describes the ’C30 and ’C31 external-memory interface. SeeChapter 10, Enhanced External-Memory Interface, for detailed information on the ’C32 external bus operation. Memories and external peripheral devices are accessible through tw...

Page 269 - Memory Interface Signals; TMS320C30 Memory Interface Signals; The TMS320C30 has two sets of control signals as follows:; TMS320C31 Memory Interface Signals; The TMS320C31 has one set of control signals:

Memory Interface Signals 9-3 TMS320C30 and TMS320C31 External-Memory Interface 9.2 Memory Interface Signals This section describes the differences between the ’C30 and ’C31 memoryinterface signals. 9.2.1 TMS320C30 Memory Interface Signals The TMS320C30 has two sets of control signals as follows: - P...

Page 270 - Table 9–1. Primary Bus Interface Signals

Memory Interface Signals 9-4 Table 9–1. Primary Bus Interface Signals Signal Type † Description Value After Reset Idle Status STRB O/Z Primary interface access strobe 1 1 R/W O/Z Specifies memory read (active high) or write(active low) mode 1 1 HOLD I Hold external memory interface NA ‡ Ignored HOLD...

Page 271 - Table 9–2. Expansion Bus Interface Signals

Memory Interface Signals 9-5 TMS320C30 and TMS320C31 External-Memory Interface Table 9–2. Expansion Bus Interface Signals Signal Type † Description Value After Reset Idle Status MSTRB O/Z Expansion bus memory access strobe 1 1 IOSTRB O/Z Expansion bus peripheral-access strobe 1 1 XR/W O/Z Specifies ...

Page 272 - Figure 9–1. Memory-Mapped External Interface Control Registers

Memory Interface Signals 9-6 Figure 9–1. Memory-Mapped External Interface Control Registers Expansion-bus control (’C30 only) 808060h 808061h 808062h 808063h 808064h 808065h 808066h 808067h 808068h 808069h 80806Ah 80806Bh 80806Ch 80806Dh 80806Fh Reserved Reserved Reserved Reserved Reserved Reserved ...

Page 273 - Memory Interface Control Registers; Primary-Bus Control Register

Memory Interface Control Registers 9-7 TMS320C30 and TMS320C31 External-Memory Interface 9.3 Memory Interface Control Registers Two memory interface control registers, the primary-bus control register andthe expansion-bus control register, are described in this section. 9.3.1 Primary-Bus Control Reg...

Page 274 - Table 9–3. Primary-Bus Control Register Bits

Memory Interface Control Registers 9-8 Table 9–3. Primary-Bus Control Register Bits Abbreviation Reset Value Name Description HOLDST 0 Hold status bit This bit signals whether the port is beingheld (HOLDST = 1) or is not being held(HOLDST = 0). This status bit is validwhether the port has been held ...

Page 275 - Expansion-Bus Control Register; Figure 9–3. Expansion-Bus Control Register; SWW

Memory Interface Control Registers 9-9 TMS320C30 and TMS320C31 External-Memory Interface 9.3.2 Expansion-Bus Control Register The expansion-bus control register is a 32-bit register that contains control bitsfor the expansion bus (see Figure 9–3 and Table 9–4). Figure 9–3. Expansion-Bus Control Regi...

Page 276 - Programmable Wait States

Programmable Wait States 9-10 9.4 Programmable Wait States The ’C3x has its own internal software-configurable ready-generation capabilityfor each strobe. This software wait-state generator is controlled by configuringtwo bit fields in the primary or expansion bus interface control registers. Use th...

Page 277 - Inputs; Wait until external RDY is signaled

Programmable Wait States 9-11 TMS320C30 and TMS320C31 External-Memory Interface Table 9–5. Wait-State Generation Inputs Output SWW Bit Field /RDYext /RDYwtcnt /RDYint Functional Description 00 0 1 x x 0 1 Wait until external RDY is signaled 01 x x 0 1 0 1 Wait until internal wait state generatorcoun...

Page 278 - Programmable Bank Switching; sizes from 2; Figure 9–4. BNKCMP Example; Table 9–6. BNKCMP and Bank Size; BNKCMP; None

Programmable Bank Switching 9-12 9.5 Programmable Bank Switching Programmable bank switching allows you to switch between external memorybanks without having to insert wait states externally due to memories that requireseveral cycles to turn off. Bank switching is implemented on the primary bus only...

Page 281 - External Memory Interface Timing; Posted Write

External Memory Interface Timing 9-15 TMS320C30 and TMS320C31 External-Memory Interface 9.6 External Memory Interface Timing This section discusses functional timing of operations on the primary bus and theexpansion bus, the two independent parallel buses or the ’C3x devices. The parallel buses impl...

Page 287 - Figure 9–10. Read and Write for IOSTRB = 0

External Memory Interface Timing 9-21 TMS320C30 and TMS320C31 External-Memory Interface 9.6.2 Expansion-Bus I/O Cycles In contrast to primary bus and MSTRB cycles, IOSTRB reads and writes areboth two cycles in duration (with no wait states) and exhibit the same timing.During these cycles, address al...

Page 288 - Figure 9–11. Read With One Wait State for IOSTRB = 0

External Memory Interface Timing 9-22 Figure 9–11 illustrates a read with one wait state when IOSTRB is active, andFigure 9–12 illustrates a write with one wait state when IOSTRB is active. Foreach wait state added, IOSTRB, XR/W, and XA are extended one clock cycle.Writes hold the data on the bus on...

Page 289 - Figure 9–12. Write With One Wait State for IOSTRB = 0

External Memory Interface Timing 9-23 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–12. Write With One Wait State for IOSTRB = 0 H3 H1 XA XD XR/W IOSTRB XRDY Write data Extracycle

Page 290 - Figure 9–13. Memory Read and I/O Write for Expansion Bus

External Memory Interface Timing 9-24 Figure 9–13 through Figure 9–23 illustrate the various transitions betweenmemory reads and writes, and I/O writes over the expansion bus. Figure 9–13. Memory Read and I/O Write for Expansion Bus H3 H1 XA XD XR/W IOSTRB MSTRB XRDY Memory address I/O address Read ...

Page 291 - Figure 9–14. Memory Read and I/O Read for Expansion Bus

External Memory Interface Timing 9-25 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–14. Memory Read and I/O Read for Expansion Bus XRDY XD XA XR/W IOSTRB MSTRB H1 H3 I/O read Read I/O address Memory address

Page 292 - Figure 9–15. Memory Write and I/O Write for Expansion Bus

External Memory Interface Timing 9-26 Figure 9–15. Memory Write and I/O Write for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR/W Memory address I/O address I/O write Memory write

Page 293 - Figure 9–16. Memory Write and I/O Read for Expansion Bus

External Memory Interface Timing 9-27 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–16. Memory Write and I/O Read for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR/W Memory address I/O address I/O read Memory write

Page 294 - Figure 9–17. I/O Write and Memory Write for Expansion Bus

External Memory Interface Timing 9-28 Figure 9–17. I/O Write and Memory Write for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR/W I/O address Memory address I/O write Memory write

Page 295 - Figure 9–18. I/O Write and Memory Read for Expansion Bus

External Memory Interface Timing 9-29 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–18. I/O Write and Memory Read for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR/W I/O address Memory address I/O write Read

Page 296 - Figure 9–19. I/O Read and Memory Write for Expansion Bus

External Memory Interface Timing 9-30 Figure 9–19. I/O Read and Memory Write for Expansion Bus I/O address Memory address Memory write XRDY XD XA XR/W IOSTRB MSTRB H1 H3 I/O read

Page 297 - Figure 9–20. I/O Read and Memory Read for Expansion Bus

External Memory Interface Timing 9-31 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–20. I/O Read and Memory Read for Expansion Bus Memory address I/O address XRDY XD XA XR/W IOSTRB MSTRB H1 H3 Read I/O read

Page 301 - Figure 9–24. Inactive Bus States for IOSTRB

External Memory Interface Timing 9-35 TMS320C30 and TMS320C31 External-Memory Interface Figure 9–24 and Figure 9–25 illustrate the signal states when a bus is inactive(after an IOSTRB or (M)STRB access, respectively). The strobes (STRB,MSTRB and IOSTRB) and (X)R/W) go to 1. The address is driven wit...

Page 302 - Figure 9–25. Inactive Bus States for STRB and MSTRB

External Memory Interface Timing 9-36 Figure 9–25. Inactive Bus States for STRB and MSTRB H3 H1 (X)A (X)D (X)R/W (M)STRB (X)RDY Write data (X)RDY ignored Bus inactive

Page 303 - Hold Cycles; Figure 9–26. HOLD and HOLDA Timing

External Memory Interface Timing 9-37 TMS320C30 and TMS320C31 External-Memory Interface 9.6.3 Hold Cycles Figure 9–26 illustrates the timing for HOLD and HOLDA. HOLD is an externalasynchronous input. There is a minimum of one cycle delay from the time whenthe processor recognizes HOLD = 0 until HOLD...

Page 304 - Programmable Wait States

10-1 TMS320C32 Enhanced External Memory Interface The ’C32 external memory interface provides greater flexibility by improvingthe ’C3x core with several new features. This chapter describes these featuresand enhancements in detail. Topic Page 10.1 TMS320C32 Memory Features 10-2 . . . . . . . . . . ....

Page 306 - TMS320C32 Enhanced External Memory Interface; External Memory Interface Overview

TMS320C32 Memory Overview 10-3 TMS320C32 Enhanced External Memory Interface 10.2 TMS320C32 Memory Overview The following sections describe examples, control register setups, andrestrictions necessary to fully understand the operation and functionality of theexternal memory interface. 10.2.1 External...

Page 307 - Figure 10–1. Memory Address Spaces

TMS320C32 Memory Overview 10-4 IOSTRB can access 32-bit data from 32-bit wide memory. It does not have theflexibility of STRB0 and STRB1 since it is composed of a single signal:IOSTRB. IOSTRB bus cycles are different from those of STRB0 and STRB1and are discussed in Section 10.10. This timing differ...

Page 308 - Figure 10–2. Status Register

TMS320C32 Memory Overview 10-5 TMS320C32 Enhanced External Memory Interface The PRGW status bit field of the CPU status (ST) register reflects the settingof the PRGW pin. Figure 10–2 depicts all the bit fields of the CPU status (ST)register. Figure 10–2. Status Register Á Á ÁÁÁ ÁÁÁ 31–16 ÁÁÁ ÁÁÁ 15 ...

Page 309 - ’C32 Short Floating-Point Format for

TMS320C32 Memory Overview 10-6 10.2.3.2 16- or 32-Bit Floating-Point Data Types The ’C32 supports 16- or 32-bit floating point data. For 16-bit floating-pointreads, the eight MSBs are the signed exponent and the eight LSBs are thesigned mantissa (see Section 5.3.2, ’C32 Short Floating-Point Format f...

Page 310 - with; External Interface Control Registers; Figure 10–3. Memory-Mapped External Interface Control Registers

Configuration 10-7 TMS320C32 Enhanced External Memory Interface 10.3 Configuration To access 8-, 16-, or 32-bit data (types) from 8-, 16-, or 32-bit wide memory, thememory interface of the ’C32 device uses either strobe STRB0 or STRB1 with four pins each. These pins serve as byte-enable and/or addit...

Page 311 - STRB0 Control Register; Figure 10–4. STRB0 Control Register; STRB1 Control Register; Figure 10–5. STRB1 Control Register

Configuration 10-8 10.3.1.1 STRB0 Control Register The STRB0 control register (Figure 10–4) is a 32-bit register that contains thecontrol bits for the portion of the external bus memory space that is mapped toSTRB0. The following table lists the register bits with the bit names and functions.At the ...

Page 312 - IOSTRB Control Register; Figure 10–6. IOSTRB Control Register

Configuration 10-9 TMS320C32 Enhanced External Memory Interface The instruction immediately preceding a change in the data-size ormemory-width bit fields should not perform a multicycle store. Donot follow a change in the data-size or memory-width bit fields witha store instruction. Also, do not per...

Page 316 - Figure 10–7. STRB Configuration; are connected to the

Configuration 10-13 TMS320C32 Enhanced External Memory Interface Figure 10–7. STRB Configuration STRB0_Bx STRB1_Bx STRB0_Bx STRB config STRB1_Bx 10.3.2 Using Physical Memory Width and Data-Type Size Fields Consider a ’C32 connected to two banks of external memory. In this configura-tion, one bank is...

Page 317 - Configuration; driving A; Active Strobe Byte Enable

Configuration 10-14 By setting the bit fields of the STRB0 bus control register with a physical-memory width of 32 bits and a data type size of 32 bits, the external addressreferring to the STRB0 location is identical to the internal address used by the‘C32 CPU. Alternatively, setting the bit fields...

Page 318 - The four modes are used to generate the internal ready signal, RDY

Programmable Wait States 10-15 TMS320C32 Enhanced External Memory Interface 10.4 Programmable Wait States The ’C3x has its own internal software-configurable ready-generation capabilityfor each strobe. This software wait-state generator is controlled by configuringtwo fields in the primary or expans...

Page 320 - Programmable Bank Switching; are compared. Bank sizes from 2; Figure 10–8. BNKCMP Example; Table 10–4. BNKCMP and Bank Size

Programmable Bank Switching 10-17 TMS320C32 Enhanced External Memory Interface 10.5 Programmable Bank Switching Programmable bank switching allows you to switch between external memorybanks without having to insert wait states externally due to memories that requireseveral cycles to turn off. Bank s...

Page 324 - Internal

32-Bit-Wide Memory Interface 10-21 TMS320C32 Enhanced External Memory Interface Table 10–5. Strobe Byte-Enable for 32-Bit-Wide Memory With 8-Bit Data-Type Size ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Internal A 1 ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ Internal A 0 ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ Active Strobe Byte Enable ÁÁÁÁ ÁÁÁÁ 0 ÁÁÁÁÁ ÁÁÁÁÁ 0 ÁÁÁÁÁ...

Page 325 - Internal A

32-Bit-Wide Memory Interface 10-22 For example, reading from or writing to memory locations 90 4000h to90 4004h involves the pins listed in Table 10–6. Table 10–6. Example of 8-Bit Data-Type Size ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Internal Address Bus ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ ExternalAddress Pins ÁÁÁÁÁÁÁÁ Á...

Page 326 - Width

32-Bit-Wide Memory Interface 10-23 TMS320C32 Enhanced External Memory Interface Figure 10–12. Functional Diagram for 16-Bit Data-Type Size and 32-Bit External-Memory Width A22A21A20A19 ... A1A0CSI/O(7-0) ’C32 A23 A22 A21 A20 A19 ... A1 A0 D(31-24)D(23-16) D(15-8) D(7-0) 1 0 Memory interface A22A21A2...

Page 331 - address pins A

16-Bit-Wide Memory Interface 10-28 Table 10–11. Example of 8-Bit Data-Type Size and 16-Bit-Wide External Memory ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Internal Address Bus ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ External Address Pins ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ STRB0_B3 / A –1 ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Active Strobe Byte ...

Page 333 - twice to

16-Bit-Wide Memory Interface 10-30 Case 6: 16-Bit-Wide Memory with 32-Bit Data-Type Size When the data type size is 32 bits, the ’C32 does not shift the internal addressbefore presenting it to the external address pins. In this case, the memoryinterface copies the value of the internal address bus t...

Page 335 - and A; Figure 10–18. External Memory Interface for 8-Bit SRAMs; to

8-Bit-Wide Memory Interface 10-32 10.8 8-Bit-Wide Memory Interface ’C32 memory interface to an 8-bit wide external memory uses STRBx_B3 andSTRBx_B2 pins as additional address pins, A –1 and A –2 , respectively, while using STRBx_B0 as strobe byte-enable pin as shown in Figure 10–18. Theexternal-memo...

Page 336 - STRBx

8-Bit-Wide Memory Interface 10-33 TMS320C32 Enhanced External Memory Interface Figure 10–19. Functional Diagram for 8-Bit Data-Type Size and 8-Bit External-Memory Width A23A22A21A20 ... A2 CSI/O(7-0) ’C32 A 23 A 22 A 21 A 20 A 19 A 18 ...A 0 STRBx_B3/A –1 STRBx_B2/A –2 STRBx_B0 D(7-0) A 23 A 22 A 21...

Page 341 - External Ready Timing Improvement; Figure 10–22. RDY Timing for Memory Read; Do not change the RDY signal during its setup time [

External Ready Timing Improvement 10-38 10.9 External Ready Timing Improvement The ready (RDY) timing should relate to the H1 low signal as shown inFigure 10–22. This is equivalent to the ’C4x ready timing, which increases thetime between valid address and the sampling of RDY. This facilitates the m...

Page 342 - STRB0 and STRB1 Bus Cycles

Bus Timing 10-39 TMS320C32 Enhanced External Memory Interface 10.10 Bus Timing This section discusses functional timing of operations on the external memorybus. Detailed timing specifications are contained in the TMS320C32 Data Sheet. The timing of STRB0 and STRB1 bus cycles is identical and discuss...

Page 343 - Bus Timing

Bus Timing 10-40 Figure 10–23. Read-Read-Write Sequence for STRBx Active RDY D A R/W STRBx H1 H3 Read Read Write Figure 10–24 shows a zero wait-state write-write-read sequence for STRBxactive. During back-to-back writes, the data is valid when STRBx changes for thefirst write, but for subsequent wri...

Page 344 - Figure 10–25. One Wait-State Read Sequence for STRBx Active

Bus Timing 10-41 TMS320C32 Enhanced External Memory Interface Figure 10–25 shows a one wait-state read sequence and Figure 10–26 showsthe write sequence for STRBx active. On the first H1 cycle, RDY is high; therefore,the read or write sequence is extended for one extra cycle. On the second H1cycle, ...

Page 345 - Figure 10–26. One Wait-State Write Sequence for STRBx Active; IOSTRB Bus Cycles

Bus Timing 10-42 Figure 10–26. One Wait-State Write Sequence for STRBx Active RDY D A R/W STRBx H1 H3 Extra cycle Write 10.10.2 IOSTRB Bus Cycles In contrast to STRB0 and STRB1 bus cycles, IOSTRB full speed (zero wait-state) reads and writes consume two H1 cycles. During these cycles, theIOSTRB sign...

Page 347 - Figure 10–28. One Wait-State Read Sequence for IOSTRB Active

Bus Timing 10-44 Figure 10–28. One Wait-State Read Sequence for IOSTRB Active IOSTRB RDY D A R/W H1 H3 Extra cycle Read Figure 10–29. One Wait-State Write Sequence for IOSTRB Active IOSTRB RDY D A R / W H1 H3 Extra cycle Write Figure 10–30 and Figure 10–31 illustrate the transitions between STRBxrea...

Page 348 - Figure 10–30. STRBx Read and IOSTRB Write

Bus Timing 10-45 TMS320C32 Enhanced External Memory Interface Figure 10–30. STRBx Read and IOSTRB Write I/O Write Read STRB0,1 IOSTRB RDY D A R / W H1 H3 Figure 10–31. STRBx Read and IOSTRB Read I/O read Read STRB0,1 IOSTRB RDY D A R / W H1 H3

Page 349 - Figure 10–32. STRBx Write and IOSTRB Write

Bus Timing 10-46 Figure 10–32 and Figure 10–33 illustrate the transitions between STRBxwrites and IOSTRB writes and reads, respectively. In these transitions, theaddress changes on the falling edge of the H3 cycle. Figure 10–32. STRBx Write and IOSTRB Write Write I/O write STRBx IOSTRB RDY D A R/W H...

Page 350 - Figure 10–34. IOSTRB Write and STRBx Write

Bus Timing 10-47 TMS320C32 Enhanced External Memory Interface Figure 10–34 through Figure 10–37 show the transitions between IOSTRBwrites/reads and STRBx writes/reads. In these transitions, the addresschanges on the rising edge of the H3 cycle. Figure 10–34. IOSTRB Write and STRBx Write I/O write Wr...

Page 351 - Figure 10–35. IOSTRB Write and STRBx Read

Bus Timing 10-48 Figure 10–35. IOSTRB Write and STRBx Read I/O Write Read STRBx IOSTRB RDY D A R/W H1 H3 Figure 10–36. IOSTRB Read and STRBx Write I/O read Write STRBx IOSTRB RDY D A R/W H1 H3

Page 352 - Figure 10–37. IOSTRB Read and STRBx Read

Bus Timing 10-49 TMS320C32 Enhanced External Memory Interface Figure 10–37. IOSTRB Read and STRBx Read Read I/O Read STRBx IOSTRB RDY D A R/W H1 H3 Figure 10–38 through Figure 10–40 illustrate the transitions between readsand writes.

Page 353 - Figure 10–38. IOSTRB Write and Read; Figure 10–39. IOSTRB Write and Write

Bus Timing 10-50 Figure 10–38. IOSTRB Write and Read I/O write IOSTRB RDY D A R/W H1 H3 I/O read Figure 10–39. IOSTRB Write and Write I/O write I/O write IOSTRB RDY D A R/W H1 H3

Page 354 - Figure 10–40. IOSTRB Read and Read; Inactive Bus States; Figure 10–41. Inactive Bus States Following IOSTRB Bus Cycle

Bus Timing 10-51 TMS320C32 Enhanced External Memory Interface Figure 10–40. IOSTRB Read and Read I/O Read I/O Read IOSTRB RDY D A R/W H1 H3 10.10.3 Inactive Bus States Figure 10–41 and Figure 10–42 show the signal states when a bus becomesinactive after an IOSTRB or STRBx, respectively. The strobes ...

Page 355 - Figure 10–42. Inactive Bus States Following STRBx Bus Cycle

Bus Timing 10-52 Figure 10–42. Inactive Bus States Following STRBx Bus Cycle I/O write STRBx RDY D A R/W H1 H3 Bus inactive RDY ignored

Page 356 - Loaders

11-1 Using the TMS320C31 and TMS320C32 Boot Loaders The ’C31 and ’C32 have on-chip boot loaders that can load and execute pro-grams received from a host processor, standard memory devices (includingEPROM), or via serial port. Topic Page 11.1 TMS320C31 Boot Loader 11-2 . . . . . . . . . . . . . . . ....

Page 358 - Boot-Loader Mode Selection; Loader Mode; External memory

TMS320C31 Boot Loader 11-3 Using the TMS320C31 and TMS320C32 Boot Loaders Table 11–1. Boot-Loader Mode Selection INT0 INT1 INT2 INT3 Loader Mode Memory Addresses 0 1 1 1 External memory Boot 1 address 0x001000 1 0 1 1 External memory Boot 2 address 0x400000 1 1 0 1 External memory Boot 3 address 0xF...

Page 359 - block loaded and begins program execution.

TMS320C31 Boot Loader 11-4 11.1.3 TMS320C31 Boot-Loading Sequence The following is the sequence of events that occur during the boot load of asource program. Table 11–2 shows the structure of the source program. 1) Select the boot loader by resetting the ’C31 while driving the MCBL / MP pin high and...

Page 363 - Source Data Stream Structure; Word

TMS320C31 Boot Loader 11-8 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 11–2. Source Data Stream Structure ÁÁÁÁ ÁÁÁÁ Word † ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Content ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Valid Data Entries ÁÁÁÁ ÁÁÁÁ 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Memory width (8, 1...

Page 364 - Byte-Wide Configured Memory; Memory width = 8 bits

TMS320C31 Boot Loader 11-9 Using the TMS320C31 and TMS320C32 Boot Loaders 11.1.4.1 Examples of External TMS320C31 Memory Loads Table 11–3, Table 11–4, and Table 11–5 show memory images for byte-wide,16-bit-wide, and 32-bit-wide configured memory (see Figure 4–2 on page 4-6). These examples assume th...

Page 367 - TMS320C31 Interrupt and Trap Memory Maps

TMS320C31 Boot Loader 11-12 Table 11–6. TMS320C31 Interrupt and Trap Memory Maps Address Description 809FC1 INT0 809FC2 INT1 809FC3 INT2 809FC4 INT3 809FC5 XINT0 809FC6 RINT0 809FC7 XINT1 (Reserved) 809FC8 RINT1 (Reserved) 809FC9 TINT0 809FCA TINT1 809FCB DINT0 809FCC–809FDF Reserved 809FE0 TRAP0 80...

Page 370 - Boot Loader Mode

TMS320C32 Boot Loader 11-15 Using the TMS320C31 and TMS320C32 Boot Loaders Table 11–7. Boot-Loader Mode Selection ÁÁÁ ÁÁÁ INT0 ÁÁÁ ÁÁÁ INT1 ÁÁÁÁ ÁÁÁÁ INT2 ÁÁÁ ÁÁÁ INT3 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Boot Loader Mode ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Source Program Location ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁÁÁ ÁÁÁÁ 1 ÁÁÁ ÁÁÁ 1 Á...

Page 375 - Figure 11–7. Handshake Data-Transfer Operation; n of the shaded entries in Table 11–8 contain the source data for the

TMS320C32 Boot Loader 11-20 Figure 11–7. Handshake Data-Transfer Operation Valid data Valid data i ii iii iv XF1 XF0 D31-0 IACK 11.2.4 TMS320C32 Boot Data Stream Structure Table 11–8 shows the data stream structure. The data stream is composed ofa header of three (serial-port load) or four (memory l...

Page 377 - SSSSSS6xh

TMS320C32 Boot Loader 11-22 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 11–8. Source Data Stream Structure (Continued) ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Valid Data Entries ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Content ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ Word † m + 2 Last block destination memory width and...

Page 381 - Figure 12–1. Timer Block Diagram

Timers 12-2 12.1 Timers The ’C3x has two 32-bit general-purpose timer modules. Each timer has twosignaling modes and internal or external clocking. You can use the timermodules to signal to the ’C3x or the external world at specified intervals or tocount external events. With an internal clock, the ...

Page 382 - Three memory-mapped registers are used by each timer:; Global-control register; The period register specifies the timer’s signaling frequency.; Counter register

Timers 12-3 Peripherals 12.1.1 Timer Pins Each timer has one pin associated with the timer clock signal (TCLK) pin. Thispin (TCK) is used as a general-purpose I/0 signal, as a timer output, or as aninput for an external clock for a timer. Each timer has a TCLK pin: TCLK0 isconnected to timer0, TCLK1...

Page 383 - Figure 12–2. Memory-Mapped Timer Locations

Timers 12-4 Figure 12–2. Memory-Mapped Timer Locations Timer0 global control† Timer0 counter‡ Timer0 period‡ Timer1 global control† Timer1 counter‡ Timer1 period‡ 808020h 808034h 808024h 808028h 808030h 808038h ‡See Section 12.1.4 †See Section 12.1.3 12.1.3 Timer Global-Control Register The timer gl...

Page 384 - Table 12–1. Timer Global-Control Register Bits Summary

Timers 12-5 Peripherals Table 12–1. Timer Global-Control Register Bits Summary Abbreviation Reset Value Name Description FUNC 0 Function Controls the function of TCLK. If FUNC = 0, TCLK is configured as a general-purpose digital I/Oport. If FUNC = 1, TCLK is configured as a timer pin. See section 12...

Page 387 - Figure 12–4. Timer Timing; Period register

Timers 12-8 Figure 12–4. Timer Timing 2/f(H1)1/f(H1) 1/f(CLKSRC) period register/f(CLKSRC) period register/f(CLKSRC) 2 x period register/f(CLKSRC) (a) TSTAT and timer output (INV = 0) when C/P = 0 (pulse mode) (b) TSTAT and timer output (INV = 0) when C/P = 1 (clock mode) 1/f(CLKSRC) 2/f(H1) TINT TI...

Page 388 - Example 12–1. Timer Output Generation Examples

Timers 12-9 Peripherals Example 12–1. Timer Output Generation Examples 2H1 2H1 H1 (a) INV = 0, C/P = 0 (pulse mode) timer period = 1Also, 4H1 H1 (b) INV = 0, C/P = 0 (pulse mode)timer period = 2 6H1 H1 (c) INV = 0, C/P = 0 (pulse mode)timer period = 3 4H1 (d) INV = 0, C/P = 1 (clock mode)timer perio...

Page 389 - Figure 12–5. Timer Configuration with CLKSRC = 1 and FUNC = 0

Timers 12-10 12.1.6 Timer Operation Modes The timer can receive its input and send its output in several different modes,depending upon the setting of CLKSRC, FUNC, and I/O. The four timer modesof operation are defined in the following sections. 12.1.6.1 CLKSRC = 1 and FUNC = 0 If CLKSRC = 1 and FUN...

Page 390 - Figure 12–6. Timer Configuration with CLKSRC = 1 and FUNC = 1

Timers 12-11 Peripherals 12.1.6.2 CLKSRC = 1 and FUNC = 1 If CLKSRC = 1 and FUNC = 1 (see Figure 12–6), the timer input comes fromthe internal clock, and the timer output goes to TCLK. This value can be invertedusing INV, and you can read in DATIN the value output on TCLK. Figure 12–6. Timer Configu...

Page 391 - Figure 12–8. Timer Configuration with CLKSRC = 0 and FUNC = 1

Timers 12-12 12.1.6.4 CLKSRC = 0 and FUNC = 1 If CLKSRC = 0 and FUNC = 1 (see Figure 12–8), TCLK drives the timer. - If INV = 0, all 0-to-1 transitions of TCLK increment the counter. - If INV = 1, all 1-to-0 transitions of TCLK increment the counter. You canread in DATIN the value of TCLK. Figure 12...

Page 393 - Example 12–2. Maximum Frequency Timer Clock Setup

Timers 12-14 2) Configure the timer through the timer global-control register (with GO = HLD = 0 ), the timer-counter register, and timer-period register, if necessary. 3) Start the timer by setting the GO/HLD bits of the timer global-control register. Example 12–2 shows how to set up the ‘C3x timer...

Page 395 - Serial Port Block Diagram

Serial Ports 12-16 Figure 12–11. Serial Port Block Diagram Receive Section Transmit Section Receive timer (16) Transmit timer (16) Bit counter (8/16/24/32) Bit counter (8/16/24/32) RSR (32) XSR (32) DRR (32) DXR (32) Load control Load control CLKR CLKX TSTAT CLKR CLKX TSTAT Receive Clock RINT FSR FS...

Page 396 - Figure 12–12. Memory-Mapped Locations for the Serial Ports

Serial Ports 12-17 Peripherals Figure 12–12. Memory-Mapped Locations for the Serial Ports Serial-port 0 global control { Serial port 0 FSR/DR/CLKR control § Serial port 0 R/X timer control ¶ Serial port 0 R/X timer counter # Serial port 0 R/X timer period k Serial port 0 data transmit l 808040h 8080...

Page 397 - Table 12–2. Serial-Port Global-Control Register Bits Summary; Receive ready flag

Serial Ports 12-18 Figure 12–13. Serial-Port Global-Control Register 28 RRESET RTINT XINT XTINT 31 30 29 27 26 25 24 23 22 21 20 19 18 17 16 RLEN XLEN FSRP FSXP R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CLKXP RFSM XFSM RCLK XCLK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HS RSR XSR FSXOUT XRDY RRDY SRC...

Page 406 - It is also set to 0 at reset.

Serial Ports 12-27 Peripherals Table 12–5. Receive/Transmit Timer-Control Register Register Bits Summary (Continued) Abbreviation Function Name Reset Value RCLKSRC 0 Receive timer clocksource Specifies the source of the receive timer clock. When RCLKSRC = 1, an internal clock with frequency equalto ...

Page 407 - cleared to 0 at reset.; Figure 12–19. Transmit Buffer Shift Operation

Serial Ports 12-28 12.2.6 Receive/Transmit Timer-Period Register The receive/transmit timer-period register is a 32-bit register (see Figure 12–18).Bits 15 –0 are the timer transmit period, and bits 31 –16 are the receive period.Each register specifies the period of the timer and is cleared to 0 at ...

Page 408 - When the data-receive register is read, both bytes; Figure 12–20. Receive Buffer Shift Operation

Serial Ports 12-29 Peripherals Data is shifted to the left (LSB to MSB). Figure 12–20 illustrates what happenswhen words less than 32 bits are shifted into the serial port. In this figure, it isassumed that an 8-bit word is being received and that the upper three bytesof the receive buffer are origi...

Page 412 - Figure 12–23. Data Word Format in Handshake Mode; Figure 12–24. Single 0 Sent as an Acknowledge Bit

Serial Ports 12-33 Peripherals 12.2.10.1 Continuous Transmit and Receive Modes When you choose continuous mode, consecutive writes do not generate orexpect new sync pulse signaling. Only the first word of a block begins withan active synchronization. Thereafter, data is transmitted as long as newdat...

Page 413 - Figure 12–25. Direct Connection Using Handshake Mode; Serial-Port Interrupt Sources; A serial port has the following interrupt sources:

Serial Ports 12-34 When the serial port is placed in the handshake mode, the insertion and deletionof a leading 1 for transmitted data, the sending of a 0 for acknowledgement ofreceived data, and the waiting for this acknowledge bit are all performed auto-matically. Using this scheme, it is simple t...

Page 414 - Serial-Port Functional Operation

Serial Ports 12-35 Peripherals 12.2.12 Serial-Port Functional Operation The following paragraphs and figures illustrate the functional timing of thevarious serial-port modes of operation. The timing descriptions are presentedwith the assumption that all signal polarities are configured to be positiv...

Page 415 - Fixed Burst Mode; Figure 12–26. Fixed Burst Mode; Fixed Standard Mode

Serial Ports 12-36 12.2.12.1 Fixed Data-Rate Timing Operation Fixed data-rate serial-port transfers can occur in two varieties: burst mode andcontinuous mode. In burst mode, transfers of single words are separated byperiods of inactivity on the serial port. In continuous mode, there are no gapsbetwe...

Page 416 - Figure 12–27. Fixed Standard Mode With Back-to-Back Frame Sync; Fixed Continuous Mode

Serial Ports 12-37 Peripherals Figure 12–27. Fixed Standard Mode With Back-to-Back Frame Sync A1 AN B1 BN C1 DXR loaded with A XINT DXR loaded with B XINT RINT XINT RINT CLKX/R FSX (Internal) FSR/FSX (External) DR/DX Load DXR with C read DRR Load DXR with Dread DRR R/XVAREN = 0 R/XFSM = 0 For receiv...

Page 417 - N–1 bit of the first word, except for transmit operations. For; Figure 12–28. Fixed Continuous Mode Without Frame Sync; Enabling or Disabling Frame Syncs in Fixed Mode; N–1 bit. The setting of XFSM is recognized as

Serial Ports 12-38 sync inputs are ignored. Additionally, you should set R/XFSM prior to orduring the first word transferred; you must set R/XFSM no later than thetransfer of the N–1 bit of the first word, except for transmit operations. For transmit operations in the fixed data-rate mode, XFSM must...

Page 418 - Variable Burst Mode; Figure 12–30. Variable Burst Mode

Serial Ports 12-39 Peripherals Figure 12–29. Exiting Fixed Continuous Mode Without Frame Sync, FSX Internal CLKX FSX (internal) DX LOAD DXR SET XFSM RESET XFSM A1 AN B1 BN C1 CN D1 DN E1 EN F1 FN 1st word 2nd word 3rd word 4th word 5th word 12.2.12.2 Variable Data-Rate Timing Operation The following...

Page 419 - Variable Standard Mode; N–4 bit to maintain continuous opera-; Figure 12–31. Variable Standard Mode With Back-to-Back Frame Syncs; N–4 bit to maintain continuous operation. Additionally, when

Serial Ports 12-40 - Variable Standard Mode When you transmit continuously in variable data-rate mode with frame sync,timing is the same as for fixed data-rate mode, except for the differencesbetween these two modes as described in Section 12.2.12 Serial-Port Functional Operation, on page 12-35. The...

Page 420 - Figure 12–32. Variable Continuous Mode Without Frame Sync; Serial-Port Initialization/Reconfiguration

Serial Ports 12-41 Peripherals Figure 12–32. Variable Continuous Mode Without Frame Sync CLKX/R FSR/FSX (external) FSX (internal) DX/DR A1 AN B1 BN C1 C2 XINT RINT Load DXR with D read DRR Set R/XFS M DXR loaded with B XINT DXR loaded with A XINT RINT Load DXR with C read DRR R/XVAREN = 1 R/XFSM = 1...

Page 421 - ) Set the XFSM and RFSM bits to 0 and the FSXOUT bit to 1 in the global-

Serial Ports 12-42 12.2.14.1 Handshake Mode Example When using the handshake mode, the transmit (FSX/DS/CLKX) and receive(FSR/DR/CLKR) signals transmit and receive data, respectively. Even if the’C3x serial port is receiving data only with handshake mode, the transmit signalsare still needed to tran...

Page 422 - CPU Transfer With Serial Port Transmit Polling Method

Serial Ports 12-43 Peripherals Example 12–4 and Example 12–5 are serial-port register setups for the abovecase. (Assume two ’C3xs have the same system clock.) Example 12–4. Serial-Port Register Setup #1 Global control = 0EBC0064h; 32 bits, fixed data rate, burst mode, Transmit port control = 0111h ;...

Page 424 - Timer-period register

Serial Ports 12-45 Peripherals 12.2.14.3 DMA Transfer With Serial Port Interrupt Example 12–8 and Example 12–9 of Section 12.3.11 on page 12-74 use theDMA synchronized to serial port interrupts to transfer data (128 words) froman array buffer to the serial port0 output register. 12.2.14.4 Serial Ana...

Page 425 - FSR0 pin) that serial data is to be transmitted.

Serial Ports 12-46 12.2.14.5 Serial Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Interface Example The DSP201/2 and DSP101/2 family of D/As and A/Ds from Burr Brown alsooffer a zero-glue-logic interface to the ’C3x family of DSPs. The interface isshown in Example 12–7. This interface is used ...

Page 426 - the ’C3x serial port.

Serial Ports 12-47 Peripherals 4) The bit clock drives both the A/D’s and D/A’s XCLK input. 5) The ’C3x transmit clock also acts as the input clock on the receive side of the ’C3x serial port. 6) Since the receive clock is synchronous to the internal clock of the ’C3x, the receive clock can run at f...

Page 427 - DMA Controller

DMA Controller 12-48 12.3 DMA Controller The DMA controller is a programmable peripheral that transfers blocks of datato any location in the memory map without interfering with CPU operation. The’C3x can interface to slow, external memories and peripherals without reducingthroughput to the CPU. The ...

Page 428 - TMS320C32 Two-Channel DMA Controller

DMA Controller 12-49 Peripherals 12.3.1.1 TMS320C30 and TMS320C31 DMA Controller The ’C30 and ’C31 have an on-chip direct memory access (DMA) controllerthat reduces the need for the CPU to perform input/output functions. The DMAcontroller can perform input/output operations without interfering with ...

Page 429 - DMA Registers Initialization

DMA Controller 12-50 12.3.2 DMA Basic Operation If a block of data is to be transferred from one region in memory to another regionin memory (as shown in Figure 12–34), the following sequence is performed: DMA Registers Initialization 1) The source-address register of a DMA channel is loaded with th...

Page 430 - Figure 12–34. DMA Basic Operation; Each DMA channel has four registers designated as follows:; Transfer-counter register: contains the block size to move

DMA Controller 12-51 Peripherals After the completion of a block transfer, the DMA controller can be programmedto do several things: - Stop until reprogrammed (TC = 1) - Continue transferring data (TC = 0) - Generate an interrupt to signal the CPU that the block transfer is complete(TCINT = 1) The D...

Page 431 - Figure 12–35. Memory-Mapped Locations for DMA Channels

DMA Controller 12-52 At reset, each DMA-channel control register is set to 0. This makes the DMAchannels lower-priority than the CPU, sets up the source address and destinationaddress to be calculated through linear addressing, and configures the DMAchannel in the unified mode. Figure 12–35. Memory-...

Page 433 - Table 12–6. DMA Global-Control Register Bits Summary

DMA Controller 12-54 Table 12–6. DMA Global-Control Register Bits Summary Abbreviation Reset Value Name Description START 00 DMA start control Controls the state in which the DMA starts and stops. TheDMA may be stopped without any loss of data. The following table summarizes the START bits and DMAop...

Page 436 - Destination-Address and Source-Address Registers; Figure 12–39. DMA Controller Address Generation

DMA Controller 12-57 Peripherals 12.3.3.2 Destination-Address and Source-Address Registers The DMA destination-address and source-address registers are 24-bit registerswhose contents specify destination and source addresses. As specified bycontrol bits DECSRC, INCSRC, DECDST, and INCDST of the DMA g...

Page 437 - Transfer-Counter Register

DMA Controller 12-58 12.3.3.3 Transfer-Counter Register The transfer-counter register is a 24-bit register that contains the number ofwords to be transmitted. Figure 12–40 shows the transfer-counter operation.It is controlled by a 24-bit counter that decrements at the beginning of a DMAmemory write....

Page 439 - Interrupt-Enable Register

DMA Controller 12-60 Figure 12–41. TMS320C30 and TMS320C31 CPU/DMA Interrupt-Enable Register xx EDINT ETINT1 ETINT0 ERINT1 EXINT1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 xx xx xx xx ERINT0 EXINT0 EINT3 EINT2 EINT1 EINT0 (DMA) (DMA) (DMA) (DMA) (DMA) (DMA) (DMA) (DMA) (DMA) (DMA) (DMA) R/W R/...

Page 442 - CPU and DMA Controller Arbitration; priority than the DMA when DMA PRI = 11

DMA Controller 12-63 Peripherals 12.3.5.2 Rotating Priority Scheme In a rotating priority scheme, the last channel serviced becomes the lowestpriority channel. The other channel sequentially rotates through the priority listwith the lowest channel next to the last-serviced channel becoming the highe...

Page 443 - Table 12–8. TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules; DMA PRI; This setting selects; consecutive instruction cycles. The first; The DMA controller uses interrupts in the following way:

DMA Controller 12-64 Table 12–8. TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules DMA PRI (Bits 13–12) Description 0 0 DMA access is lower priority than the CPU access. If the DMAchannel and the CPU request the same resource, then the CPUhas priority. (DMA PRI bits are set to 00 2 at reset.) 0 1...

Page 444 - Interrupt Vector Table and Prioritization, on page 7-29 for; Interrupts and Synchronization of DMA Channels; Figure 12–43. Mechanism for No DMA Synchronization

DMA Controller 12-65 Peripherals The DMA and the CPU can respond to the same interrupt if the CPU is notinvolved in any pipeline conflict or in any instruction that halts instruction fetching.Refer to section 7.6.2, Interrupt Vector Table and Prioritization, on page 7-29 for more details. It is also...

Page 447 - On-chip memory and peripheral; Single DMA Memory Transfer Timing; transfers, assuming that there are no pipeline conflicts.

DMA Controller 12-68 The data transfer rate for a DMA channel (assuming a single-channel accesswith no conflicts between CPU or other DMA channels) is as follows: - On-chip memory and peripheral J DMA read: One cycle J DMA write: One cycle - External memory (STRB, STRB0, STRB1, MSTRB) J DMA read: Tw...

Page 448 - Figure 12–47. DMA Timing When Destination is On Chip

DMA Controller 12-69 Peripherals Figure 12–47. DMA Timing When Destination is On Chip Cycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate Source on chip R1 R2 R3 R4 R5 R6 R7 R8 (1 + 1) T Destination on chip W1 W2 W3 W4 W5 W6 W7 (1 + 1) T Source STRB STRB0 STRB1 MSTRB bus R1 R1 R1 I R2 R2 R...

Page 451 - Figure 12–49. DMA Timing When Destination is an IOSTRB Bus

DMA Controller 12-72 Figure 12–49. DMA Timing When Destination is an IOSTRB Bus Cycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate Source on chip R1 R2 R3 R4 R5 Destination IOSTRB W1 W1 W1 W1 W2 W2 W2 W2 W3 W3 W3 W3 W4 W4 W4 W4 1 + (2 + Cw) T Destination IOSTRB Cw Cw Cw Cw 1 + (2 + Cw) T ...

Page 452 - ) Configure the DMA through the DMA global-control register (with; Hints for DMA Programming; Expansion and Peripheral Buses

DMA Controller 12-73 Peripherals 12.3.9 DMA Initialization/Reconfiguration You can control the DMA through memory-mapped registers located on thededicated peripheral bus. Following is the general procedure for initializingand/or reconfiguring the DMA: 1) Halt the DMA by clearing the START bits of th...

Page 453 - The STAT bits in the DMA channel-control register are set to 00; DMA Programming Examples

DMA Controller 12-74 - The transfer counter has a zero value. However, the transfer counter isdecremented after the DMA read operation finishes (not after the writeoperation). Nevertheless, a transfer counter with a 0 value can be used asan indication of a transfer completion. - The STAT bits in the...

Page 454 - Example 12–8. Array Initialization With DMA

DMA Controller 12-75 Peripherals Example 12–8. Array Initialization With DMA * TITLE: ARRAY INITIALIZATION WITH DMA* .GLOBAL START .DATADMA .WORD 808000H ; DMA GLOBAL-CONTROL REG ADDRESS RESET .WORD 0C40H ; DMA GLOBAL-CONTROL REG RESET VALUE CONTROL .WORD 0C43H ; DMA GLOBAL-CONTROL REG INITIALIZATIO...

Page 455 - Example 12–9. DMA Transfer With Serial-Port Receive Interrupt

DMA Controller 12-76 Example 12–9. DMA Transfer With Serial-Port Receive Interrupt * TITLE DMA TRANSFER WITH SERIAL PORT RECEIVE INTERRUPT* .GLOBAL START.DATA DMA .WORD 808000H ; DMA GLOBAL-CONTROL REG ADDRESS CONTROL .WORD 0D43H ; DMA GLOBAL-CONTROL REG INITIALIZATION SOURCE .WORD 80804CH ; DATA SO...

Page 456 - Serial-Port Transmit Synchronization; DMA Transfer With Serial-Port Transmit Interrupt

DMA Controller 12-77 Peripherals Example 12–10 sets up the DMA to transfer data (128 words) from an arraybuffer to the serial port 0 output register with serial port transmit interrupt XINT0.The DMA sends an interrupt to the CPU when the data transfer completes. Serial port 0 is initialized to trans...

Page 457 - Other examples are as follows:

DMA Controller 12-78 Example 12–10. DMA Transfer With Serial-Port Transmit Interrupt (Continued) * DMA INITIALIZATION LDI @DMA,AR0 ; POINT TO DMA GLOBAL CONTROL REGISTER LDI @SPORT,AR1LDI @RESET,R0STI R0,*+AR1(4) ; RESET SPORT TIMER STI R0,*AR0 ; RESET DMA STI R0,*AR1 ; RESET SPORT LDI @SOURCE,R0 ; ...

Page 459 - Assembly Language Instructions; cond. This chapter defines the condition; Instruction Set Summary

13-1 Assembly Language Instructions The ’C3x assembly language instruction set supports numeric-intensive, signal-processing, and general-purpose applications. (The addressing modes used withthe instructions are described in Chapter 5.) The ’C3x instruction set can also use one of 20 condition codes...

Page 460 - Table 13–1. Load and Store Instructions; Instruction

Instruction Set 13-2 13.1 Instruction Set The ’C3x instruction set is well suited to digital signal processing and othernumeric-intensive applications. All instructions are a single machine wordlong, and most instructions require one cycle to execute. In addition to multiplyand accumulate instructio...

Page 462 - count operand) and a destination operand. A source

Instruction Set 13-4 13.1.3 3-Operand Instructions Whereas 2-operand instructions have a single source operand (or shift count) and a destination operand, 3-operand instructions can have two source operands(or one source operand and a count operand) and a destination operand. A source operand can be...

Page 463 - Table 13–5. Low-Power Control Instructions

Instruction Set 13-5 Assembly Language Instructions Table 13–4. Program-Control Instructions Instruction Description Instruction Description B cond Branch conditionally (standard) IDLE Idle until interrupt B condD Branch conditionally (delayed) NOP No operation BR Branch unconditionally (standard) R...

Page 464 - Table 13–6. Interlocked-Operations Instructions; Parallel loading of registers; Table 13–7. Parallel Instructions

Instruction Set 13-6 Table 13–6. Interlocked-Operations Instructions Instruction Description Instruction Description LDFI Load floating-point value, interlocked STFI Store floating-point value, interlocked LDII Load integer, interlocked STII Store integer, interlocked SIGI Signal, interlocked 13.1.7...

Page 466 - ’C31 silicon revision 6.0 or greater

Instruction Set 13-8 Table 13–7. Parallel Instructions (Continued) (b) Parallel load instructions Mnemonic Description LDF || LDF Load floating-point value LDI || LDI Load integer (c) Parallel multiply and add/subtract instructions Mnemonic Description MPYF3 || ADDF3 Multiply and add floating-point ...

Page 467 - Misuse of the tools

Instruction Set 13-9 Assembly Language Instructions 13.1.8 Illegal Instructions The ’C3x has no illegal instruction-detection mechanism. Fetching an illegal(undefined) opcode can cause the execution of an undefined operation. Properuse of the TI TMS320 floating-point software tools will not generate...

Page 468 - Table 13–8. Instruction Set Summary

Instruction Set Summary 13-10 13.2 Instruction Set Summary Table 13–8 lists the ’C3x instruction set in alphabetical order. Each table entryprovides the instruction mnemonic, description, and operation. Table 13–8. Instruction Set Summary Mnemonic Description Operation ABSF Absolute value of a float...

Page 475 - Parallel Instruction Set Summary; Table 13–9. Parallel Instruction Set Summary

Parallel Instruction Set Summary 13-17 Assembly Language Instructions 13.3 Parallel Instruction Set Summary Table 13–9 lists the ’C3x instruction set in alphabetical order. Each tableentry shows the instruction mnemonic, description, and operation. Refer toSection 13.1 for a functional listing of th...

Page 478 - Group Addressing Mode Instruction Encoding; General Addressing Modes; Mode; Register (all CPU registers unless specified otherwise)

Group Addressing Mode Instruction Encoding 13-20 13.4 Group Addressing Mode Instruction Encoding The six addressing types (covered in Section 6.1, Addressing Types, on page 6-2) form these four groups of addressing modes: - General addressing modes (G) - 3-operand addressing modes (T) - Parallel add...

Page 479 - Figure 13–1. Encoding for General Addressing Modes

Group Addressing Mode Instruction Encoding 13-21 Assembly Language Instructions Figure 13–1 shows the encoding for the general addressing modes. The notationmod n indicates the modification field that goes with the ARn field. Refer to Table 13–10 on page 13-22 for further information. Figure 13–1. E...

Page 480 - Table 13–10. Indirect Addressing

Group Addressing Mode Instruction Encoding 13-22 Table 13–10. Indirect Addressing (a) Indirect addressing with displacement Mod Field Syntax Operation Description 00000 *+AR n(disp) addr = AR n + disp With predisplacement add 00001 *– AR n(disp) addr = AR n – disp With predisplacement subtract 00010...

Page 482 - src1 addressing modes

Group Addressing Mode Instruction Encoding 13-24 13.4.2 3-Operand Addressing Modes Instructions that use the 3-operand addressing modes, such as ADDI3, LSH3,CMPF3, or XOR3, usually have this form: src1 operation src2 → dst where the destination operand is signified by dst and the source operands by ...

Page 483 - Figure 13–2. Encoding for 3-Operand Addressing Modes; Figure 13–3. Encoding for Parallel Addressing Modes

Group Addressing Mode Instruction Encoding 13-25 Assembly Language Instructions The following values of AR n and ARm are valid: AR n,0 ≤ n ≤ 7 AR m,0 ≤ m ≤ 7 The notation modm or modn indicates the modification field that goes with the AR m or ARn field, respectively. Refer to Table 13–10 on page 13...

Page 485 - Figure 13–5. Encoding for Conditional-Branch Addressing Modes

Group Addressing Mode Instruction Encoding 13-27 Assembly Language Instructions 13.4.4 Conditional-Branch Addressing Modes Instructions using the conditional-branch addressing modes (B cond, Bcond D, CALL cond, DBcond, and DBcond D) can perform a variety of conditional operations. Bits 31–27 are set...

Page 486 - Condition Codes and Flags; cond field of any of the conditional instructions, such as; Table 13–11. Output Value Formats; Type of Operation; Floating point

Condition Codes and Flags 13-28 13.5 Condition Codes and Flags The ’C3x provides 20 condition codes (00000–10100, excluding 01011) thatyou can place in the cond field of any of the conditional instructions, such as RETS cond or LDFcond. The conditions include signed and unsigned compari- sons, compa...

Page 487 - Figure 13–6. Status Register; LUF; result

Condition Codes and Flags 13-29 Assembly Language Instructions Figure 13–6. Status Register PRGW status (’C32 only) INT config (’C32 only) Note: xx = reserved bit, read as 0R = read, W = write GIE CC CE CF xx RM OVM LUF LV UF N Z V C R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13...

Page 488 - Table 13–12. Condition Codes and Flags; Unconditional

Condition Codes and Flags 13-30 Table 13–12 lists the condition mnemonic, code, description, and flag for eachof the 20 condition codes. Table 13–12. Condition Codes and Flags (a) Unconditional compares Condition Code Description Flag † U 00000 Unconditional Irrevelant (b) Unsigned compares Conditio...

Page 490 - Individual Instructions; Software Applications, of the TMS320C3x General-

Individual Instructions 13-32 13.6 Individual Instructions This section contains the individual assembly language instructions for the ’C3x.The instructions are listed in alphabetical order. Information for each instructionincludes assembler syntax, operation, operands, encoding, description, cycles...

Page 491 - Table 13–13. Instruction Symbols; Symbol

Individual Instructions 13-33 Assembly Language Instructions Table 13–13. Instruction Symbols Symbol Meaning srcsrc1src2src3src4 Source operandSource operand 1Source operand 2Source operand 3Source operand 4 dstdst1dst2dispcondcount Destination operandDestination operand 1Destination operand 2Displa...

Page 494 - 7, which is used to designate; Table 13–14. CPU Register Syntax; Assemblers

Individual Instructions 13-36 - Use the syntax in Table 13–14 to designate CPU registers in operands.Note the alternate notation R n, 0 v n v 27, which is used to designate any CPU register. Table 13–14. CPU Register Syntax Assemblers Syntax Alternate Register Syntax Assigned Function R0 R1 R2 R3 R4...

Page 495 - Individual Instruction Descriptions

Individual Instructions 13-37 Assembly Language Instructions 13.6.3 Individual Instruction Descriptions Each assembly language instruction for the ’C3x is described in this sectionin alphabetical order. The description includes the assembler syntax, operation,operands, encoding, description, cycles,...

Page 496 - EXAMPLE; Example Instruction; Syntax

EXAMPLE Example Instruction 13-38 Syntax INST src, dst or INST1 src2, dst1 || INST2 src3, dst2 Each instruction begins with an assembler syntax expression. You can placelabels either before the command (instruction mnemonic) on the same line oron the preceding line in the first column. The optional ...

Page 498 - Example

EXAMPLE Example Instruction 13-40 Example INST @98AEh,R5 Before Instruction After Instruction R5 07 6690 0000 R5 00 6690 1000 R5 decimal 2.30562500e+02 R5 decimal 1.80126953e+00 DP 080 DP 080 LUF 0 LUF 0 LV 0 LV 0 UF 0 UV 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098AEh 5CDF 8098AEh 5CDF 0200h ...

Page 499 - Absolute Value of Floating Point; ABSF

Absolute Value of Floating Point ABSF 13-41 Assembly Language Instructions Syntax ABSF src, dst Operation | src| → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (R n, 0 ≤ n ≤ 7) Opcode 31 24 23...

Page 500 - Parallel ABSF and STF

ABSF||STF Parallel ABSF and STF 13-42 Syntax ABSF src2, dst1 || STF src3, dst2 Operation | src2 | → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n1, 0 ≤ n1 ≤ 7) src3 register (R n2, 0 ≤ n2 ≤ 7) dst2 indirect ( disp = 0, 1, IR0, IR1) This instruction’s operands...

Page 501 - Mode Bit; Operation is not affected by OVM bit value.; Cycle Count; Data Loads and Stores, on page 8-24 for the effects of

Parallel ABSF and STF ABSF||STF 13-43 Assembly Language Instructions Mode Bit OVM Operation is not affected by OVM bit value. Example ABSF *++AR3(IR1) ,R4  STF R4,*– AR7(1) Before Instruction After Instruction R4 07 33C0 0000 R4 05 74C0 0000 AR3 80 9800 AR3 8098AF AR7 80 98C5 AR7 8098C5 IR1 0AF IR...

Page 502 - ABSI; Absolute Value of Integer

ABSI Absolute Value of Integer 13-44 Syntax ABSI src, dst Operation | src| → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0 0 0 0 0 src 0 dst G 1 0 Description The...

Page 503 - Example 1; Example 2

Absolute Value of Integer ABSI 13-45 Assembly Language Instructions Example 1 ABSI R0,R0 or ABSI R0 Before Instruction After Instruction R0 00 FFFF FFCB R 0 00 0000 0035 –53 53 Example 2 ABSI *AR1,R3 Before Instruction After Instruction R3 00 0000 0000 R3 00 0000 0035 AR1 00 0020 AR1 00 0020 Data me...

Page 504 - Parallel ABSI and STI

ABSI||STI Parallel ABSI and STI 13-46 Syntax ABSI src2, dst1 || STI src3, dst2 Operation | src2 | → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n1, 0 ≤ 1 ≤ 7) src3 register (R n2, 0 ≤ n2 ≤ 7) dst2 indirect ( disp = 0, 1, IR0, IR1) This instruction’s operands ...

Page 506 - Add Integer With Carry; ADDC

ADDC Add Integer With Carry 13-48 Syntax ADDC src, dst Operation dst + src + C → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0 0 0 0 1 src 0 dst G 0 Description T...

Page 509 - Add Floating-Point Values; ADDF

Add Floating-Point Values ADDF 13-51 Assembly Language Instructions Syntax ADDF src, dst Operation dst + src → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (R n, 0 ≤ n ≤ 7) Opcode src 31 2423 ...

Page 514 - Parallel ADDF3 and STF; OVM

ADDF3||STF Parallel ADDF3 and STF 13-56 OVM Operation is not affected by OVM bit value. Example ADDF3 *+AR3(IR1),R2,R5 || STF R4,*AR2 Before Instruction After Instruction R2 07 0C80 0000 R2 07 0C80 0000 R4 05 7B40 0000 R4 05 7B40 0000 R5 00 0000 0000 R5 08 2020 0000 AR2 80 98F3 AR2 80 98F3 AR3 80 98...

Page 515 - Add Integer

Add Integer ADDI 13-57 Assembly Language Instructions Syntax ADDI src, dst Operation dst + src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0 0 0 0 0 1 G src dst...

Page 518 - Parallel ADDI3 and STI

ADDI3||STI Parallel ADDI3 and STI 13-60 Syntax ADDI3 src2, src1, dst1 || STI src3, dst2 Operation src1 + src2 → dst1 || src3 → dst2 Operands src1 register (R n1, 0 ≤ n1 ≤ 7) src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n2, 0 ≤ n2 ≤ 7) src3 register (R n3, 0 ≤ n3 ≤ 7) dst2 indirect ( disp ...

Page 519 - Operation is affected by OVM bit value.

Parallel ADDl3 and STI ADDl3||STI 13-61 Assembly Language Instructions OVM Operation is affected by OVM bit value. Example ADDI3 *AR0 – – (IR0),R5,R0  STI R3,*AR7 Before Instruction After Instruction R0 00 0000 0000 R0 00 0000 0208 R3 00 0000 0035 R3 00 0000 0035 R5 00 0000 00DC R5 00 0000 00DC AR...

Page 520 - AND

AND Bitwise-Logical AND 13-62 Syntax AND src, dst Operands dst AND src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate (not sign extended) dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0 0 0 0 0 1 dst src 0 1 G...

Page 524 - Parallel AND3 and STI

AND3||STI Parallel AND3 and STI 13-66 OVM Operation is not affected by OVM bit value. Example AND3 *+AR1(IR0),R4,R7 || STI R3,*AR2 Before Instruction After Instruction R0 00 0000 0008 R0 00 0000 0008 R3 00 0000 0035 R3 00 0000 0035 R4 00 0000 A323 R4 00 0000 A323 R7 00 0000 0000 R7 00 0000 0003 AR1 ...

Page 525 - Bitwise-Logical AND With Complement; ANDN

Bitwise-Logical AND With Complement ANDN 13-67 Assembly Language Instructions Syntax ANDN src, dst Operation dst AND ∼ src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate (not sign extended) dst any CPU register Opc...

Page 526 - Bitwise-Logical AND With Complement

ANDN Bitwise-Logical AND With Complement 13-68 Example ANDN @980Ch,R2 Before Instruction After Instruction R2 00 0000 0C2F R2 00 0000 042D DP 080 DP 080 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80980Ch 0A02 80980Ch 0A02

Page 529 - Arithmetic Shift; ASH

Arithmetic Shift ASH 13-71 Assembly Language Instructions Syntax ASH count, dst Operation If ( count ≥ 0): dst << count → dst Else: dst >> |count | → dst Operands count general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst a...

Page 533 - operand ordering on the cycle count.

Arithmetic Shift, 3-Operand ASH3 13-75 Assembly Language Instructions Example 2 ASH3 R1,R3,R5 Before Instruction After Instruction R1 00 FFFF FFF8 R1 00 FFFF FFF8 R3 00 FFFF CB00 R3 00 FFFF CB00 R5 00 0000 0000 R5 00 FFFF FFCB LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 0 C 0 C 0 –8 –8 Not...

Page 534 - Parallel ASH3 and STI

ASH3||STI Parallel ASH3 and STI 13-76 Syntax ASH3 count, src2, dst1 || STI src3, dst2 Operation If (coun t ≥ 0): src2 << count → dst1 Else: src2 >> |count| → dst1 || src3 → dst2 Operands count register (Rn1, 0 ≤ n1 ≤ 7) src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n2, 0 ≤ n2 ≤...

Page 537 - Bcond

Branch Conditionally (Standard) Bcond 13-79 Assembly Language Instructions Syntax B cond src Operation If cond is true: If src is in register-addressing mode (Rn, 0 ≤ n ≤ 27), src → PC. If src is in PC-relative mode (label or address), displacement + PC + 1 → PC. Else, continue Operands src conditio...

Page 539 - BcondD

Branch Conditionally (Delayed) BcondD 13-81 Assembly Language Instructions Syntax B cond D src Operation If cond is true: If src is in register-addressing mode (Rn, 0 ≤ n ≤ 27), src → PC. If src is in PC-relative mode (label or address), displacement + PC + 3 → PC. Else, continue Operands src condit...

Page 541 - BR

Branch Unconditionally (Standard) BR 13-83 Assembly Language Instructions Syntax BR src Operation src → PC Operands src long-immediate addressing mode Opcode 31 24 23 16 8 7 0 15 0 1 1 0 0 0 0 0 src Description BR performs a PC-relative branch that executes in four cycles, since a pipelineflush also...

Page 542 - BRD; BRD 2Ch

BRD Branch Unconditionally (Delayed) 13-84 Syntax BRD src Operation src → PC Operands src long-immediate addressing mode Opcode 31 24 23 16 8 7 0 15 0 1 1 0 0 1 0 0 src Description BRD signifies a delayed branch that allows the three instructions after thedelayed branch to be fetched before the PC i...

Page 543 - Call Subroutine; CALL

Call Subroutine CALL 13-85 Assembly Language Instructions Syntax CALL src Operation Next PC → *++SP src → PC Operands src long-immediate addressing mode Opcode 31 24 23 16 8 7 0 15 0 1 1 0 0 0 1 0 src Description A call is performed. The next PC value is pushed onto the system stack. Thesrc operand ...

Page 544 - CALLcond; Call Subroutine Conditionally

CALLcond Call Subroutine Conditionally 13-86 Syntax CALL cond src Operation If cond is true: Next PC → *++SP If src is in register addressing mode (Rn, 0 ≤ n ≤ 27), src → PC. If src is in PC-relative mode (label or address), displacement + PC + 1 → PC. Else, continue Operands src conditional-branch ...

Page 545 - CALLNZ R5

Call Subroutine Conditionally CALLcond 13-87 Assembly Language Instructions Example CALLNZ R5 Before Instruction After Instruction R5 00 0000 0789 R5 00 0000 0789 PC 0123 PC 0789 SP 809835 SP 809836 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809836h 124

Page 546 - CMPF; Compare Floating-Point Value

CMPF Compare Floating-Point Value 13-88 Syntax CMPF src, dst Operation dst – src Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 0 0 0 0 0 1 0 dst 0 0 G sr...

Page 550 - CMPI; Compare Integer

CMPI Compare Integer 13-92 Syntax CMPI src, dst Operation dst – src Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 0 0 0 0 0 1 0 dst 0 1 G src Descripti...

Page 553 - Decrement and Branch Conditionally (Standard); DBcond

Decrement and Branch Conditionally (Standard) DBcond 13-95 Assembly Language Instructions Syntax DB cond ARn, src Operation AR n – 1 → AR n If cond is true and ARn ≥ 0 : If src is in register addressing mode (Rn, 0 ≤ n ≤ 27), src → PC. If src is in PC-relative mode (label or address), displacement +...

Page 555 - Decrement and Branch Conditionally (Delayed); DBcondD

Decrement and Branch Conditionally (Delayed) DBcondD 13-97 Assembly Language Instructions Syntax DB cond D ARn, src Operation AR n – 1 → AR n If cond is true and ARn ≥ 0: If src is in register addressing mode (Rn, 0 ≤ n ≤ 27) src → PC If src is in PC-relative mode (label or address) displacement + P...

Page 557 - FIX

Floating-Point-to-Integer Conversion FIX 13-99 Assembly Language Instructions Syntax FIX src, dst Operation fix (src) → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 31 24 23 16 ...

Page 560 - Parallell FIX and STI

FIX||STI Parallell FIX and STI 13-102 Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF Unaffected LV 1 if an integer overflow occurs; unchanged otherwise UF 0 N 1 if a negative result is generated; 0 otherwise Z 1 if a 0 result is generated; 0 otherwise...

Page 561 - FLOAT

Integer-to-Floating-Point Conversion FLOAT 13-103 Assembly Language Instructions Syntax FLOAT src, dst Operation float (src) → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 7) Opc...

Page 564 - Parallel FLOAT and STF

FLOAT||STF Parallel FLOAT and STF 13-106 Example FLOAT *+AR2(IR0),R6 || STF R7,*AR1 Before Instruction After Instruction R6 00 0000 0000 R6 07 2E00 0000 R7 03 4C20 0000 R7 03 4C20 0000 AR1 80 9933 AR1 80 9933 AR2 80 98C5 AR2 80 98C5 IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0...

Page 565 - Interrupt Acknowledge; IACK

Interrupt Acknowledge IACK 13-107 Assembly Language Instructions Syntax IACK src Operation Perform a dummy read operation with IACK = 0.At end of dummy read, set IACK to 1. Operands src general addressing modes (G): 0 1 direct 1 0 indirect Opcode 31 24 23 16 8 7 0 15 0 0 0 1 1 1 src 1 G 0 0 0 0 0 0 ...

Page 567 - Idle Until Interrupt; IDLE

Idle Until Interrupt IDLE 13-109 Assembly Language Instructions Syntax IDLE Operation 1 → ST(GIE) Next PC → PC Idle until interrupt. Operands None Opcode 31 24 23 16 8 7 0 15 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description The global-interrupt-enable bit is set, the next ...

Page 569 - The processor idles until a reset

Low-Power Idle IDLE2 13-111 Assembly Language Instructions For correct device operation, the three instructions after a delayedbranch should not be IDLE or IDLE2 instructions. Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Oper...

Page 570 - LDE; Load Floating-Point Exponent

LDE Load Floating-Point Exponent 13-112 Syntax LDE src, dst Operation src(exp) → dst(exp) Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (R n, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 0 0 0 0 0 0 1 1 ...

Page 572 - Load Floating-Point Value

LDF Load Floating-Point Value 13-114 Syntax LDF src, dst Operation src → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (R n, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 0 0 0 0 0 1 1 0 1 dst src G D...

Page 573 - Load Floating-Point Value Conditionally; LDFcond

Load Floating-Point Value Conditionally LDFcond 13-115 Assembly Language Instructions Syntax LDF cond src, dst Operation If cond is true: src → dst. Else: dst is unchanged. Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 i...

Page 575 - LDFI

Load Floating-Point Value, Interlocked LDFI 13-117 Assembly Language Instructions Syntax LDFI src, dst Operation Signal interlocked operationsrc → dst Operands src general addressing modes (G): 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) dst register (Rn, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 ...

Page 578 - Parallel LDF and LDF

LDF||LDF Parallel LDF and LDF 13-120 Example LDF * – – AR1(IR0),R7 || LDF *AR7++(1),R3 Before Instruction After Instruction R3 00 0000 0000 R0 00 0000 0008 R7 00 0000 0000 R3 05 7B40 0000 AR1 80 985F R7 07 0C80 0000 AR7 80 988A AR1 80 9857 IR0 8 AR7 80 988B LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z ...

Page 580 - Parallel LDF and STF

LDF||STF Parallel LDF and STF 13-122 Example LDF *AR2 – – (1),R1 || STF R3,*AR4++(IR1) Before Instruction After Instruction R1 00 0000 0000 R1 07 0C80 0000 R3 05 7B40 0000 R3 05 7B40 0000 AR2 80 98E7 AR2 80 98E6 AR4 80 9900 AR4 80 9910 IR1 10 IR1 10 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V ...

Page 581 - Load Integer

Load Integer LDI 13-123 Assembly Language Instructions Syntax LDI src, dst Operation src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 0 0 0 0 dst src G D...

Page 583 - Load Integer Conditionally; LDIcond

Load Integer Conditionally LDIcond 13-125 Assembly Language Instructions Syntax LDI cond src, dst Operation If cond is true: src → dst, Else: dst is unchanged. Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU r...

Page 584 - Auxiliary Register Arithmetic

LDIcond Load Integer Conditionally 13-126 Example LDIZ *ARO++,R6 Before Instruction After Instruction R6 00 0000 0FE2 R6 00 0000 0FE2 AR0 80 98F0 AR0 80 98F1 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098F0h 027C 8098F0h 027C 4,066 4,066 636 636 Note: Auxiliary Regi...

Page 585 - Load Integer, Interlocked; LDII

Load Integer, Interlocked LDII 13-127 Assembly Language Instructions Syntax LDII src, dst Operation Signal interlocked operationsrc → dst Operands src general addressing modes (G): 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 0 0 1 0 dst...

Page 588 - Parallel LDI and LDI

LDI||LDI Parallel LDI and LDI 13-130 Example LDI *–AR1(1),R7 || LDI *AR7++(IR0),R1 Before Instruction After Instruction R1 00 0000 0000 R1 00 0000 02EE R7 00 0000 0000 R7 00 0000 00FA AR1 80 9826 AR1 80 9826 AR7 80 98C8 AR7 80 98D8 IR0 10 IR0 10 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V ...

Page 590 - Parallel LDI and STI

LDI||STI Parallel LDI and STI 13-132 Example LDI *–AR1(1),R2 || STI R7,*AR5++(IR0) Before Instruction After Instruction R2 00 0000 0000 R2 00 0000 00DC R7 00 0000 0035 R7 00 0000 0035 AR1 80 98E7 AR1 80 98E7 AR5 80 982C AR5 80 9834 IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 ...

Page 591 - Load Floating-Point Mantissa; LDM

Load Floating-Point Mantissa LDM 13-133 Assembly Language Instructions Syntax LDM src, dst Operation src (man) → dst (man) Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (R n, 0 ≤ n ≤ 7) Opcode 31 2...

Page 592 - Load Data-Page Pointer

LDP Load Data-Page Pointer 13-134 Syntax LDP src, DP Operation src → data-page pointer Operands src is the 8 MSBs of the absolute 24-bit source address (src). The “DP” in the operand is optional. Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 src Description This pseudo-...

Page 593 - Divide Clock by 16

Divide Clock by 16 LOPOWER 13-135 Assembly Language Instructions Syntax LOPOWER (supported by: ’LC31 and ’C32, ’C31 silicon revision 5.0 or greater, ’C30 silicon revision 7.0 or greater) Operation H1 → H1/16 Operands None Opcode 31 23 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0...

Page 594 - LSH; Logical Shift

LSH Logical Shift 13-136 Syntax LSH count, dst Operation If count ≥ 0: dst << count → dst Else: dst >> |count | → dst Operands count general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 31 24 23 16 8...

Page 596 - Description

LSH3 Logical Shift, 3-Operand 13-138 Syntax LSH3 count, src, dst Operation If count ≥ 0: src << count → dst Else: src >> |count | → dst Operands src 3-operand addressing modes (T): 0 0 any CPU register 0 1 indirect ( disp = 0, 1, IR0, IR1) 1 0 any CPU register 1 1 indirect ( disp = 0, 1,...

Page 600 - Parallel LSH3 and STI

LSH3||STI Parallel LSH3 and STI 13-142 Logical right shift: 0 → src2 → C If the count operand is 0, no shift is performed, and the carry bit is set to 0. The count operand is assumed to be a 7-bit signed integer, and the src2 and dst1 operands are assumed to be unsigned integers. All registers are r...

Page 603 - Restore Clock to Regular Speed; MAXSPEED

Restore Clock to Regular Speed MAXSPEED 13-145 Assembly Language Instructions Syntax MAXSPEED (supported by ’C31, ’C32, ’C31 silicon revision 5.0 or greater, ’C30 silicon revision 7.0 or greater) Operation H1/16 → H1 Operands None Opcode 31 23 16 8 7 0 15 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 604 - Multiply Floating-Point Value

MPYF Multiply Floating-Point Value 13-146 Syntax MPYF src, dst Operation dst × src → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (R n, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 0 1 0 0...

Page 607 - srcA; Operands; parallel addressing modes (0

Parallel MPYF3 and ADDF3 MPYF3||ADDF3 13-149 Assembly Language Instructions Syntax MPYF3 srcA, srcB, dst1 || ADDF3 srcC, srcD, dst2 Operation srcA × srcB → dst1 || srcC + srcD → dst2 Operands srcAsrcBsrcCsrcD Any two indirect ( disp = 0, 1 IR0, IR1) Any two register (0 v R n v 7) dst1 register ( d1)...

Page 608 - Parallel MPYF3 and ADDF3

MPYF3||ADDF3 Parallel MPYF3 and ADDF3 13-150 This instruction’s operands have been augmented in the following devices: - ’C31 silicon version 6.0 or greater - ’C32 silicon version 2.0 or greater srcA, srcB, srcC, srcD can be one of the following combinations: Register (0 v R n v 7) Indirect ( disp =...

Page 610 - src3 and src4 are in internal memory

MPYF3||ADDF3 Parallel MPYF3 and ADDF3 13-152 Example MPYF3 *AR5++(1),* – – AR1(IR0),R0 || ADDF3 R5,R7,R3 Note: Cycle Count One cycle if: - src3 and src4 are in internal memory - src3 is in internal memory and src4 is in external memory Two cycles if: - src3 is in external memory and src4 is in inter...

Page 612 - Parallel MPYF3 and STF

MPYF3||STF Parallel MPYF3 and STF 13-154 Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF 1 if a floating-point underflow occurs; 0 unchanged otherwise LV 1 if a floating-point overflow occurs; unchanged otherwise UF 1 if a floating-point underflow occu...

Page 615 - Opcode

Parallel MPYF3 and SUBF3 MPYF3||SUBF3 13-157 Assembly Language Instructions Opcode 31 24 23 16 8 7 0 15 1 0 0 0 0 1 src4 src3 P src1 src2 d1 d2 Description A floating-point multiplication and a floating-point subtraction are performedin parallel. All registers are read at the beginning and loaded at...

Page 616 - Parallel MPYF3 and SUBF3

MPYF3||SUBF3 Parallel MPYF3 and SUBF3 13-158 Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF 1 if a floating-point underflow occurs; unchanged otherwise LV 1 if a floating-point overflow occurs; unchanged otherwise UF 1 if a floating-point underflow oc...

Page 617 - Multiply Integer; MPYI

Multiply Integer MPYI 13-159 Assembly Language Instructions Syntax MPYI src, dst Operation dst × src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 0 1 1 0...

Page 622 - Parallel MPYI3 and ADDI3

MPYI3||ADDI3 Parallel MPYI3 and ADDI3 13-164 This instruction’s operands have been augmented in the following devices: - ’C31 silicon version 6.0 or greater - ’C32 silicon version 2.0 or greater srcA, srcB, srcC, srcD can be one of the following combinations: Register (0 v R n v 7) Indirect ( disp =...

Page 624 - Parallel MPYl3 and ADD13

MPYl3||ADDl3 Parallel MPYl3 and ADD13 13-166 Before Instruction After Instruction R0 00 0000 0000 R0 00 0000 07D0 R3 00 0000 0000 R3 00 0000 0000 R4 00 0000 0064 R4 00 0000 0064 R7 00 0000 0014 R7 00 0000 0014 AR3 80 981F AR3 80 981F AR5 80 996E AR5 80 996D LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z ...

Page 626 - Parallel MPYl3 and STI

MPYI3||STI Parallel MPYl3 and STI 13-168 Status Bits These condition flags are modified only if the destination register is R7 – R0. LUF Unaffected LV 1 if an integer overflow occurs; unchanged otherwise UF 0 N 1 if a negative result is generated; 0 otherwise Z 1 if a 0 result is generated; 0 otherw...

Page 628 - Parallel MPYI3 and SUBI3

MPYI3||SUBI3 Parallel MPYI3 and SUBI3 13-170 This instruction’s operands have been augmented in the following devices: - ’C31 silicon version 6.0 or greater - ’C32 silicon version 2.0 or greater srcA, srcB, srcC, srcD can be one of the following combinations: Register (0 v R n v 7) Indirect ( disp =...

Page 631 - Negative Integer With Borrow; NEGB

Negative Integer With Borrow NEGB 13-173 Assembly Language Instructions Syntax NEGB src, dst Operation 0 – src – C → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0...

Page 632 - NEGF; Negate Floating-Point Value

NEGF Negate Floating-Point Value 13-174 Syntax NEGF src, dst Operation 0 – src → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 1 1 1 0 dst ...

Page 634 - Parallel NEGF and STF

NEGF||STF Parallel NEGF and STF 13-176 Syntax NEGF src2, dst1 || STF src3, dst2 Operation 0 – src2 → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n1, 0 ≤ n1 ≤ 7) src3 register (R n2, 0 ≤ n2 ≤ 7) dst2 indirect ( disp = 0, 1, IR0, IR1) This instruction’s operand...

Page 635 - Data Loads and Stores, on page 8-24 for the effects

Parallel NEGF and STF NEGF||STF 13-177 Assembly Language Instructions Example NEGF *AR4 – – (1),R7 || STF R2,*++AR5(1) Before Instruction After Instruction R2 07 33C0 0000 R2 07 33C0 0000 R7 00 0000 0000 R7 05 84C0 0000 AR4 80 98E1 AR4 80 98E0 AR5 80 9803 AR5 80 9804 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 ...

Page 636 - NEGI; Negate Integer

NEGI Negate Integer 13-178 Syntax NEGI src, dst Operation 0 – src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 0 0 0 1 dst G src Description The differen...

Page 638 - Parallel NEGI and STI

NEGI||STI Parallel NEGI and STI 13-180 Example NEGI *–AR3,R2 || STI R2,*AR1++ Before Instruction After Instruction R2 00 0000 0019 R2 00 FFFF FF24 AR1 80 98A5 AR1 80 98A6 AR3 80 982F AR3 80 982F LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 0 C 0 C 1 Data memory 80982Eh 0DC 80982Eh 0DC 8098A...

Page 639 - No Operation; NOP

No Operation NOP 13-181 Assembly Language Instructions Syntax NOP src Operation No ALU or multiplier operations.AR n is modified if src is specified in indirect mode. Operands src general addressing modes (G): 0 0 register (no operation) 1 0 indirect (modify AR n, 0 ≤ n ≤ 7) (disp = 0–255, IR0, IR1)...

Page 640 - NORM; Normalize

NORM Normalize 13-182 Syntax NORM src, dst Operation norm ( src) → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 1 0 0 1 dst src G Description The src operand is assume...

Page 642 - Bitwise-Logical Complement

NOT Bitwise-Logical Complement 13-184 Syntax NOT src, dst Operation ∼ src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 1 0 1 1 dst src G Description The ...

Page 644 - Parallel NOT and STI

NOT||STI Parallel NOT and STI 13-186 Syntax NOT src2, dst1 || STI src3, dst2 Operation ∼ src2 → dst1 || src3 → dst2 Operands src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n1, 0 ≤ n1 ≤ 7) src3 register (R n2, 0 ≤ n2 ≤ 7) dst2 indirect ( disp = 0, 1, IR0, IR1) This instruction’s operands hav...

Page 646 - OR

OR Bitwise-Logical OR 13-188 Syntax OR src, dst Operation dst OR src → dst Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate (not sign-extended) dst any CPU register Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 0 0 0 0 dst src G D...

Page 650 - Parallel OR3 and STI

OR3||STI Parallel OR3 and STI 13-192 Syntax OR3 src2, src1, dst1 || STI src3, dst2 Operation src1 OR src2 → dst1 | src3 → dst2 Operands src1 register (R n1, 0 ≤ n1 ≤ 7) src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n2, 0 ≤ n2 ≤ 7) src3 register (R n3, 0 ≤ n3 ≤ 7) dst2 indirect ( disp = 0, ...

Page 652 - POP; Pop Integer; POP R3

POP Pop Integer 13-194 Syntax POP dst Operation *SP– – → dst Operands dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 0 1 0 1 dst 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description The top of the current system stack is popped and loaded into the dst register (32 LSBs). The top of t...

Page 653 - Pop Floating-Point Value; POPF; POPF R4

Pop Floating-Point Value POPF 13-195 Assembly Language Instructions Syntax POPF dst Operation *SP– – → dst1 Operands dst register (Rn, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 0 1 1 1 dst 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description The top of the current system stack (32 MSBs) is poppe...

Page 654 - PUSH; PUSH Integer; PUSH R6

PUSH PUSH Integer 13-196 Syntax PUSH src Operation src → *++SP Operands src register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 1 1 0 1 src 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description The contents of the src register (32 LSBs) are pushed on the current system stack. The src is assu...

Page 655 - PUSH Floating-Point Value; PUSHF; PUSHF R2

PUSH Floating-Point Value PUSHF 13-197 Assembly Language Instructions Syntax PUSHF src Operation src → *++SP Operands src register (Rn, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 0 0 0 0 1 1 1 1 1 src 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description The contents of the src register (32 MSBs) are pushed...

Page 656 - RETIcond; Return From Interrupt Conditionally

RETIcond Return From Interrupt Conditionally 13-198 Syntax RETI cond Operation If cond is true: *SP – – → PC 1 → ST (GIE). Else, continue. Operands None Opcode 31 24 23 16 8 7 0 15 0 1 1 1 1 0 0 0 0 cond 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description A conditional return is performed. If the cond...

Page 657 - RETINZ

Return From Interrupt Conditionally RETIcond 13-199 Assembly Language Instructions Example RETINZ Before Instruction After Instruction PC 0456 PC 0123 SP 809830 SP 80982F ST 0 ST 2000 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809830h 123 809830h 123

Page 658 - RETScond; Return From Subroutine Conditionally

RETScond Return From Subroutine Conditionally 13-200 Syntax RETS cond Operation If cond is true: *SP– – → PC. Else, continue. Operands None Opcode 31 24 23 16 8 7 0 15 0 1 1 1 1 0 0 1 0 cond 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description A conditional return is performed. If the condition is true...

Page 659 - RETSGE

Return From Subroutine Conditionally RETScond 13-201 Assembly Language Instructions Example RETSGE Before Instruction After Instruction PC 0123 PC 0456 SP 80983C SP 80983B LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80983Ch 456 80983Ch 456

Page 660 - RND; Round Floating-Point Value

RND Round Floating-Point Value 13-202 Syntax RND src, dst Operation rnd( src) → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 1 0 0 0 dst s...

Page 661 - BZUF Instruction

Round Floating-Point Value RND 13-203 Assembly Language Instructions Example RND R5,R2 Before Instruction After Instruction R2 00 0000 0000 R2 07 33C1 6F00 R5 07 33C1 6EEF R5 07 33C1 6EEF LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 1.79755599e+02 1.79755599e+02 1.79755600e+02 Not...

Page 662 - ROL; Rotate Left

ROL Rotate Left 13-204 Syntax ROL dst Operation dst left-rotated 1 bit → dst Operands dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 1 0 1 0 dst 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Description The contents of the dst operand are left rotated one bit and loaded into the dst regis...

Page 663 - Rotate Left Through Carry; ROLC; ROLC R3

Rotate Left Through Carry ROLC 13-205 Assembly Language Instructions Syntax ROLC dst Operation dst left-rotated one bit through carry bit → dst Operands dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 0 1 0 0 dst 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Description The contents of the...

Page 665 - Rotate Right; ROR

Rotate Right ROR 13-207 Assembly Language Instructions Syntax ROR dst Operation dst right-rotated one bit through carry bit → dst Operands dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 0 1 1 0 dst 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Description The contents of the dst operand a...

Page 666 - RORC; Rotate Right Through Carry; RORC R4

RORC Rotate Right Through Carry 13-208 Syntax RORC dst Operation dst right-rotated one bit through carry bit → dst Operands dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 1 1 0 0 dst 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Description The contents of the dst operand are right rotate...

Page 667 - Repeat Block; RPTB

Repeat Block RPTB 13-209 Assembly Language Instructions Syntax RPTB src Operation src → RE 1 → ST (RM) Next PC → RS Operands src long-immediate addressing mode Opcode 31 24 23 16 8 7 0 15 0 1 1 0 0 0 0 1 src Description RPTB allows a block of instructions to be repeated RC register + 1 times with-ou...

Page 669 - Repeat Single Instruction; RPTS

Repeat Single Instruction RPTS 13-211 Assembly Language Instructions Syntax RPTS src Operation src → RC 1 → ST (RM) 1 → S Next PC → RS Next PC → RE Operands src general addressing modes (G): 0 0 register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate Opcode 31 24 23 16 8 7 0 15 0 0 0...

Page 670 - RPTS AR5; DB

RPTS Repeat Single Instruction 13-212 Example RPTS AR5 Before Instruction After Instruction AR5 00 00FF AR5 00 00FF PC 0123 PC 0124 RC 0 RC 0FF RE 0 RE 124 RS 0 RS 124 ST 0 ST 100 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Because the block-repeat modes modify the program counte...

Page 671 - SIGI

Signal, Interlocked SIGI 13-213 Assembly Language Instructions Syntax SIGI Operation Signal interlocked operation.Wait for interlock acknowledge.Clear interlock. Operands None Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description An interlocked opera...

Page 672 - Store Floating-Point Value

STF Store Floating-Point Value 13-214 Syntax STF src, dst Operation src → dst Operands src register (Rn, 0 ≤ n ≤ 7) dst general addressing modes (G): 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 0 0 0 1 src G dst Description The src register is loaded into t...

Page 676 - Parallel Store Floating-Point Value

STF||STF Parallel Store Floating-Point Value 13-218 Example STF R4,*AR3 – – || STF R3,*++AR5 Before Instruction After Instruction R3 07 33C0 0000 R3 07 33C0 0000 R4 07 0C80 0000 R4 07 0C80 0000 AR3 80 9835 AR3 80 9834 AR5 80 99D2 AR5 80 99D3 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C ...

Page 677 - Store Integer

Store Integer STI 13-219 Assembly Language Instructions Syntax STI src, dst Operation src → dst Operands src register (Rn, 0 ≤ n ≤ 27) dst general addressing modes (G): 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 1 0 0 1 src G dst Description The src regist...

Page 678 - STII; Store Integer, Interlocked

STII Store Integer, Interlocked 13-220 Syntax STII src, dst Operation src → dst Signal end of interlocked operation Operands src register (Rn, 0 ≤ n ≤ 27) dst general addressing modes (G): 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 1 0 1 1 src G dst Descri...

Page 680 - Parallel STI and STI

STI||STI Parallel STI and STI 13-222 Example STI R0,*++AR2(IR0) || STI R5,*AR0 Before Instruction After Instruction R0 00 0000 00DC R0 00 0000 00DC R5 00 0000 0035 R5 00 0000 0035 AR0 80 98D3 AR0 80 98D3 AR2 80 9830 AR2 80 9838 IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 ...

Page 681 - Subtract Integer With Borrow; SUBB

Subtract Integer With Borrow SUBB 13-223 Assembly Language Instructions Syntax SUBB src, dst Operation dst – src – C → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 ...

Page 684 - SUBC; Subtract Integer Conditionally

SUBC Subtract Integer Conditionally 13-226 Syntax SUBC src, dst Operation If ( dst – src ≥ 0): ( dst – src << 1) OR 1 → dst Else: dst << 1 → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst re...

Page 686 - SUBF; Subtract Floating-Point Value

SUBF Subtract Floating-Point Value 13-228 Syntax SUBF src, dst Operation dst – src → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 0 1 1 1 1 ...

Page 690 - Parallel SUBF3 and STF

SUBF3||STF Parallel SUBF3 and STF 13-232 Syntax SUBF3 src1, src2, dst1 || STF src3, dst2 Operation src2 – src1 → dst1 || src3 → dst2 Operands src1 register (R n1, 0 ≤ n1 ≤ 7) src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n2, 0 ≤ n2 ≤ 7) src3 register (R n3, 0 ≤ n3 ≤ 7) dst2 indirect ( disp...

Page 692 - SUBI; Subtract Integer

SUBI Subtract Integer 13-234 Syntax SUBI src, dst Operation dst – src → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 1 0 0 0 0 dst G src D...

Page 696 - Parallel SUBI3 and STI

SUBI3||STI Parallel SUBI3 and STI 13-238 Example SUBI3 R7,*+AR2(IR0),R1 || STI R3,*++AR7 Before Instruction After Instruction R1 00 0000 0000 R1 00 0000 00C8 R3 00 0000 0035 R3 00 0000 0035 R7 00 0000 0014 R7 00 0000 0014 AR2 80 982F AR2 80 982F AR7 80 983B AR7 80 983C IR0 10 IR0 10 LUF 0 LUF 0 LV 0...

Page 697 - Subtract Reverse Integer With Borrow; SUBRB

Subtract Reverse Integer With Borrow SUBRB 13-239 Assembly Language Instructions Syntax SUBRB src, dst Operation src – dst – C → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 27) ...

Page 698 - SUBRF; Subtract Reverse Floating-Point Value

SUBRF Subtract Reverse Floating-Point Value 13-240 Syntax SUBRF src, dst Operation src – dst → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 7) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 7) Opcode 31 24 23 16 8 7 0 15 0 0 0 1 ...

Page 699 - Subtract Reverse Integer; SUBRI

Subtract Reverse Integer SUBRI 13-241 Assembly Language Instructions Syntax SUBRI src, dst Operation src – dst → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 ...

Page 700 - SWI; Software Interrupt

SWI Software Interrupt 13-242 Syntax SWI Operation Performs an emulation interrupt Operands None Opcode 31 24 23 16 8 7 0 15 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description The SWI instruction performs an emulator interrupt. This is a reserved instruc-tion and shoul...

Page 701 - Trap Conditionally; TRAPcond

Trap Conditionally TRAPcond 13-243 Assembly Language Instructions Syntax TRAP cond N Operation 0 → ST(GIE) If cond is true: Next PC → *++SP, Trap vector N → PC. Else: Set ST(GIE) to original state.Continue. Operands N (0 ≤ N ≤ 31) Opcode 31 24 23 16 8 7 0 15 0 1 1 1 0 0 0 0 1 cond 0 0 0 0 0 0 0 0 0 ...

Page 703 - Test Bit Fields; TSTB

Test Bit Fields TSTB 13-245 Assembly Language Instructions Syntax TSTB src, dst Operation dst AND src Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7 0 15 0 0...

Page 707 - Bitwise-Exclusive OR; XOR

Bitwise-Exclusive OR XOR 13-249 Assembly Language Instructions Syntax XOR src, dst Operation dst XOR src → dst Operands src general addressing modes (G): 0 0 register (R n, 0 ≤ n ≤ 27) 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst register (Rn, 0 ≤ n ≤ 27) Opcode 31 24 23 16 8 7...

Page 710 - Parallel XOR3 and STI; src1 XOR src2

XOR3||STI Parallel XOR3 and STI 13-252 Syntax XOR3 src2, src1, dst1 || STI src3, dst2 Operation src1 XOR src2 → dst1 || src3 → dst2 Operands src1 register (R n1, 0 ≤ n1 ≤ 7) src2 indirect ( disp = 0, 1, IR0, IR1) dst1 register (R n2, 0 ≤ n2 ≤ 7) src3 register (R n3, 0 ≤ n3 ≤ 7) dst2 indirect ( disp ...

Page 712 - Instruction Opcodes; Appendix A

A-1 Appendix A Instruction Opcodes The opcode fields for all TMS320C3x instructions are shown in Table A–1. Bitsin the table marked with a hyphen are defined in the individual instructiondescriptions (see Chapter 13, Assembly Language Instructions). Table A–1, along with the instruction descriptions...

Page 713 - Table A–1. TMS320C3x Instruction Opcodes

Instruction Opcodes A-2 Table A–1. TMS320C3x Instruction Opcodes Instruction 31 30 29 28 27 26 25 24 23 ABSF 0 0 0 0 0 0 0 0 0 ABSI 0 0 0 0 0 0 0 0 1 ADDC 0 0 0 0 0 0 0 1 0 ADDF 0 0 0 0 0 0 0 1 1 ADDI 0 0 0 0 0 0 1 0 0 AND 0 0 0 0 0 0 1 0 1 ANDN 0 0 0 0 0 0 1 1 0 ASH 0 0 0 0 0 0 1 1 1 CMPF 0 0 0 0 0...

Page 718 - This appendix contains the source code for the ’C31 boot loader.; Appendix B

B-1 Appendix A TMS320C31 Boot Loader Source Code This appendix contains the source code for the ’C31 boot loader. Appendix B

Page 724 - Boot-Loader Source Code Description; Appendix C

C-1 Appendix A TMS320C32 Boot Loader Source Code This appendix includes a description of the ’C32 boot loader sequence ofevents and a listing of its source code. Topic Page C.1 Boot-Loader Source Code Description C-2 . . . . . . . . . . . . . . . . . . . . . . . . . . C.2 Boot-Loader Source Code Lis...

Page 727 - Boot-Loader Source Code Listing; EPROM; INTERRUPT PIN; SERIAL

Boot-Loader Source Code Listing C-4 C.2 Boot-Loader Source Code Listing *********************************************************************************** C32BOOT – TMS320C32 BOOT LOADER PROGRAM (143 words) March–96* (C) COPYRIGHT TEXAS INSTRUMENTS INCORPORATED, 1994 v.27 *=========================...

Page 734 - Glossary; Appendix D

D-1 Appendix A Glossary A A0–A23: External address pin s for data/program memory or I/O devices. These pins are on the primary bus. address: The location of program code or data stored in memory. addressing mode: The method by which an instruction interprets its oper- ands to acquire the data it nee...

Page 737 - internal interrupt enable register:

Glossary D-4 I IACK: Interrupt acknowledge signal. An output signal indicating that an in- terrupt has been received and that the program counter is fetching theinterrupt vector that will force the processor into an interrupt service rou-tine. IE: See internal interrupt enable register. I/O flag (IO...

Page 740 - short integer format:

Glossary D-7 Glossary S short floating-point format: A 16-bit representation of a floating point num- ber with a 12-bit mantissa and a 4-bit exponent. short floating-point format for external 16-bit data: A 16-bit representa- tion of a floating point number with an 8-bit mantissa and an 8-bit expo-n...

Page 742 - Index

Index Index-1 Index 16-bit-wide configured memory, TMS320C31 11-10 2-operand instruction 13-3 2-operand instruction word 8-25 3-operand addressing modes 2-17, 13-24–13-25 3-operand instruction 13-4 add, integer 13-58 arithmetic shift 13-73 bitwise-exclusive OR 13-250 bitwise-logical ANDN 13-69 OR 13...