Texas Instruments TMS320C2XX - Manuals

Notational Conventions/Information About Cautions v Read This First Notational Conventions This document uses the following conventions: - Program listings and program examples are shown in a special typeface . Here is a segment of a program listing: OUTPUT LDP #6 ;select data page 6 BLDD #300, 20h ...

Related Documentation From Texas Instruments vi Related Documentation From Texas Instruments This subsection describes related TI  documents that can be ordered by calling the Texas Instruments Literature Response Center at (800) 477–8924.When ordering, please identify the document by its title and...

Related Documentation From Texas Instruments vii Read This First TMS320C2xx Simulator Getting Started (literature number SPRU137) describes how to install the TMS320C2xx simulator and the C sourcedebugger for the ’C2xx. The installation for MS-DOS  , PC-DOS  , SunOS  , Solaris  , and HP-UX  sys...

Related Articles viii Related Articles “A Greener World Through DSP Controllers”, Panos Papamichalis, DSP & Multimedia Technology, September 1994. “A Single-Chip Multiprocessor DSP for Image Processing—TMS320C80”, Dr. Ing. Dung Tu, Industrie Elektronik, Germany, March 1995. “Application Guide wi...

Trademarks x Trademarks TI, 320 Hotline On-line, XDS510, XDS510PP, XDS510WS, and XDS511 aretrademarks of Texas Instruments Incorporated. HP-UX is a trademark of Hewlett-Packard Company. Intel is a trademark of Intel Corporation. MS-DOS and Windows are registered trademarks of Microsoft Corporation. ...

If You Need Assistance xi Read This First If You Need Assistance. . . - World-Wide Web Sites TI Online http://www.ti.com Semiconductor Product Information Center (PIC) http://www.ti.com/sc/docs/pic/home.htm DSP Solutions http://www.ti.com/dsps 320 Hotline On-line t http://www.ti.com/sc/docs/dsps/sup...

Contents xiii Contents 1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summarizes the features of the TMS320 family of products and presents typical applications.Describes the TMS320C2xx DSP ...

Contents xiv 3 Central Processing Unit 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the TMS320C2xx CPU. Includes information about the central arithmetic logic unit,the accumulator, the shifters, the multiplier, and...

Contents xv Contents 5 Program Control 5-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the TMS320C2xx hardware and software features used in controlling program flow,including program-address generation l...

Contents xvi 6.3 Indirect Addressing Mode 6-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Current Auxiliary Register 6-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Indirect Addressing...

Contents xvii Contents 9 Synchronous Serial Port 9-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the operation and control of the TMS320C2xx on-chip synchronous serial port. 9.1 Overview of the Synchronous Serial Port 9-...

Contents xviii 10.3 Controlling and Resetting the Port 10-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Asynchronous Serial Port Control Register (ASPCR) 10-7 . . . . . . . . . . . . . . . . . . . . 10.3.2 I/O Status Register (IOSR) 10-10 . . . . . . ...

Contents xix Contents D Submitting ROM Codes to TI D-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Explains the process for submitting custom program code to TI for designing masks for theon-chip ROM on a TMS320 DSP. E Design Consideratio...

Figures xx Figures 1–1 TMS320 Family 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Overall Block Diagram of the ’C2xx 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Tables xxiii Contents Tables 1–1 Typical Applications for TMS320 DSPs 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 ’C2xx Generation Summary 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1...

Examples xxv Contents Examples 4–1 An Interrupt Service Routine Supporting INT1 and HOLD 4-28 . . . . . . . . . . . . . . . . . . . . . . . . . 6–1 RPT Instruction Using Short-Immediate Addressing 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 ADD Instruction Using Long-Immedi...

Notes, Cautions, and Warnings xxvi Cautions Obtain the Proper Timing Information 4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Do Not Write to Test/Emulation Addresses 4-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

1-1 Introduction Introduction The TMS320C2xx (’C2xx) is one of several fixed-point generations of DSPsin the TMS320 family. The ’C2xx is source-code compatible with theTMS320C2x. Much of the code written for the ’C2x can be reassembled to runon a ’C2xx device. In addition, the ’C2xx generation is up...

TMS320 Family 1-2 1.1 TMS320 Family The TMS320 family consists of fixed-point, floating-point, and multiprocessordigital signal processors (DSPs). TMS320 DSPs have an architecture de-signed specifically for real-time signal processing. The following characteris-tics make this family the ideal choice...

TMS320 Family 1-3 Introduction Figure 1–1. TMS320 Family Performance

TMS320 Family 1-4 1.1.2 Typical Applications for the TMS320 Family Table 1–1 lists some typical applications for the TMS320 family of DSPs. TheTMS320 DSPs offer adaptable approaches to traditional signal-processingproblems such as filtering and vocoding. They also support complexapplications that of...

TMS320C2xx Generation 1-5 Introduction 1.2 TMS320C2xx Generation Texas Instruments uses static CMOS integrated-circuit technology to fabricatethe TMS320C2xx DSPs. The architectural design of the ’C2xx is based on thatof the ’C5x. The operational flexibility and speed of the ’C2xx and ’C5x are aresul...

2-1 Architectural Overview Architectural Overview This chapter provides an overview of the architectural structure and compo-nents of the ’C2xx. The ’C2xx DSPs use an advanced, modified Harvard archi-tecture that maximizes processing power by maintaining separate bus struc-tures for program memory a...

2-2 Figure 2–1. Overall Block Diagram of the ’C2xx Program control PRDB PRDB DRDB DRDB DWEB DRAB DWAB PAB DWEB Stack 8 × 16 MUX MSTACK PAR NPAR MUX PC ROM/flash SARAM DARAM B0 DARAM B1, B2 ST0 IMR IFR GREG ST1 MUX Input shifter Multiplier 16 × 16 TREG MUX PREG Product shifter Accumulator Output shif...

’C2xx Bus Structure 2-4 Figure 2–2. Bus Structure Block Diagram B0 DARAM ROM/ flash SARAM B1, B2 DARAM Memorymapped registers PAB DRAB DWAB PRDB DRDB DWEB Control bus External signals Memory control MULTI_DSP CLOCK/PLL Interrupts JTAG/TEST Central processing unit (CPU) Auxiliary registers registers ...

Central Processing Unit 2-5 Architectural Overview 2.2 Central Processing Unit The CPU is the same on all the ’C2xx devices. The ’C2xx CPU contains: - A 32-bit central arithmetic logic unit (CALU) - A 32-bit accumulator - Input and output data-scaling shifters for the CALU - A 16-bit × 16-bit multip...

Central Processing Unit 2-6 2.2.3 Multiplier The on-chip multiplier performs 16-bit × 16-bit 2s-complement multiplication with a 32-bit result. In conjunction with the multiplier, the ’C2xx uses the 16-bittemporary register (TREG) and the 32-bit product register (PREG). The TREGalways supplies one o...

Memory and I/O Spaces 2-7 Architectural Overview 2.3 Memory and I/O Spaces The ’C2xx memory is organized into four individually selectable spaces: pro-gram, local data, global data, and I/O. These spaces form an address rangeof 224K words. All ’C2xx devices include 288 words of dual-access RAM (DARA...

Memory and I/O Spaces 2-9 Architectural Overview 2.3.4 Flash Memory Some of the ’C2xx devices feature on-chip blocks of flash memory, which iselectronically erasable and programmable, and non-volatile. Each block offlash memory will have a set of control registers that allow for erasing, pro-grammin...

Program Control 2-10 2.4 Program Control Several features provide program control: - The program controller of the CPU decodes instructions, manages thepipeline, stores the status of operations, and decodes conditional opera-tions. Elements involved in program control are the program counter, thesta...

On-Chip Peripherals 2-11 Architectural Overview 2.5 On-Chip Peripherals All the ’C2xx devices have the same CPU, but different on-chip peripherals areconnected to their CPUs. The on-chip peripherals featured on the ’C2xx de-vices are: - Clock generator (an oscillator and a phase lock loop circuit) -...

On-Chip Peripherals 2-12 2.5.5 General-Purpose I/O Pins The ’C2xx has pins that provide general-purpose input or output signals. All’C2xx devices have a general-purpose input pin, BIO, and a general-purposeoutput pin, XF. Except for the ’C209, the ’C2xx devices also have pins IO0, IO1,IO2, and IO3, ...

Scanning-Logic Circuitry 2-13 Architectural Overview 2.6 Scanning-Logic Circuitry The ’C2xx has JTAG scanning-logic circuitry that is compatible with IEEEStandard 1149.1. This circuitry is used for emulation and testing purposesonly. The serial scan path is used to test pin-to-pin continuity as well...

3-1 Central Processing Unit This chapter describes the main components of the central processing unit(CPU). First, this chapter describes three fundamental sections of the CPU(see Figure 3–1): - Input scaling section - Multiplication section - Central arithmetic logic section The chapter then descri...

3-2 Figure 3–1. Block Diagram of the Input Scaling, Central Arithmetic Logic, and Multiplication Sections of the CPU 32 Input shifter (32 bits) 16 32 Output shifter (32 bits) 32 C Accumulator CALU 32 32 MUX 32 16 MUX MUX 16 16 PREG Multiplier 16 × 16 16 Data write bus (DWEB) Data read bus (DRDB) TRE...

Input Scaling Section 3-3 Central Processing Unit 3.1 Input Scaling Section A 32-bit input data-scaling shifter (input shifter) aligns a 16-bit value comingfrom memory to the 32-bit CALU. This data alignment is necessary for data-scaling arithmetic as well as aligning masks for logical operations. T...

Multiplication Section 3-5 Central Processing Unit 3.2 Multiplication Section The ’C2xx uses a 16-bit × 16-bit hardware multiplier that can produce a signed or unsigned 32-bit product in a single machine cycle. As shown in Figure 3–5,the multiplication section consists of: - The 16-bit temporary reg...

Multiplication Section 3-6 Inputs. The multiplier accepts two 16-bit inputs: - One input is always from the 16-bit temporary register (TREG). The TREGis loaded before the multiplication with a data-value from the data read bus(DRDB). - The other input is one of the following: J A data-memory value f...

Multiplication Section 3-7 Central Processing Unit Table 3–1. Product Shift Modes for the Product-Scaling Shifter ÁÁ ÁÁ PM ÁÁÁÁ ÁÁÁÁ Shift ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Comments ÁÁ ÁÁ 00 ÁÁÁÁ ÁÁÁÁ no shift ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Product sent to CALU or data write bus (DWEB...

Central Arithmetic Logic Section 3-8 3.3 Central Arithmetic Logic Section Figure 3–6 shows the main components of the central arithmetic logic section,which are: - The central arithmetic logic unit (CALU), which implements a wide rangeof arithmetic and logic functions. - The 32-bit accumulator (ACC)...

Central Arithmetic Logic Section 3-9 Central Processing Unit 3.3.1 Central Arithmetic Logic Unit (CALU) The central arithmetic logic unit (CALU), implements a wide range of arithme-tic and logic functions, most of which execute in a single clock cycle. Thesefunctions can be grouped into four categor...

Central Arithmetic Logic Section 3-10 Status bits. Four status bits are associated with the accumulator: - Carry bit (C). C (bit 9 of status register ST1) is affected during: J Additions to and subtractions from the accumulator: C = 0 When the result of a subtraction generates a borrow. When the res...

Central Arithmetic Logic Section 3-11 Central Processing Unit 3.3.3 Output Data-Scaling Shifter The output data-scaling shifter (output shifter) has a 32-bit input connected tothe 32-bit output of the accumulator and a 16-bit output connected to the databus. The shifter copies all 32-bits of the acc...

Auxiliary Register Arithmetic Unit (ARAU) 3-12 3.4 Auxiliary Register Arithmetic Unit (ARAU) The CPU also contains the auxiliary register arithmetic unit (ARAU), an arith-metic unit independent of the central arithmetic logic unit (CALU). The mainfunction of the ARAU is to perform arithmetic operati...

Auxiliary Register Arithmetic Unit (ARAU) 3-13 Central Processing Unit The eight auxiliary registers (AR7–AR0) provide flexible and powerful indirectaddressing. Any location in the 64K data memory space can be accessed us-ing a 16-bit address contained in an auxiliary register. For the details of in...

Status Registers ST0 and ST1 3-15 Central Processing Unit 3.5 Status Registers ST0 and ST1 The ’C2xx has two status registers, ST0 and ST1, which contain status andcontrol bits. These registers can be stored into and loaded from data memory,thus allowing the status of the machine to be saved and res...

Status Registers ST0 and ST1 3-16 Table 3–2. Bit Fields of Status Registers ST0 and ST1 Name Description ARB Auxiliary register pointer buffer. Whenever the auxiliary register pointer (ARP) is loaded, the pre-vious ARP value is copied to the ARB, except during an LST (load status register) instructi...

Status Registers ST0 and ST1 3-17 Central Processing Unit Table 3–2. Bit Fields of Status Registers ST0 and ST1 (Continued) Name Description OVM Overflow mode bit. OVM determines how overflows in the CALU are handled. The SETC andCLRC instructions set and clear this bit, respectively. An LST instruc...

4-1 Memory and I/O Spaces Memory and I/O Spaces This chapter describes the ’C2xx memory configuration options and the ad-dress maps of the individual ’C2xx devices. It also illustrates typical ways ofinterfacing the ’C2xx with external memory and external input/output (I/O)devices. Each ’C2xx device...

Overview of the Memory and I/O Spaces 4-2 4.1 Overview of the Memory and I/O Spaces The ’C2xx address map is organized into four individually selectable spaces: - Program memory (64K words) contains the instructions to be executed,as well as data used during program execution. - Local data memory (6...

Overview of the Memory and I/O Spaces 4-3 Memory and I/O Spaces 4.1.1 Pins for Interfacing to External Memory and I/O Spaces The pins for interfacing to external memory and I/O space, described inTable 4–1, are of four main types: - External buses. Sixteen signals (A15–A0) are available for passing ...

Program Memory 4-5 Memory and I/O Spaces 4.2 Program Memory Program-memory space holds the code for applications; it can also hold tableinformation and constant operands. The program-memory space addressesup to 64K 16-bit words. Every ’C2xx device contains a DARAM block B0 thatcan be configured as p...

Program Memory 4-6 Figure 4–1. Interface With External Program Memory ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ A0A1A2A3A4A5A6A7A8A9 A10 A11 A12 D0D1D2D...

Local Data Memory 4-7 Memory and I/O Spaces 4.3 Local Data Memory The local data-memory space addresses up to 64K 16-bit words. Every ’C2xxdevice has three on-chip DARAM blocks: B0, B1, and B2. Block B0 has 256words that are configurable as either data locations or program locations.Blocks B1 (256 w...

Local Data Memory 4-8 4.3.1 Data Page 0 Address Map Table 4–2 shows the address map of data page 0 (addresses 0000h–007Fh).Note the following: - Three memory-mapped registers can be accessed with zero wait states: J Interrupt mask register (IMR) J Global memory allocation register (GREG) J Interrupt...

Local Data Memory 4-9 Memory and I/O Spaces 4.3.2 Interfacing With External Local Data Memory While the ’C2xx is accessing the on-chip local data-memory blocks, the exter-nal memory signals DS and STRB are in high impedance. The external busesare active only when the ’C2xx is accessing locations wit...

Local Data Memory 4-10 Figure 4–3. Interface With External Local Data Memory ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ A0A1A2A...

Global Data Memory 4-11 Memory and I/O Spaces 4.4 Global Data Memory Addresses in the upper 32K words (8000h–FFFFh) of local data memory canbe used for global data memory. The global memory allocation register(GREG) determines the size of the global data-memory space, which is be-tween 256 and 32K w...

Global Data Memory 4-12 As an example of configuring global memory, suppose you want to designate8K addresses as global addresses. You would write the 8-bit value 11100000 2 to the eight LSBs of the GREG (see Figure 4–4). This would designate ad-dresses E000h–FFFFh of data memory as global data addr...

Global Data Memory 4-13 Memory and I/O Spaces toggled between local memory and global memory. For example, in the systemof Figure 4–6, when GREG = XXXXXXXX00000000 2 (no global memory), the local data RAM is fully accessible; when GREG = XXXXXXXX10000000 2 (all global memory), the local data RAM is ...

Boot Loader 4-14 4.5 Boot Loader This section applies to ’C2xx devices that have an on-chip boot loader. Theboot loader is used for booting software from an 8-bit external ROM to a 16-bitexternal RAM at reset (see Figure 4–7). The source for your program is an ex-ternal ROM located in external globa...

Boot Loader 4-15 Memory and I/O Spaces 4.5.2 Connecting the EPROM to the Processor To map the EPROM into the global data space at address 8000h, make thefollowing connections between the processor and the EPROM (refer toFigure 4–8): - Connect the address lines of the processor and the EPROM (see lin...

Boot Loader 4-16 4.5.3 Programming the EPROM Texas Instruments fixed-point development tools provide the utilities to gener-ate the boot ROM code. (For an introduction to the procedure for generatingboot loader code, see Appendix C, Program Examples.) However, should you need to do the programming, ...

Boot Loader 4-17 Memory and I/O Spaces Figure 4–9 shows how to store a 16-bit program into the 8-bit EPROM. A sub-script h (for example, on Word1 h ) indicates the high-byte and a subscript l (for example, on Word1 l ) indicates the low byte. Figure 4–9. Storing the Program in the EPROM 16-Bit Progr...

Boot Loader 4-18 4.5.5 Boot Loader Execution Once the EPROM has been programmed and installed, and the boot loaderhas been enabled, the processor automatically boots the program fromEPROM at startup. If you need to reboot the processor during operation, bringthe RS pin low to cause a hardware reset....

Boot Loader 4-19 Memory and I/O Spaces Figure 4–10. Program Code Transferred From 8-Bit EPROM to 16-Bit RAM 8-Bit EPROM 16-Bit RAM Address 7 0 Address 15 8 7 0 8000h Destination h = 00h 0000h Word1 h Word1 l 8001h Destination l = 00h • Word2 h Word2 l 8002h Length N h • • . • 8003h Length N l • • • ...

Boot Loader 4-20 Figure 4–11. Interrupt Vectors Transferred First During Boot Load 8000h 8-bit EPROM in global data memory 16-bit RAM in program memory 0000h 003Fh 8001h Destination h (00) Destination l (00) Length N h Length N l 8002h 8003h Interrupt vectors Program code Interrupt vectors Program c...

Boot Loader 4-21 Memory and I/O Spaces 4.5.6 Boot Loader Program ********************************************************************************** TMS320C2xx Boot Loader Program ** ** This code sets up and executes boot loader code that loads program ** code from location 8000h in external global d...

I/O Space 4-23 Memory and I/O Spaces 4.6 I/O Space The ’C2xx supports an I/O address range of 64K 16-bit words. Figure 4–12shows the ’C2xx I/O address map. Figure 4–12. I/O Address Map for the ’C2xx FFFFh ’C2xx I/O 0000h FF00h External FEFFh reserved addresses registers and I/O-mapped FF10h FF0Fh Re...

I/O Space 4-24 The map has three main sections of addresses: - Addresses 0000h–FEFFh allow access to off-chip peripherals typicallyused in DSP applications, such as digital-to-analog and analog-to-digitalconverters. - Addresses FF00h–FF0Fh are mapped to on-chip I/O space. These ad-dresses are reserv...

I/O Space 4-26 Figure 4–13. I/O Port Interface Circuitry ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ A0A1A2 A3 D0D1D2D3D4D5D6D7 IS WE 123 645 18161412 975...

Direct Memory Access Using the HOLD Operation 4-27 Memory and I/O Spaces 4.7 Direct Memory Access Using the HOLD Operation The ’C2xx HOLD operation allows direct-memory access to external program,data, and I/O spaces. The process is controlled by two signals: - HOLD. An external device can drive the...

Direct Memory Access Using the HOLD Operation 4-28 Example 4–1. An Interrupt Service Routine Supporting INT1 and HOLD .mmregs ;Include c2xx memory–mapped registers. ICR .set 0FFECh ;Define interrupt control register in I/O space. ICRSHDW .set 060h ;Define ICRSHDW in scratch pad location. * Interrupt...

Direct Memory Access Using the HOLD Operation 4-29 Memory and I/O Spaces Here are three valid methods for exiting the IDLE state, thus deassertingHOLDA and restoring the buses to normal operation: - Cause a rising edge on the HOLD/INT1 pin when MODE = 0. - Assert system reset at the reset pin. - Ass...

Direct Memory Access Using the HOLD Operation 4-30 Figure 4–15. Reset Deasserted Before HOLD Deasserted RS HOLD HOLDA Direct Memory Access Using the HOLD Operation

Device-Specific Information 4-31 Memory and I/O Spaces 4.8 Device-Specific Information For ’C2xx devices other than the ’C209, this section mentions the presenceor absence of the boot loader and HOLD features, shows address maps, andexplains the contents and configuration of the program-memory and d...

Device-Specific Information 4-33 Memory and I/O Spaces DARAM blocks B1 and B2 are fixed, but DARAM block B0 may be mapped toprogram space or data space, depending on the value of the CNF bit (bit 12of status register ST1): - CNF = 0. B0 is mapped to data space and is accessible at data addresses0200...

Device-Specific Information 4-34 Table 4–6. ’C203 Data-Memory Configuration Options CNF DARAM B0 (hex) DARAM B1 (hex) DARAM B2 (hex) External (hex) Reserved (hex) 0 0200–02FF 0300–03FF 0060–007F 0800–FFFF 0000–005F 0080–01FF 0400–07FF 1 – 0300–03FF 0060–007F 0800–FFFF 0000–005F 0080–02FF 0400–07FF 4...

Device-Specific Information 4-37 Memory and I/O Spaces Table 4–7. ’C204 Program-Memory Configuration Options MP/MC CNF ROM (hex) DARAM B0 (hex) External (hex) Reserved (hex) 0 0 0000–0FFF – 1000–FFFF – 0 1 0000–0FFF FF00–FFFF 1000–FDFF FE00–FEFF 1 0 – – 0000–FFFF – 1 1 – FF00–FFFF 0000–FDFF FE00–FEF...

5-1 Program Control This chapter discusses the processes and features involved in controlling theflow of a program on the ’C2xx. Program control involves controlling the order in which one or more blocks ofinstructions are executed. Normally, the flow of a program is sequential: the’C2xx executes in...

Program-Address Generation 5-2 5.1 Program-Address Generation Program flow requires the processor to generate the next program address(sequential or nonsequential) while executing the current instruction. Pro-gram-address generation is illustrated in Figure 5–1 and summarized inTable 5–1. Figure 5–1...

Program-Address Generation 5-3 Program Control Table 5–1. Program-Address Generation Summary ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Operation ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Program-Address Source ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Sequential operation ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ PC (contains program address +1) ÁÁÁÁÁÁÁÁ...

Program-Address Generation 5-4 The ’C2xx can load the PC in a number of ways, to accommodate sequentialand nonsequential program flow. Table 5–2 shows what is loaded to the PCaccording to the code operation performed. Table 5–2. Address Loading to the Program Counter ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Code Operation...

Program-Address Generation 5-5 Program Control - PSHD and POPD. These instructions allow you to build a stack in datamemory for the nesting of subroutines or interrupts beyond eight levels.The PSHD instruction pushes a data-memory value onto the top of thestack. The POPD instruction pops a value fro...

Program-Address Generation 5-6 Figure 5–3. A Pop Operation Before Instruction After Instruction Accumulator Accumulator or memory 82h or memory 45h location location 45h 16h 16h 7h Stack 7h Stack 33h 33h 42h 42h 56h 56h 37h 37h 61h 61h 61h 5.1.3 Micro Stack (MSTACK) The program-address generation lo...

Pipeline Operation 5-7 Program Control 5.2 Pipeline Operation Instruction pipelining consists of a sequence of bus operations that occur dur-ing the execution of an instruction. The ’C2xx pipeline has four independentstages: instruction-fetch, instruction-decode, operand-fetch, and instruction-execu...

Branches, Calls, and Returns 5-8 5.3 Branches, Calls, and Returns Branches, calls, and returns break the sequential flow of instructions by trans-ferring control to another location in program memory. A branch only transfers control to the new location. A call also saves the return address (the addr...

Branches, Calls, and Returns 5-9 Program Control By the time the unconditional call instruction reaches the execute phase of thepipeline, the next two instruction words have already been fetched. These twoinstruction words are flushed from the pipeline so that they are not executed,the return addres...

Conditional Branches, Calls, and Returns 5-10 5.4 Conditional Branches, Calls, and Returns The ’C2xx provides branch, call, and return instructions that will execute onlyif one or more conditions are met. You specify the conditions as operands ofthe conditional instruction. Table 5–3 lists the condi...

Conditional Branches, Calls, and Returns 5-11 Program Control - Group 2. You can select up to three conditions. Each of these conditionsmust be from a different category (A, B, or C); you cannot have two condi-tions from the same category. For example, you can test TC, C, and BIOat the same time, bu...

Conditional Branches, Calls, and Returns 5-13 Program Control RETC, like RET, is a single-word instruction. However, because of the poten-tial PC discontinuity, it operates with the same effective execution time as theconditional branch (BCND) and the conditional call (CC). By the time the condi-tio...

Repeating a Single Instruction 5-14 5.5 Repeating a Single Instruction The ’C2xx repeat (RPT) instruction allows the execution of a single instructionN + 1 times, where N is specified as an operand of the RPT instruction. WhenRPT is executed, the repeat counter (RPTC) is loaded with N. RPTC is thend...

Interrupts 5-15 5.6 Interrupts Interrupts are hardware- or software-driven signals that cause the ’C2xx tosuspend its current program sequence and execute a subroutine. Typically, in-terrupts are generated by hardware devices that need to give data to or takedata from the ’C2xx (for example, A/D and...

Interrupts 5-16 3) Execute the interrupt service routine. Once the interrupt is acknowl- edged, the ’C2xx branches to its corresponding subroutine called an inter-rupt service routine (ISR). The ’C2xx follows the branch instruction youplace at a predetermined address (the vector location) and execut...

Interrupts 5-17 Program Control Table 5–5. ’C2xx Interrupt Locations and Priorities (Continued) ÁÁÁ Á Á Á ÁÁÁ K † ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ VectorLocation ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ Name ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Priority ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Function ÁÁÁ ÁÁÁ 10 ÁÁÁÁÁ ÁÁÁÁÁ 14h ÁÁÁÁÁ ÁÁÁÁÁ INT10 ÁÁÁÁ ÁÁÁÁ –...

Interrupts 5-18 5.6.3 Maskable Interrupts When a maskable interrupt is successfully requested by a hardware device orby an external pin, the corresponding flag or flags are activated. These flagsare activated whether or not the interrupt is later acknowledged by the proces-sor. Two registers on the ...

Interrupts 5-19 Program Control After an interrupt request is received by the CPU, the CPU must decide wheth-er to acknowledge the request. Maskable hardware interrupts are acknowl-edged only after certain conditions are met: - Priority is highest. When more than one hardware interrupt is requesteda...

Interrupts 5-20 Figure 5–6 summarizes how maskable interrupts are handled by the CPU. Figure 5–6. Maskable Interrupt Operation Flow Chart Interrupt request sent to CPU Corresponding IFR flag bit set Interrupts enabled (INTM bit = 0) ? Interrupt unmasked? Interrupt acknowledged Yes Yes No No INTM bit...

Interrupts 5-21 Program Control 1 to the corresponding IFR bit. All pending interrupts can be cleared by writingthe current contents of the IFR back into the IFR. Acknowledgement of ahardware request also clears the corresponding IFR bit. A device reset clearsall IFR bits. Notes: 1) When an interrup...

Interrupts 5-22 Bit 3 RINT — Receive interrupt flag. Bit 3 is tied to the receive interrupt for the synchro-nous serial port. To avoid double interrupts, write a 1 to this bit in the interrupt service routine. RINT = 0 Interrupt RINT is not pending. RINT = 1 Interrupt RINT is pending. Bit 2 TINT — T...

Interrupts 5-24 Bit 0 HOLD/INT1 — HOLD/Interrupt 1 mask. This bit masks or unmasks interrupts re-quested at the HOLD/INT1 pin. HOLD/INT1 = 0 HOLD/INT1 is masked. HOLD/INT1 = 1 HOLD/INT1 is unmasked. 5.6.6 Interrupt Control Register (ICR) The 16-bit interrupt control register (ICR), located at addres...

Interrupts 5-25 Program Control to mask INT3 (prevent the setting of flags FINT3 and INT2/INT3) write a 0 toMINT3. If INT2/INT3 is not set, the CPU has not received and will not acknowl-edge the interrupt request. When INT2/INT3 is set, one or both of the interrupts is pending. To differentiatethe o...

Interrupts 5-26 Figure 5–9 shows the ICR, and bit descriptions follow the figure. Figure 5–9. ’C2xx Interrupt Control Register (ICR) — I/O-Space Address FFECh 15 5 4 3 2 1 0 ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved MODE FINT3 FINT2 MINT3 MINT2 0 R/W–0 R/W1C–0 R/W1C–0 R/W–0 R/W–0 Note: 0 = Always read as...

Interrupts 5-27 Program Control Bit 0 MINT2 — Interrupt 2 mask. This bit masks the external interrupt INT2 or, in conjunc-tion with the INT2/INT3 bit of the IMR, unmasks INT2. MINT2 = 0 INT2 is masked. Neither FINT2 nor bit 1 of the IFR (INT2/INT3) is setby a request on the INT2 pin. MINT2 = 1 INT3 ...

Interrupts 5-28 Note: The INTR instruction does not affect IFR flags. When you use the INTRinstruction to initiate an interrupt that has an associated flag bit in the IFR,the instruction neither sets nor clears the flag bit. No software write operationcan set the IFR flag bits; only the appropriate ...

Interrupts 5-29 Program Control Figure 5–10. Nonmaskable Interrupt Operation Flow Chart Interrupt request sent to CPU Interrupt acknowledged TRAP instruction? Yes No INTM bit set to 1 PC saved on stack Interrupt service routine run Return instruction restores PC Program continues 5.6.8 Interrupt Ser...

Interrupts 5-30 Managing ISRs within ISRs The ’C2xx hardware stack allows you to have ISRs within ISRs. When consid-ering nesting ISRs like this, keep the following in mind: - If you want the ISR be interrupted by a maskable interrupt, the ISR mustunmask the interrupt by setting the appropriate IMR ...

Interrupts 5-31 Program Control For an external, maskable hardware interrupt, a minimum latency of eightcycles is required to synchronize the interrupt externally, recognize the inter-rupt, and branch to the interrupt vector location. On the ninth cycle, the inter-rupt vector is fetched. For a softw...

Reset Operation 5-33 Program Control 5.7 Reset Operation Reset (RS) is a nonmaskable external interrupt that can be used at any timeto put the ’C2xx into a known state. Reset is the highest priority interrupt; noother interrupt takes precedence over reset. Reset is typically applied afterpower up wh...

Power-Down Mode 5-36 5.8 Power-Down Mode The ’C2xx has a power-down mode that allows the ’C2xx core to enter a dor-mant state and use less power than during normal operation. Executing anIDLE instruction initiates power-down mode. When the IDLE instructionexecutes, the program counter is incremented...

Power-Down Mode 5-37 Program Control 5.8.2 Termination of Power-Down During a HOLD Operation One of the necessary steps in the HOLD operation is the execution of an IDLEinstruction (see Section 4.7, Direct Memory Access Using The HOLD Opera- tion, on page 4-27) . There are unique characteristics of ...

6-1 Addressing Modes Addressing Modes This chapter explains the three basic memory addressing modes used by the’C2xx instruction set. The three modes are: - Immediate addressing mode - Direct addressing mode - Indirect addressing mode In immediate addressing, a constant to be manipulated by the inst...

Immediate Addressing Mode 6-2 6.1 Immediate Addressing Mode In immediate addressing, the instruction word contains a constant to be ma-nipulated by the instruction. The ’C2xx supports two types of immediate ad-dressing: - Short-immediate addressing. Instructions that use short-immediate ad-dressing ...

Immediate Addressing Mode 6-3 Addressing Modes Figure 6–2. Two Words Loaded Consecutively to the Instruction Register in Example 6–2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 1 1 1 1 1 1 1 0 1 shift = 2 16-bit constant = 16 384 = 4000h First instruction word: Second instruction word: 0 1 0 0 ADD o...

Direct Addressing Mode 6-4 6.2 Direct Addressing Mode In the direct addressing mode, data memory is addressed in blocks of 128words called data pages. The entire 64K of data memory consists of 512 datapages labeled 0 through 511, as shown in Figure 6–3. The current data pageis determined by the valu...

Direct Addressing Mode 6-5 Addressing Modes Figure 6–4. Instruction Register (IR) Contents in Direct Addressing Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 LSBs 0 8 MSBs 8 MSBs Bits 15 through 8 indicate the instruction type (for example,ADD) and also contain any information regarding a shift of th...

Direct Addressing Mode 6-6 6.2.1 Using Direct Addressing Mode When you use direct addressing mode, the processor uses the DP to find thedata page and uses the seven LSBs of the instruction register to find a particu-lar address on that page. Always do the following: 1) Set the data page. Load the ap...

Direct Addressing Mode 6-7 Addressing Modes Example 6–3. Using Direct Addressing with ADD (Shift of 0 to 15) LDP #4 ;Set data page to 4 (addresses 0200h–027Fh). ADD 9h,5 ;The contents of data address 0209h are ;left–shifted 5 bits and added to the;contents of the accumulator. 7 LSBs from IR 16-bit d...

Direct Addressing Mode 6-8 In Example 6–5, the ADDC instruction references a data memory address thatis generated as shown following the program code. Note that if an instructiondoes not perform shifts, like the ADDC instruction does not, all eight MSBs ofthe instruction contain the opcode for the i...

Indirect Addressing Mode 6-9 Addressing Modes 6.3 Indirect Addressing Mode Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect ad-dressing. Any location in the 64K data memory space can be accessed usinga 16-bit address contained in an auxiliary register. 6.3.1 Current Auxilia...

Indirect Addressing Mode 6-10 ister as the data memory address and then increments or decrements thecontent of the current auxiliary register by the index amount. - Increment or decrement by an index amount using reverse carry. Thevalue in AR0 is the index amount. After the instruction uses the cont...

Indirect Addressing Mode 6-11 Addressing Modes Table 6–1. Indirect Addressing Operands (Continued) Option Operand Example Increment by index amount,adding with reverse carry *BR0+ LT *BR0+ loads the temporary register(TREG) with the content of the datamemory address referenced by thecurrent AR and t...

Indirect Addressing Mode 6-12 Example 6–6. Selecting a New Current Auxiliary Register MAR *,AR1 ;Load the ARP with 1 to make AR1 the;current auxiliary register. LT *+,AR2 ;AR2 is the next auxiliary register.;Load the TREG with the content of the;address referenced by AR1, add one to;the content of A...

Indirect Addressing Mode 6-13 Addressing Modes Table 6–2. Effects of the ARU Code on the Current Auxiliary Register ARU Code 6 5 4 Arithmetic Operation Performed on Current AR 0 0 0 No operation on current AR 0 0 1 current AR – 1 → current AR 0 1 0 current AR + 1 → current AR 0 1 1 Reserved 1 0 0 cu...

Indirect Addressing Mode 6-14 Table 6–3. Field Bits and Notation for Indirect Addressing Instruction Opcode Bits 15 – 8 7 6 5 4 3 2 1 0 Operand(s) Operation ← 8 MSBs → 1 0 0 0 0 ← NAR → * No manipulation of current AR ← 8 MSBs → 1 0 0 0 1 ← NAR → *,AR n NAR → ARP ← 8 MSBs → 1 0 0 1 0 ← NAR → *– curr...

Indirect Addressing Mode 6-15 Addressing Modes 6.3.5 Examples of Indirect Addressing In Example 6–7, when the ADD instruction is fetched from program memory,the instruction register is loaded with the value shown. Example 6–7. No Increment or Decrement ADD *,8 ;Add to the accumulator the content of ...

Indirect Addressing Mode 6-16 Example 6–9. Decrement by 1 ADD *–,8 ;Operates as in Example 6–7, but in;addition, the current auxiliary register;is decremented by one. Example 6–10. Increment by Index Amount ADD *0+,8 ;Operates as in Example 6–7, but in;addition, the content of register AR0;is added ...

Indirect Addressing Mode 6-17 Addressing Modes 6.3.6 Modifying Auxiliary Register Content The LAR, ADRK, SBRK, and MAR instructions are specialized instructions forchanging the content of an auxiliary register (AR): - The LAR instruction loads an AR. - The ADRK instruction adds an immediate value to...

7-1 Assembly Language Instructions Assembly Language Instructions The ’C2xx instruction set supports numerically intensive signal-processing op-erations as well as general-purpose applications such as multiprocessing andhigh-speed control. The ’C2xx instruction set is compatible with the ’C2xinstruc...

Instruction Set Summary 7-2 7.1 Instruction Set Summary This section provides a summary of the instruction set in six tables (Table 7–1to Table 7–6) according to the following functional headings: - Accumulator, arithmetic, and logic instructions (see Table 7–1 on page7-4) - Auxiliary register and d...

Instruction Set Summary 7-3 Assembly Language Instructions IAAA AAAA (One I followed by seven As) The I at the left represents a bitthat reflects whether direct addressing (I = 0) or indirect ad-dressing (I = 1) is being used. When direct addressing is used,the seven As are the seven least significa...

Instruction Set Summary 7-4 ZLVC ZLVC Two 4-bit fields — each representing the following conditions: ACC = 0 Z ACC < 0 L Overflow V Carry C A conditional instruction contains two of these 4-bit fields. The4-LSB field of the instruction is a mask field. A 1 in the corre-sponding mask bit indicates...

Instruction Set Summary 7-7 Assembly Language Instructions Table 7–2. Auxiliary Register Instructions Mnemonic Description Words Cycles Opcode ADRK Add constant to current AR,short immediate 1 1 0111 1000 IIII IIII BANZ Branch on current AR not-zero,indirect 2 4 (condition true)2 (condition false) 0...

Instruction Set Summary 7-8 Table 7–3. TREG, PREG, and Multiply Instructions (Continued) Mnemonic Opcode Cycles Words Description MAC Multiply and accumulate, direct or indirect 2 3 1010 0010 IAAA AAAA+ 1 word MACD Multiply and accumulate with data move, direct orindirect 2 3 1010 0011 IAAA AAAA+ 1 ...

Instruction Set Summary 7-9 Assembly Language Instructions Table 7–4. Branch Instructions (Continued) Mnemonic Opcode Cycles Words Description CALL Call subroutine, indirect 2 4 0111 1010 1AAA AAAA+ 1 word CC Call conditionally 2 4 (conditions true)2 (any condition false) 1110 10TP ZLVC ZLVC+ 1 word...

How To Use the Instruction Descriptions 7-12 7.2 How To Use the Instruction Descriptions Section 7.3 contains detailed information on the instruction set. The descrip-tion for each instruction presents the following categories of information: - Syntax - Operands - Opcode - Execution - Status Bits - ...

How To Use the Instruction Descriptions 7-13 Assembly Language Instructions [, x] Operand x is optional.Example: For the syntax:ADD dma, [, shift] you must supply dma, as in the instruction: ADD 7h and you have the option of adding a shift value, as in the instruction: ADD 7h, 5 [, x1 [, x2]] Operan...

How To Use the Instruction Descriptions 7-14 7.2.2 Operands Operands can be constants, or assembly-time expressions referring tomemory, I/O ports, register addresses, pointers, shift counts, and a variety ofother constants. The operands category for each instruction description de-fines the variable...

How To Use the Instruction Descriptions 7-15 Assembly Language Instructions The field called dma contains the value dma, which is defined in the operands category. The contents of the fields ARU, N, and NAR are derived from the op-erands ind and n but do not directly correspond to those operands; th...

How To Use the Instruction Descriptions 7-17 Assembly Language Instructions If an instruction requires memory operand(s), the rows in the table indicate thelocation(s) of the operand(s), as defined here: DARAM The operand is in internal dual-access RAM. SARAM The operand is in internal single-access...

How To Use the Instruction Descriptions 7-18 The instruction-cycle timings are based on the following assumptions: - At least the next four instructions are fetched from the same memory sec-tion (internal or external) that was used to fetch the current instruction (ex-cept in the case of PC disconti...

Instruction Descriptions 7-20 7.3 Instruction Descriptions This section contains detailed information on the instruction set for the ’C2xx(For a summary of the instruction set, see Section 7.1.) The instructions arepresented alphabetically, and the description for each instruction presents thefollow...

Absolute Value of Accumulator ABS 7-21 Assembly Language Instructions Syntax ABS Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ...|(ACC)| → ACC; 0 → C Status Bits Affected by Affects OVM C and OV This instruction is not affect...

ABS Absolute Value of Accumulator 7-22 Example 1 ABS Before Instruction After Instruction ACC X 1234h ACC 0 1234h C C Example 2 ABS Before Instruction After Instruction ACC X 0FFFFFFFFh ACC 0 1h C C Example 3 ABS ;(OVM = 1) Before Instruction After Instruction ACC X 80000000h ACC 0 7FFFFFFFh C C X 1...

Add to Accumulator ADD 7-25 Assembly Language Instructions Cycles for a Single ADD Instruction (Using Direct and Indirect Addressing) Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2 † 1+p External 1+d 1+d 1+d 2+d+p † If the operand and the code are in the same SARAM block Cyc...

Add to Accumulator With Carry ADDC 7-27 Assembly Language Instructions Syntax ADDC dma Direct addressing ADDC ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* ...

Add to Accumulator With Sign Extension Suppressed ADDS 7-29 Assembly Language Instructions Syntax ADDS dma Direct addressing ADDS ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the follow...

Add to Accumulator With Shift Specified by TREG ADDT 7-31 Assembly Language Instructions Syntax ADDT dma Direct addressing ADDT ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the followin...

Add Short-Immediate Value to Auxiliary Register ADRK 7-33 Assembly Language Instructions Syntax ADRK # k Short immediate addressing Operands k: 8-bit short immediate value ADRK # k 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 0 0 0 k Execution Increment PC, then ...(current AR) + 8-bit positive c...

AND AND With Accumulator 7-34 Syntax AND dma Direct addressing AND ind [, ARn] Indirect addressing AND # lk [, shift] Long immediate addressing AND # lk, 16 Long immediate with left shift of 16 Operands dma: 7 LSBs of the data-memory address shift: Left shift value from 0 to 15 (defaults to 0) n: Va...

Add PREG to Accumulator APAC 7-37 Assembly Language Instructions Syntax APAC Operands None APAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 0 0 Execution Increment PC, then ...(ACC) + shifted (PREG) → ACC Status Bits Affected by Affects PM and OVM C and OV This instruction is n...

APAC Add PREG to Accumulator 7-38 Example APAC ;(PM = 01) Before Instruction After Instruction PREG 40h PREG 40h ACC X 20h ACC 0 A0h C C

Branch Unconditionally B 7-39 Assembly Language Instructions Syntax B pma [, ind [, ARn] ] Indirect addressing Operands pma: 16-bit program-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *BR0– B pma [, ...

BACC Branch to Location Specified by Accumulator 7-40 Syntax BACC Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 1 0 0 0 1 1 1 1 1 0 1 Execution ACC(15:0) → PC Status Bits None Description Control is passed to the 16-bit address residing in the lower half of the accumu-lator. W...

Branch on Auxiliary Register Not Zero BANZ 7-41 Assembly Language Instructions Syntax BANZ pma [, ind [, ARn] ] Indirect addressing Operands pma: 16-bit program-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– ...

BANZ Branch on Auxiliary Register Not Zero 7-42 Example 1 BANZ PGM0 ;(PGM0 labels program address 0) Before Instruction After Instruction ARP 0 ARP 0 AR0 5h AR0 4h Because the content of AR0 is not zero, the program branches to program ad-dress 0 is loaded into the program counter (PC), and the prog...

Branch Conditionally BCND 7-43 Assembly Language Instructions Syntax BCND pma, cond 1 [,cond 2] [,...] Operands pma: 16-bit program-memory address cond Condition EQ ACC = 0 NEQ ACC ≠ 0 LT ACC < 0 LEQ ACC ≤ 0 GT ACC > 0 GEQ ACC ≥ 0 NC C = 0 C C = 1 NOV OV = 0 OV OV = 1 BIO BIO low NTC TC = 0 TC...

Test Bit BIT 7-45 Assembly Language Instructions Syntax BIT dma, bit code Direct addressing BIT ind, bit code [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address bit code: Value from 0 to 15 indicating which bit to test (see Figure 7–1) n: Value from 0 to 7 designating the ne...

Test Bit Specified by TREG BITT 7-47 Assembly Language Instructions Syntax BITT dma Direct addressing BITT ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ ...

BLPD Block Move From Program Memory to Data Memory 7-54 Syntax General syntax: BLPD source, destination BLPD # pma, dma Direct with long immediate source BLPD # pma, ind [, ARn] Indirect with long immediate source Operands pma: 16-bit program-memory address dma: 7 LSBs of the data-memory address n: ...

Block Move From Program Memory to Data Memory BLPD 7-55 Assembly Language Instructions Description A word in program memory pointed to by the source is copied to data-memory space pointed to by destination. The first word of the source space is pointed to by a long-immediate value. The data-memory d...

Block Move From Program Memory to Data Memory BLPD 7-57 Assembly Language Instructions Cycles for a Repeat (RPT) Execution of a BLPD Instruction (Continued) Operand External SARAM DARAM ROM Source: SARAMDestination: SARAM n+22n ‡ n+22n ‡ n+22n ‡ n+4 † 2n+2 § n+2+2p code 2n+2p code ‡ Source: External...

CALA Call Subroutine at Location Specified by Accumulator 7-58 Syntax CALA Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 1 1 0 0 0 1 1 1 1 1 0 1 Execution PC + 1 → TOS ACC(15:0) → PC Status Bits None Description The current program counter (PC) is incremented and pushed onto the...

Call Unconditionally CALL 7-59 Assembly Language Instructions Syntax CALL pma [, ind [, ARn] ] Indirect addressing Operands pma: 16-bit program-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *BR0– CALL ...

CC Call Conditionally 7-60 Syntax CC pma, cond Ă 1 [, cond Ă 2] [,...] Operands pma: 16-bit program-memory address cond Condition EQ ACC = 0 NEQ ACC ≠ 0 LT ACC < 0 LEQ ACC ≤ 0 GT ACC > 0 GEQ ACC ≥ 0 NC C = 0 C C = 1 NOV OV = 0 OV OV = 1 BIO BIO low NTC TC = 0 TC TC = 1 UNC Unconditionally Opco...

CLRC Clear Control Bit 7-62 Syntax CLRC control bit Operands control bit: Select one of the following control bits:C Carry bit of status register ST1 CNF RAM configuration control bit of status register ST1 INTM Interrupt mode bit of status register ST0 OVM Overflow mode bit of status register ST0 S...

Clear Control Bit CLRC 7-63 Assembly Language Instructions Words 1 Cycles for a Single CLRC Instruction ROM DARAM SARAM External 1 1 1 1+p Cycles for a Repeat (RPT) Execution of a CLRC Instruction ROM DARAM SARAM External n n n n+p Example CLRC TC ;(TC is bit 11 of ST1) Before Instruction After Inst...

CMPL Complement Accumulator 7-64 Syntax CMPL Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ...(ACC) → ACC Status Bits None Description The contents of the accumulator are replaced with its logical inversion (1scomplement). The...

Compare Auxiliary Register With AR0 CMPR 7-65 Assembly Language Instructions Syntax CMPR CM Operands CM: Value from 0 to 3 Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CM 1 0 0 0 1 0 1 1 1 1 1 1 0 1 Execution Increment PC, then ...Compare (current AR) to (AR0) and place the result in the TC bit of s...

DMOV Data Move in Data Memory 7-66 Syntax DMOV dma Direct addressing DMOV ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *BR0– DMOV dma 1...

IDLE Idle Until Interrupt 7-68 Syntax IDLE Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then wait for unmasked or nonmaskable hardware interrupt. Status Bits Affected by INTM Description The IDLE instruction forces the program bei...

Input Data From Port IN 7-69 Assembly Language Instructions Syntax IN dma, PA Direct addressing IN ind, PA [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register PA: 16-bit I/O port or I/O-mapped register address ind: ...

Software Interrupt INTR 7-71 Assembly Language Instructions Syntax INTR K Operands K: Value from 0 to 31 that indicates the interrupt vector locationto branch to Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 K 1 1 0 0 1 1 1 1 1 0 1 Execution (PC) + 1 → stack corresponding interrupt vector location → ...

LACC Load Accumulator With Shift 7-72 Syntax LACC dma [, shift] Direct addressing LACC dma, 16 Direct with left shift of 16 LACC ind [, shift [, ARn] ] Indirect addressing LACC ind, 16[, ARn] Indirect with left shift of 16 LACC # lk [, shift] Long immediate addressing Operands dma: 7 LSBs of the dat...

Load Low Accumulator and Clear High Accumulator LACL 7-75 Assembly Language Instructions Syntax LACL dma Direct addressing LACL ind [, ARn] Indirect addressing LACL # k Short immediate Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register k: 8-b...

LACT Load Accumulator With Shift Specified by TREG 7-78 Syntax LACT dma Direct addressing LACT ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *...

LAR Load Auxiliary Register 7-80 Syntax LAR AR x, dma Direct addressing LAR AR x, ind [, ARn] Indirect addressing LAR AR x, #k Short immediate addressing LAR AR x, #lk Long immediate addressing Operands x: Value from 0 to 7 designating the auxiliary register to be loaded dma: 7 LSBs of the data-memo...

Load Data Page Pointer LDP 7-83 Assembly Language Instructions Syntax LDP dma Direct addressing LDP ind [, ARn] Indirect addressing LDP # k Short immediate addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register k: 9-bit short immediate...

Load Product Register High Word LPH 7-85 Assembly Language Instructions Syntax LPH dma Direct addressing LPH ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *...

Load Status Register LST 7-87 Assembly Language Instructions Syntax LST # m, dma Direct addressing LST # m, ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register m: Select one of the following:0 Indicates that ST0...

LST Load Status Register 7-88 Figure 7–4. LST #1 Operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST0 ARP OV OVM 1 INTM DP ↑ ↑ ↑ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST1 ARB CNF TC SXM C 1 1 1 1 XF 1 1 PM Status Bits Affects ARB, ARP, OV...

Load TREG and Accumulate Previous Product LTA 7-93 Assembly Language Instructions Syntax LTA dma Direct addressing LTA ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven o...

Load TREG, Accumulate Previous Product, and Move Data LTD 7-95 Assembly Language Instructions Syntax LTD dma Direct addressing LTD ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the follo...

LTP Load TREG and Store PREG in Accumulator 7-98 Syntax LTP dma Direct addressing LTP ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *BR0...

LTS Load TREG and Subtract Previous Product 7-100 Syntax LTS dma Direct addressing LTS ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *BR...

MAC Multiply and Accumulate 7-102 Syntax MAC pma, dma Direct addressing MAC pma, ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address pma: 16-bit program-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven opti...

MACD Multiply and Accumulate With Data Move 7-106 Syntax MACD pma, dma Direct addressing MACD pma, ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address pma: 16-bit program-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the fo...

Multiply and Accumulate With Data Move MACD 7-107 Assembly Language Instructions Status Bits Affected by Affects PM and OVM C and OV Description The MACD instruction: - Adds the previous product, shifted as defined by the PM status bits, to theaccumulator. The carry bit is set (C = 1) if the result ...

Modify Auxiliary Register MAR 7-111 Assembly Language Instructions Syntax MAR dma Direct addressing MAR ind [, ARn] Indirect addressing Operands n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *BR0– MAR dma 15 14 13 12...

Multiply MPY 7-113 Assembly Language Instructions Syntax MPY dma Direct addressing MPY ind [, ARn] Indirect addressing MPY # k Short immediate addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register k: 13-bit short immediate value ind: ...

MPYA Multiply and Accumulate Previous Product 7-116 Syntax MPYA dma Direct addressing MPYA ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+...

MPYS Multiply and Subtract Previous Product 7-118 Syntax MPYS dma Direct addressing MPYS ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *...

MPYU Multiply Unsigned 7-120 Syntax MPYU dma Direct addressing MPYU ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *BR0– MPYU dma 15 14 1...

NEG Negate Accumulator 7-122 Syntax NEG Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 0 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ...(ACC) × –1 → ACC Status Bits Affected by Affects OVM C and OV Description The content of the accumulator is replaced with its arithmetic ...

NMI Nonmaskable Interrupt 7-124 Syntax NMI Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 0 1 0 1 0 0 1 1 1 1 1 0 1 Execution (PC) + 1 → stack 24h → PC 1 → INTM Status Bits AffectsINTM This instruction is not affected by INTM. Description The NMI instruction forces the program coun...

No Operation NOP 7-125 Assembly Language Instructions Syntax NOP Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 Execution Increment PC Status Bits None Description No operation is performed. The NOP instruction affects only the PC. The NOPinstruction is us...

NORM Normalize Contents of Accumulator 7-126 Syntax NORM ind Indirect addressing Operands ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *BR0– NORM ind 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 0 1 ARU N NAR Note: ARU, N, and NAR are defined in Section 6.3, Indirect A...

Normalize Contents of Accumulator NORM 7-127 Assembly Language Instructions Notes: For the NORM instruction, the auxiliary register operations are executed dur-ing the fourth phase of the pipeline, the execution phase. For other instruc-tions, the auxiliary register operations take place in the seco...

OR With Accumulator OR 7-129 Assembly Language Instructions Syntax OR dma Direct addressing OR ind [, ARn] Indirect addressing OR # lk [, shift] Long immediate addressing OR # lk, 16 Long immediate with left shift of 16 Operands dma: 7 LSBs of the data-memory address shift: Left shift value from 0 t...

OR With Accumulator OR 7-131 Assembly Language Instructions Example 1 OR DAT8 ;(DP = 8) Before Instruction After Instruction Data Memory Data Memory 408h 0F000h 408h 0F000h ACC X 100002h ACC X 10F002h C C Example 2 OR *,AR0 Before Instruction After Instruction ARP 1 ARP 0 AR1 300h AR1 300h Data Memo...

OUT Output Data to Port 7-132 Syntax OUT dma, PA Direct addressing OUT ind, PA [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address PA: 16-bit I/O address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0...

PAC Load Accumulator With Product Register 7-134 Syntax PAC Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ...shifted (PREG) → ACC Status Bits Affected byPM Description The content of PREG, shifted as specified by the PM status...

Pop Top of Stack to Low Accumulator POP 7-135 Assembly Language Instructions Syntax POP Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ...(TOS) → ACC(15:0) 0 → ACC(31:16) Pop stack one level Status Bits None Description The con...

Pop Top of Stack to Data Memory POPD 7-137 Assembly Language Instructions Syntax POPD dma Direct addressing POPD ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options...

Push Data-Memory Value Onto Stack PSHD 7-139 Assembly Language Instructions Syntax PSHD dma Direct addressing PSHD ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven optio...

Push Low Accumulator Onto Stack PUSH 7-141 Assembly Language Instructions Syntax PUSH Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then...Push all stack locations down one levelACC(15:0) → TOS Status Bits None Description The stac...

RET Return From Subroutine 7-142 Syntax RET Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 Execution (TOS) → PC Pop stack one level. Status Bits None Description The contents of the top stack register are copied into the program counter. Theremaining stack...

Return Conditionally RETC 7-143 Assembly Language Instructions Syntax RETC cond 1 [, cond 2] [,...] Operands cond Condition EQ ACC = 0 NEQ ACC ≠ 0 LT ACC < 0 LEQ ACC ≤ 0 GT ACC > 0 GEQ ACC ≥ 0 NC C = 0 C C =1 NOV OV = 0 OV OV = 1 BIO BIO low NTC TC = 0 TC TC = 1 UNC Unconditionally ‡ Opcode 0 ...

ROL Rotate Accumulator Left 7-144 Syntax ROL Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ...C → ACC(0) (ACC(31)) → C (ACC(30:0)) → ACC(31:1) Status Bits Affects C This instruction is not affected by SXM. Description The ROL ...

Rotate Accumulator Right ROR 7-145 Assembly Language Instructions Syntax ROR Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ...C → ACC(31) (ACC(0)) → C (ACC(31:1)) → ACC(30:0) Status Bits AffectsC This instruction is not affect...

RPT Repeat Next Instruction 7-146 Syntax RPT dma Direct addressing RPT ind [, ARn] Indirect addressing RPT # k Short immediate Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register k: 8-bit short immediate value ind: Select one of the following ...

SACH Store High Accumulator With Shift 7-148 Syntax SACH dma [, shift2 ] Direct addressing SACH ind [, shift2 [, ARn] ] Indirect addressing Operands dma: 7 LSBs of the data-memory address shift2: Left shift value from 0 to 7 (defaults to 0) n: Value from 0 to 7 designating the next auxiliary registe...

SACL Store Low Accumulator With Shift 7-150 Syntax SACL dma [, shift2 ] Direct addressing SACL ind [, shift2 [, ARn] ] Indirect addressing Operands dma: 7 LSBs of the data-memory address shift2: Left shift value from 0 to 7 (defaults to 0) n: Value from 0 to 7 designating the next auxiliary register...

SAR Store Auxiliary Register 7-152 Syntax SAR AR x, dma Direct addressing SAR AR x, ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address x: Value from 0 to 7 designating the auxiliary register value to be stored n: Value from 0 to 7 designating the next auxiliary register ...

SBRK Subtract Short-Immediate Value From Auxiliary Register 7-154 Syntax SBRK # k Short immediate addressing Operands k: 8-bit positive short immediate value SBRK # k 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 0 0 k Execution Increment PC, then ...(current AR) – k → current AR Note that k is ...

Set Control Bit SETC 7-155 Assembly Language Instructions Syntax SETC control bit Operands control bit: Select one of the following control bits:C Carry bit of status register ST1 CNF RAM configuration control bit of status register ST1 INTM Interrupt mode bit of status register ST0 OVM Overflow mod...

Shift Accumulator Left SFL 7-157 Assembly Language Instructions Syntax SFL Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 1 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ...(ACC(31)) → C (ACC(30:0)) → ACC(31:1) 0 → ACC(0) Status Bits AffectsC This instruction is not affected...

SFR Shift Accumulator Right 7-158 Syntax SFR Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ...If SXM = 0 Then 0 → ACC(31). If SXM = 1 Then (ACC(31)) → ACC(31) (ACC(31:1)) → ACC(30:0) (ACC(0)) → C Status Bits Affected by Affect...

SPAC Subtract PREG From Accumulator 7-160 Syntax SPAC Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 1 0 0 0 0 0 0 1 1 1 1 1 0 1 Execution Increment PC, then ...(ACC) – shifted (PREG) → ACC Status Bits Affected by Affects PM and OVM C and OV This instruction is not affected by SXM. D...

Store High PREG SPH 7-161 Assembly Language Instructions Syntax SPH dma Direct addressing SPH ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *B...

Store Low PREG SPL 7-163 Assembly Language Instructions Syntax SPL dma Direct addressing SPL ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR...

Store Long-Immediate Value to Data Memory SPLK 7-165 Assembly Language Instructions Syntax SPLK # lk, dma Direct addressing SPLK # lk, ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register lk: 16-bit long immediat...

Set PREG Output Shift Mode SPM 7-167 Assembly Language Instructions Syntax SPM constant Operands constant: Value from 0 to 3 that determines the product shift mode Opcode constant 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Execution Increment PC, then ...constant → product shi...

SQRA Square Value and Accumulate Previous Product 7-168 Syntax SQRA dma Direct addressing SQRA ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *...

SQRS Square Value and Subtract Previous Product 7-170 Syntax SQRS dma Direct addressing SQRS ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR...

SST Store Status Register 7-172 Syntax SST # m, dma Direct addressing SST # m, ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register m: Select one of the following:0 Indicates that ST0 will be stored 1 Indicates t...

Store Status Register SST 7-173 Assembly Language Instructions Status registers ST0 and ST1 are defined in Section 3.5, Status Registers ST0 and ST1, on page 3-15. Words 1 Cycles for a Single SST Instruction Program Operand ROM DARAM SARAM External DARAM 1 1 1 1+p SARAM 1 1 1, 2 † 1+p External 2+d 2...

SUB Subtract From Accumulator 7-174 Syntax SUB dma [, shift ] Direct addressing SUB dma,16 Direct with left shift of 16 SUB ind [,shift [, ARn] ] Indirect addressing SUB ind,16[ , ARn] Indirect with left shift of 16 SUB # k Short immediate SUB # lk [,shift ] Long immediate Operands dma: 7 LSBs of th...

SUBB Subtract From Accumulator With Borrow 7-178 Syntax SUBB dma Direct addressing SUBB ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *B...

SUBC Conditional Subtract 7-180 Syntax SUBC dma Direct addressing SUBC ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *BR0– SUBC dma 15 1...

SUBS Subtract From Accumulator With Sign Extension Suppressed 7-182 Syntax SUBS dma Direct addressing SUBS ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ ...

SUBT Subtract From Accumulator With Shift Specified by TREG 7-184 Syntax SUBT dma Direct addressing SUBT ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *–...

TBLR Table Read 7-186 Syntax TBLR dma Direct addressing TBLR ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR0+ *BR0– TBLR dma 15 14 13 12 11...

Table Write TBLW 7-189 Assembly Language Instructions Syntax TBLW dma Direct addressing TBLW ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:* *+ *– *0+ *0– *BR...

TRAP Software Interrupt 7-192 Syntax TRAP Operands None Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 0 1 0 1 0 0 1 1 1 1 1 0 1 Execution (PC) + 1 → stack 22h → PC Status Bits Not affected by INTM; does not affect INTM. Description The TRAP instruction is a software interrupt that transfers pro...

Exclusive OR With Accumulator XOR 7-193 Assembly Language Instructions Syntax XOR dma Direct addressing XOR ind [, ARn] Indirect addressing XOR # lk, [, shift ] Long immediate addressing XOR # lk,16 Long immediate with left shift of 16 Operands dma: 7 LSBs of the data-memory address shift: Left shif...

ZALR Zero Low Accumulator and Load High Accumulator With Rounding 7-196 Syntax ZALR dma Direct addressing ZALR ind [, ARn] Indirect addressing Operands dma: 7 LSBs of the data-memory address n: Value from 0 to 7 designating the next auxiliary register ind: Select one of the following seven options:*...

8-1 On-Chip Peripherals On-Chip Peripherals This chapter discusses on-chip peripherals connected to the ’C2xx CPU andtheir control registers. The on-chip peripherals are controlled throughmemory-mapped registers. The operations of the timer and the serial ports aresynchronized to the processor throu...

Control of On-Chip Peripherals 8-2 8.1 Control of On-Chip Peripherals The on-chip peripherals are controlled by accessing control registers that aremapped to on-chip I/O space. Data is also transferred to and from the peripher-als through these registers. Setting and clearing bits in these registers...

Clock Generator 8-4 8.2 Clock Generator The high pulse of the master clock output signal (CLKOUT1) signifies the logicphase of the device (the phase when values are changed), while the low pulsesignifies the latch phase (the phase when values are latched). CLKOUT1 de-termines much of the device’s op...

Clock Generator 8-5 On-Chip Peripherals - External Oscillator. CLKIN is the output of an external oscillator, whichis connected to the CLKIN/X2 pin. The X1 pin must be left unconnected.See Figure 8–2. Figure 8–2. Using an External Oscillator ’C2xx X1 CLKIN/X2 No connection Oscillator Regardless of t...

Clock Generator 8-6 Table 8–2. ’C2xx Input Clock Modes ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Clock Mode ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ CLKOUT1 Rate ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ DIV2 ÁÁÁ Á Á Á ÁÁÁ DIV1 ÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ ExternalCLKIN Source? ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ InternalOscillator ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ InternalPLL ÁÁÁÁ ÁÁÁÁ...

Timer 8-8 8.4 Timer The ’C2xx features an on-chip timer with a 4-bit prescaler. This timer is a downcounter that can be stopped, restarted, reset, or disabled by specific statusbits. You can use the timer to generate periodic CPU interrupts. Figure 8–4 shows a functional block diagram of the timer. ...

Timer 8-9 On-Chip Peripherals The TINT request automatically sets the TINT flag bit in the interrupt flag regis-ter (IFR). You can mask or unmask the request with the interrupt mask register(IMR). If you are not using the timer, mask TINT so that it does not cause anunexpected interrupt. 8.4.1 Timer...

Timer 8-10 sor v are the TIM and PRD, respectively. Both are16-bit registers mapped toI/O space. The 4-bit TDDR (timer divide-down register) and the 4-bit PSC (prescalercounter) are contained in the timer control register (TCR) described in subsec-tion 8.4.2. The TIM (timer counter register) and the...

Timer 8-11 On-Chip Peripherals Figure 8–5. ’C2xx Timer Control Register (TCR) — I/O-Space Address FFF8h 15 12 11 10 9 6 5 4 3 0 ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ Reserved FREE SOFT PSC TRB TSS TDDR 0 R/W–0 R/W–0 R/W–0 R/W–0 W–0 R/W–0 Note: 0 = Always read as zeros; R = Read access; W = Write access; value following...

Timer 8-12 Bit 4 TSS — Timer stop status bit. TSS stops or starts the timer. At reset, TSSis cleared to 0 and the timer immediately starts. TSS = 0 Starts or restarts the timer. TSS = 1 Stops the timer. Bits 3–0 TDDR — Timer divide-down register. Every (TDDR + 1) CLKOUT1 cycles,the timer counter reg...

Timer 8-13 On-Chip Peripherals 8.4.4 Setting the Timer Interrupt Rate When the divide-down value (TDDR) is 0, you can program the timer to gener-ate an interrupt (TINT) every 2 to 65 536 cycles by programming the periodregister (PRD) from 0 to 65 535 (FFFFh). When TDDR is nonzero (1 to 15),the timer...

Wait-State Generator 8-14 8.5 Wait-State Generator Wait states are necessary when you want to interface the ’C2xx with slowerexternal logic and memory. By adding wait states, you lengthen the time theCPU waits for external memory or an external I/O port to respond when theCPU reads from or writes to...

Wait-State Generator 8-16 Table 8–4 shows how to set the number of wait states you want for each typeof off-chip memory. For example, if you write 1s to bits 0 through 5, the devicewill generate seven wait states for off-chip lower program memory and sevenwait states for off-chip upper program memor...

General-Purpose I/O Pins 8-17 On-Chip Peripherals 8.6 General-Purpose I/O Pins The ’C2xx provides pins that can be used to supply input signals from an exter-nal device or output signals to an external device. These pins are not boundto specific uses; rather, they can provide input or output signals...

General-Purpose I/O Pins 8-18 Figure 8–7. BIO Timing Diagram Example BIO CLKOUT1 1 CLKOUT1 cycle 8.6.2 Output Pin XF The XF pin is the external flag output pin. If you connect XF to an input pin ofanother processor, you can use XF as a signal to other processor. The mostrecent XF value is latched in...

9-1 Synchronous Serial Port Synchronous Serial Port The ’C2xx devices have a synchronous serial port that provides directcommunication with serial devices such as codecs (coder/decoders) andserial A/D converters. The serial port may also be used for intercommunicationbetween processors in multiproce...

Overview of the Synchronous Serial Port 9-2 9.1 Overview of the Synchronous Serial Port Both receive and transmit operations of the synchronous serial port have afour-word-deep first-in, first-out (FIFO) buffer. The FIFO buffers reduce theamount of CPU overhead inherent in servicing transmit or rece...

Components and Basic Operation 9-3 Synchronous Serial Port 9.2 Components and Basic Operation The synchronous serial port has several hard-wired parts, including two FIFObuffers and six signal pins. Figure 9–1 shows how the components of the syn-chronous serial port are interconnected. Figure 9–1. S...

Components and Basic Operation 9-4 - Data signal. The data signal carries the actual data that is transferred inthe transmit/receive operation. The data signal transmit pin (DX) of onedevice should be connected to the data signal receive (DR) pin on anotherdevice. Table 9–1 describes the six pins th...

Components and Basic Operation 9-5 Synchronous Serial Port Figure 9–2. 2-Way Serial Port Transfer With External Frame Sync and External Clock TMS320C203 TLC320AD55C Analogsignal A/D D/A Analogsignal DR DX CLKX CLKR FSX FSR D OUT D IN SCK FS Legend: DOUT Transmit data DR Receive data DIN Receive data...

Components and Basic Operation 9-6 9.2.3 Interrupts The synchronous serial port (SSP) has two hardware interrupts that let the pro-cessor know when the FIFO buffers need to be serviced: - Transmit interrupts (XINTs) cause a branch to address 000Ah in programspace whenever the transmit-interrupt trig...

Controlling and Resetting the Port 9-8 9.3 Controlling and Resetting the Port The synchronous serial port control register (SSPCR) controls the operationof the synchronous serial port. To configure the serial port, a total of two writesto the SSPCR are necessary: 1) Write your choices to the configu...

Controlling and Resetting the Port 9-9 Synchronous Serial Port Table 9–2. Run and Emulation Modes ÁÁÁ ÁÁÁ FREE ÁÁÁÁ ÁÁÁÁ SOFT ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Run/Emulation Mode ÁÁÁ ÁÁÁ 0 ÁÁÁÁ ÁÁÁÁ 0 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Immediate stop ÁÁÁ Á Á Á ÁÁÁ 0 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ 1 ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Stop after completionof w...

Controlling and Resetting the Port 9-12 Bit 0 DLB — Digital loopback mode. The DLB bit can be used to put the serialport in digital loopback mode. DLB = 0 Digital loopback mode is disabled. The DR, FSR, and CLKRsignals are connected to their respective device pins. DLB = 1 Digital loopback mode is e...

Controlling and Resetting the Port 9-13 Synchronous Serial Port A transmit frame sync pulse marks the start of a data transmission. The syn-chronous serial port can transmit using the internal frame sync source or usingan external source: - To use internal frame sync pulses, set the TXM bit in the S...

Controlling and Resetting the Port 9-14 1) Create interrupt service routines for XINTs and RINTs and include a branch to each service routine at the appropriate interrupt vector address: - The RINT vector is fetched from address 0008h. - The XINT vector is fetched from address 000Ah. 2) Select when ...

Managing the Contents of the FIFO Buffers 9-15 Synchronous Serial Port 9.4 Managing the Contents of the FIFO Buffers The SDTR is a read/write register (at I/O address FFF0h) that is used to senddata to the transmit FIFO buffer and to extract data from the receive FIFObuffer. A word is written to the...

Transmitter Operation 9-16 9.5 Transmitter Operation Transmitter operation is different in continuous and burst modes. Other differ-ences also depend on whether an internal or an external frame sync is used. 9.5.1 Burst Mode Transmission With Internal Frame Sync (FSM = 1, TXM = 1) Use burst mode tra...

Transmitter Operation 9-17 Synchronous Serial Port If the SDTR is loaded with a new word while the transmit FIFO buffer is full, thenew word will be lost; the FIFO buffer will not accept any more than four words. The burst mode can be discontinued (changed to continuous mode) only bya serial-port or...

Transmitter Operation 9-19 Synchronous Serial Port Figure 9–5. Burst Mode Transmission With External Frame Sync FSX CLKX DX XINT A15 MSB A14 A13 A12 A11 A10 ... A0 B15 LSB XSR loaded from buffer XSR loaded from buffer

Transmitter Operation 9-21 Synchronous Serial Port If the SDTR is loaded with a new word while the transmit FIFO buffer is full, thenew word will be lost; the FIFO buffer will not accept any more than four words. Continuous mode can be discontinued (changed to burst mode) only by a seri-al-port or d...

Transmitter Operation 9-23 Synchronous Serial Port The continuous mode can be discontinued (changed to burst mode) only bya serial-port or device reset. Changing the FSM bit during transmit or halt willnot necessarily cause a switch to burst mode. Figure 9–7. Continuous Mode Transmission With Extern...

Receiver Operation 9-24 9.6 Receiver Operation Receiver operation is different in continuous and burst modes. The receiverdoes not generate frame sync pulses; it always takes the frame sync pulse asan input. In selecting the proper receive mode, note that the mode for the receiver mustmatch the mode...

Receiver Operation 9-25 Synchronous Serial Port If a frame sync pulse occurs during reception, reception is restarted, and thebits that were shifted into the RSR before the pulse are lost. Figure 9–8. Burst Mode Reception CLKR FSR DR RINT A15 MSB A14 A13 A12 A11 A10 ... A0 B15 LSB Word loaded to buf...

Receiver Operation 9-26 3) The remaining bits in the word are then shifted into the RSR, one by one at the falling edge of each consecutive clock cycle. 4) After all bits have been received, if the FIFO buffer is not full, the contents of the RSR are copied to the receive FIFO buffer. If the receive...

Troubleshooting 9-27 Synchronous Serial Port 9.7 Troubleshooting The synchronous serial port uses three bits for troubleshooting and testing. Inaddition to using these three bits, you must be able to identify special errorconditions that may occur in actual transfers. Error conditions result from an...

Troubleshooting 9-28 Table 9–6. Run and Emulation Modes ÁÁÁ ÁÁÁ FREE ÁÁÁ ÁÁÁ SOFT ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Run/Emulation Mode ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Immediate stop ÁÁÁ Á Á Á ÁÁÁ 0 ÁÁÁ Á Á Á ÁÁÁ 1 ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Stop after completionof word ÁÁÁ ÁÁÁ 1 ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ...

Troubleshooting 9-29 Synchronous Serial Port 9.7.2 Burst Mode Error Conditions The following are descriptions of errors that can occur in burst mode: - Underflow. Underflow is caused if an external FSX occurs, and there areno new words in the transmit FIFO buffer. Upon receiving the FSX (gener-ally,...

10-1 Asynchronous Serial Port Asynchronous Serial Port The ’C2xx has an asynchronous serial port that can be used to transfer datato and from other devices. The port has several important features: - Full-duplex transmit and receive operations at the maximum transfer rate - Data-word length of eight...

Components and Basic Operation 10-3 Asynchronous Serial Port 10.2 Components and Basic Operation Figure 10–1 shows the main components of the asynchronous serial port. Figure 10–1. Asynchronous Serial Port Block Diagram TXRXINT ADTR ARSR ADTR AXSR Control logic (transmit) Control logic (receive) TX ...

Components and Basic Operation 10-4 Table 10–1. Asynchronous Serial Port Interface Pins Pin Name Description TX Asynchronous serial port data transmit pin. Transmits serial data fromthe asynchronous serial port transmit shift register (AXSR). RX Asynchronous serial port data receive pin. Receives se...

Components and Basic Operation 10-6 10.2.5 Basic Operation Figure 10–2 shows a typical serial link between a ’C2xx device and any hostCPU. In this mode of communication, any 8-bit character can be transmittedor received serially by way of the transmit data pin (TX) or the receive data pin(RX), respe...

Controlling and Resetting the Port 10-7 Asynchronous Serial Port 10.3 Controlling and Resetting the Port The asynchronous serial port is programmed through three on-chip registersmapped to I/O space: the asynchronous serial port control register (ASPCR),the I/O status register (IOSR), and the baud-r...

Controlling and Resetting the Port 10-8 Bits 12–10 Reserved. Always read as 0s. Bit 9 DIM — Delta interrupt mask. DIM selects whether or not delta interruptsare asserted on the TXRXINT interrupt line. A delta interrupt is generated bya change on one of the general-purpose I/O pins (IO3, IO2, IO1, or...

Controlling and Resetting the Port 10-9 Asynchronous Serial Port Bit 3 CIO3 — Configuration bit for IO3. CIO3 configures I/O pin 3 (IO3) as aninput or as an output. CIO3 = 0 IO3 is configured as an input. This is the default value at re-set. CIO3 = 1 IO3 is configured as an output. Bit 2 CIO2 — Conf...

Controlling and Resetting the Port 10-10 10.3.2 I/O Status Register (IOSR) The IOSR returns the status of the asynchronous serial port and of I/O pinsIO0–IO3. The IOSR is a 16-bit, on-chip register mapped to address FFF6h inI/O space. Figure 10–4 shows the fields in the IOSR, and bit descriptions fo...

Controlling and Resetting the Port 10-13 Asynchronous Serial Port Bit 3 IO3 — Status bit for IO3. When the IO3 pin is configured as an input (by theCIO3 bit of the ASPCR), this bit reflects the current level on the IO3 pin. IO3 = 0 The IO3 signal is low. IO3 = 1 The IO3 signal is high. Bit 2 IO2 — S...

Controlling and Resetting the Port 10-14 Table 10–2. Common Baud Rates and the Corresponding BRD Values BRD Value in Hexadecimal BaudRate CLKOUT1 = 20 MHz (50 ns) CLKOUT1 = 28.57 MHz (35 ns) CLKOUT1 = 40 MHz (25 ns) 1200 0411 05CC 0823 2400 0208 02E6 0411 4800 0104 0173 0208 9600 0082 00B9 0104 1920...

Controlling and Resetting the Port 10-15 Asynchronous Serial Port 10.3.5 Using I/O Pins IO3, IO2, IO1, and IO0 Pins IO3, IO2, IO1, and IO0 can be individually configured as inputs or outputsand can be used as handshake control for the asynchronous serial port or asgeneral-purpose I/O pins. They are ...

Controlling and Resetting the Port 10-16 When pins IO0–IO3 are configured as inputs When pins IO0–IO3 are configured as inputs, the eight LSBs of the IOSR allowyou to monitor these four pins. Each of the IOSR bits 3–0, called IO3, IO2, IO1,and IO0, can be used to read the current logic level (high o...

Transmitter Operation 10-19 Asynchronous Serial Port 10.4 Transmitter Operation The transmitter consists of an 8-bit transmit register (ADTR) and an 8-bit trans-mit shift register (AXSR). Data to be transmitted is written to the ADTR, andthen the port transfers the data to the AXSR. Data written to ...

Receiver Operation 10-20 10.5 Receiver Operation The receiver includes two internal 8-bit registers: the receive register (ADTR)and receive shift register (ARSR). The data received at the RX pin should havethe serial form shown in Figure 10–7 (the number of stop bits required de-pends on the value o...

’C209 Versus Other ’C2xx Devices 11-3 TMS320C209 - Memory and I/O Spaces: J The I/O addresses of the peripheral registers are different on the’C209. J The ’C209 does not support the ’C2xx HOLD operation. - Interrupts: J The ’C209 has four maskable interrupt lines, none of them shared.The other devic...

’C209 Memory and I/O Spaces 11-8 (4K) are mapped to external data memory. Thus, a total of 8K additionaladdresses (4K program and 4K data) are available for external memory. DARAM blocks B1 and B2 are fixed, but DARAM block B0 may be mapped toprogram space or data space, depending on the value of th...

’C209 Interrupts 11-10 11.3 ’C209 Interrupts Table 11–4 lists the interrupts available on the ’C209 and shows their vectorlocations. In addition, it shows the priority of each of the hardware interrupts.Note that a device reset can be initiated in either of two ways: by driving theRS pin low or by d...

’C209 Interrupts 11-11 TMS320C209 Table 11–4. ’C209 Interrupt Locations and Priorities (Continued) ÁÁÁ Á Á Á ÁÁÁ K † ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ VectorLocation ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ Name ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Priority ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Function ÁÁÁ ÁÁÁ 15 ÁÁÁÁÁ ÁÁÁÁÁ 1Eh ÁÁÁÁÁ ÁÁÁÁÁ INT15 ÁÁÁÁ ÁÁÁ...

’C209 Interrupts 11-12 Figure 11–2. ’C209 Interrupt Flag Register (IFR) — Data-Memory Address 0006h 15 4 3 2 1 0 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved TINT INT3 INT2 INT1 0 R/W1C–0 R/W1C–0 R/W1C–0 R/W1C–0 Note: 0 = Always read as zeros; R = Read access; W1C = Write 1 to this bit to clear it t...

’C209 On-Chip Peripherals 11-15 TMS320C209 Table 11–5. ’C209 Input Clock Modes ÁÁÁÁÁ ÁÁÁÁÁ Clock Mode ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ CLKOUT1 Rate ÁÁÁÁÁ ÁÁÁÁÁ CLKMOD ÁÁÁÁ ÁÁÁÁ Oscillator ÁÁÁÁÁ ÁÁÁÁÁ PLL ÁÁÁÁÁ ÁÁÁÁÁ ÷ 2 ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ CLKOUT1 = CLKIN ÷ 2 ÁÁÁÁÁ ÁÁÁÁÁ 0 ÁÁÁÁ ÁÁÁÁ Enabled ÁÁÁÁÁ ÁÁÁÁÁ Disabled ÁÁÁÁ...

A-1 Appendix A Register Summary For the status and control registers of the ’C2xx devices, this appendixsummarizes: - Their addresses - Their reset values - The functions of their bits Topic Page A.1 Addresses and Reset Values A-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Addresses and Reset Values A-2 A.1 Addresses and Reset Values The following tables list the ’C2xx registers, the addresses at which they canbe accessed, and their reset values. Note that the registers mapped to internalI/O space on the ’C209 are at addresses different from those of other ’C2xxdevice...

Addresses and Reset Values A-3 Register Summary Table A–3. Addresses and Reset Values of On-Chip Registers Mapped to I/O Space (Continued) I/O Address Name Description Reset Value Other ’C2xx ’C209 IOSR – FFF6h 18xxh I/O status register BRD – FFF7h 0001h Baud-rate divisor register TCR FFFCh FFF8h 00...

Register Descriptions A-4 A.2 Register Descriptions The following figures summarize the content of the ’C2xx status and controlregisters that are divided into fields. (The other registers contain no controlbits; they simply hold a single 16-bit value.) Each figure in this section providesinformation...

Register Descriptions A-5 Register Summary Status Register ST0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X 0 X ÉÉÉ ÉÉÉ 1 † 1 X X X X X X X X X ARP OV OVM INTM DP All unmasked interrupts enabledAll unmasked interrupts disabled 01 Auxiliary register pointer Selects the current page(0, 1, 2, ..., 511) ...

Register Descriptions A-6 ’C2xx Interrupt Flag Register (IFR) — Except ’C209 — Data-Memory Address 0006h 15 6 5 4 3 2 1 0 ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ 0 0 0 0 0 0 0 Reserved † TXRXINT XINT RINT TINT INT2/INT3 HOLD/INT1 R/W1C Neither INT2 nor INT3 pendingINT2 and/or INT3 pending 01 Interrupt TXRXINT not pendi...

Register Descriptions A-7 Register Summary Interrupt Mask Register (IMR) — Except ’C209 — Data-Memory Address 0004h 15 6 5 4 3 2 1 0 ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ 0 0 0 0 0 0 0 Reserved † TXRXINT XINT RINT TINT INT2/INT3 HOLD/INT1 R/W INT2 and INT3 maskedINT2 and INT3 unmasked 01 Interrupt TXRXINT maskedInt...

Register Descriptions A-9 Register Summary Timer Control Register (TCR) — Except ’C209 — I/O Address FFF8h 15 12 11 10 9 6 5 4 3 0 ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ 0 0 0 0 0 0 0 Reserved † FREE SOFT PSC TRB TSS TDDR Start or restart timer.Stop timer. 0011 Stop after the next decrement of the TIM (hard stop).Stop a...

Register Descriptions A-11 Register Summary CLK Register — I/O Address FFE8h 15 1 0 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 0 0 Reserved † CLKOUT1 01 CLKOUT1 signal available at CLKOUT1 pinCLKOUT1 signal not available at CLKOUT1 pin R/W CLKOUT1 pin control † These reserved bits are always ...

Register Descriptions A-12 Synchronous Serial Port Control Register (SSPCR) — I/O Address FFF1h ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 15 ÁÁÁÁ ÁÁÁÁ 14 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 13 ÁÁÁÁ ÁÁÁÁ 12 ÁÁÁÁ ÁÁÁÁ 11 ÁÁÁÁ ÁÁÁÁ 10 ÁÁÁÁ ÁÁÁÁ 9 ÁÁÁÁ ÁÁÁÁ 8 ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 0 ÁÁÁÁ ÁÁÁÁ 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0 ÁÁÁÁ ÁÁÁÁ 0 ÁÁÁÁ ÁÁÁÁ 0 ÁÁÁÁ ÁÁÁÁ 0 ...

B-1 Appendix A TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison This appendix contains a table that compares the TMS320C1x, TMS320C2x,TMS320C2xx, and TMS320C5x instructions alphabetically. Each table entryshows the syntax for the instruction, indicates which devices support theinstruction, and desc...

Using the Instruction Set Comparison Table B-2 B.1 Using the Instruction Set Comparison Table To help you read the comparison table, this section provides an example of atable entry and a list of acronyms. B.1.1 An Example of a Table Entry In cases where more than one syntax is used, the first synta...

Using the Instruction Set Comparison Table B-3 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison B.1.2 Symbols and Acronyms Used in the Table The following table lists the instruction set symbols and acronyms usedthroughout this chapter: Table B–1. Symbols and Acronyms Used in the Instruction Set Su...

Using the Instruction Set Comparison Table B-4 Based on the device, this is how the indirect addressing operand {ind} isinterpreted: {ind} ’C1x: { * | *+ | *– } ’C2x: { * | *+ | *– | *0+| *0– | *BR0+ | *BR0– } ’C2xx: { * | *+ | *– | *0+| *0– | *BR0+ | *BR0– } ’C5x: { * | *+ | *– | *0+| *0– | *BR0+ |...

Enhanced Instructions B-5 TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison B.2 Enhanced Instructions An enhanced instruction is a single mnemonic that performs the functions ofseveral similar instructions. For example, the enhanced instruction ADDperforms the ADD, ADDH, ADDK, and ADLK functions and...

Instruction Set Comparison Table B-6 B.3 Instruction Set Comparison Table Syntax 1x 2x 2xx 5x Description ABS √ √ √ √ Absolute Value of Accumulator If the contents of the accumulator are less than zero,replace the contents with the 2s complement of thecontents. If the contents are ≥ 0, the accumulat...

C-1 Appendix A Program Examples This appendix provides: - A brief introduction to the process for generating executable program files. - Sample programs for implementing simple routines and using interrupts,I/O pins, the timer, and the serial ports. This appendix is not intended to teach you how to ...

About These Program Examples C-2 C.1 About These Program Examples Figure C–1 illustrates the basic process for creating assembly language filesand then generating executable files from them: 1) Use the ’C2xx assembler to create: - A command file ( c203.cmd in the figure) that defines address ranges ...

About These Program Examples C-3 Program Examples The program examples in Section C.2 and Section C.3 consist of code forshared files and task-specific files. Table C–1 describes the shared programs.Shared files contain code that is used by multiple task-specific files. The task-specific programs ar...

Shared Program Code C-5 Program Examples C.2 Shared Program Code Example C–1. Generic Command File (c203.cmd) /* Title: c203.cmd */ /* Generic command file for linking TMS320C2xx assembler files *//* input files: *.obj files */ /* output files: *.out file */ /* Map files: *.map file (optional) */ /*...

Task-Specific Program Code C-16 Example C–11. Testing and Using Automatic Baud-Rate Detection on Asynchronous Serial Port (autobaud.asm) * File: autobaud.asm * * Function: UART,auto baud test * * Locks to incoming baud rate if the first character * * is ”A” or ”a” & continuously echoes data rece...

Introduction to Generating Boot Loader Code C-23 Program Examples C.4 Introduction to Generating Boot Loader Code The ’C2xx on-chip boot loader boots software from an 8-bit external EPROMto a 16-bit external RAM at reset. This section introduces to the procedure forusing Texas Instruments developmen...

Introduction to Generating Boot Loader Code C-24 Example C–15. Linker Command File MEMORY{PAGE 0: /* PM – Program memory */ EX1_PM :ORIGIN=0H , LENGTH=0FEFFH /* External program RAM */ B0_PM :ORIGIN=0FF00H, LENGTH=0100H /* BLOCK MAP IN CNF=1 */ PAGE 1: /* DM – Data memory */ REGS :ORIGIN=0H , LENGTH...

D-1 Appendix A Submitting ROM Codes to TI The size of a printed circuit board is a consideration in many DSP applications.To make full use of the board space, Texas Instruments offers this ROM codeoption that reduces the chip count and provides a single-chip solution. This op-tion allows you to use ...

D-2 Figure D–1. TMS320 ROM Code Submittal Flow Chart Customer TMS320 Design Customer submits:— TMS320 New Code Release Form— Print Evaluation and Acceptance Form (PEAF)— Purchase order for mask prototypes— TMS320 code Texas Instruments responds:— Customer code input into TI system— Code sent back to...

D-3 Submitting ROM Codes to TI The TMS320 ROM code may be submitted in one of the following forms: - 5-1/4-in floppy: COFF format from macro-assembler/linker (preferred) - Modem (BBS): COFF format from macro-assembler/linker - EPROM (others): TMS27C64 - PROM: TBP28S166, TBP28S86 When code is submitt...

E-1 Appendix A Design Considerations for Using XDS510 Emulator This appendix assists you in meeting the design requirements of the TexasInstruments XDS510 emulator with respect to IEEE-1149.1 designs anddiscusses the XDS510 cable (manufacturing part number 2617698-0001).This cable is identified by a...

Designing Your Target System’s Emulator Connector (14-Pin Header) E-2 E.1 Designing Your Target System’s Emulator Connector (14-Pin Header) JTAG target devices support emulation through a dedicated emulation port.This port is accessed directly by the emulator and provides emulation func-tions that a...

Designing Your Target System’s Emulator Connector (14-Pin Header) E-3 Design Considerations for Using XDS510 Emulator Table E–1. 14-Pin Header Signal Descriptions Signal Description Emulator † State Target † State EMU0 Emulation pin 0 I I/O EMU1 Emulation pin 1 I I/O GND Ground PD(V CC ) Presence de...

Emulator Cable Pod E-5 Design Considerations for Using XDS510 Emulator E.3 Emulator Cable Pod Figure E–2 shows a portion of the emulator cable pod. The functional featuresof the pod are: - TDO and TCK_RET can be parallel-terminated inside the pod if requiredby the application. By default, these sign...

Emulator Cable Pod Signal Timing E-6 E.4 Emulator Cable Pod Signal Timing Figure E–3 shows the signal timings for the emulator cable pod. Table E–2defines the timing parameters illustrated in the figure. These timing parame-ters are calculated from values specified in the standard data sheets for th...

Emulation Timing Calculations E-7 Design Considerations for Using XDS510 Emulator E.5 Emulation Timing Calculations Example E–1 and Example E–2 help you calculate emulation timings in yoursystem. For actual target timing parameters, see the appropriate data sheetfor the device you are emulating. The...

Emulation Timing Calculations E-8 Example E–1. Key Timing for a Single-Processor System Without Buffers t pd ǒ TCK_RET-TMS ń TDI Ǔ + ƪ t d ǒ TMSmax Ǔ ) t su ǒ TTMS Ǔ ƫ t TCKfactor + (20 ns ) 10 ns) 0.4 + 75 ns, or 13.3 MHz t pd ǒ TCK_RET–TDO Ǔ + ƪ t d ǒ TTDO Ǔ ) t su ǒ TDOmin Ǔ ƫ t TCKfactor + (15 n...

Connections Between the Emulator and the Target System E-10 E.6 Connections Between the Emulator and the Target System It is extremely important to provide high-quality signals between the emulatorand the JTAG target system. You must supply the correct signal buffering, testclock inputs, and multipl...

Connections Between the Emulator and the Target System E-11 Design Considerations for Using XDS510 Emulator Figure E–5. Emulator Connections With Signal Buffering VCC Emulator header VCC GND 12 10 8 6 4 5 GND GND GND GND GND PD TCK_RET TCK TDO TDI TMS TRST EMU1 EMU0 9 11 7 3 1 2 14 13 JTAG device TC...

Connections Between the Emulator and the Target System E-12 E.6.2 Using a Target-System Clock Figure E–6 shows an application with the system test clock generated in thetarget system. In this application, the emulator’s TCK signal is left uncon-nected. Figure E–6. Target-System-Generated Test Clock ...

Connections Between the Emulator and the Target System E-13 Design Considerations for Using XDS510 Emulator E.6.3 Configuring Multiple Processors Figure E–7 shows a typical daisy-chained multiprocessor configuration thatmeets the minimum requirements of the IEEE 1149.1 specification. Theemulation si...

Physical Dimensions for the 14-Pin Emulator Connector E-14 E.7 Physical Dimensions for the 14-Pin Emulator Connector The JTAG emulator target cable consists of a 3-foot section of jacketed cablethat connects to the emulator, an active cable pod, and a short section of jack-eted cable that connects t...

Emulation Design Considerations E-16 E.8 Emulation Design Considerations This section describes the use and application of the scan path linker (SPL),which can simultaneously add all four secondary JTAG scan paths to the mainscan path. It also describes the use of the emulation pins and the configur...

Emulation Design Considerations E-17 Design Considerations for Using XDS510 Emulator Figure E–10. Connecting a Secondary JTAG Scan Path to a Scan Path Linker TDI TCK TDO TRST TMS TDO TRST TCK TMS TDI DTDI0 DTMS0 DTDO0 DTCK TDO TRST TCK TMS TDI SPL JTAG 0 JTAG N DTDI1 DTMS1 DTDO1 DTDI2 DTMS2 DTDO2 DT...

Emulation Design Considerations E-18 E.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL) Example E–3 and Example E–4 help you to calculate the key emulation tim-ings in the SPL secondary scan path of your system. For actual target timingparameters, see the appropriate device data sheet ...

Emulation Design Considerations E-20 E.8.3 Using Emulation Pins The EMU0/1 pins of TI devices are bidirectional, 3-state output pins. When inan inactive state, these pins are at high impedance. When the pins are active,they provide one of two types of output: - Signal Event. The EMU0/1 pins can be c...

Emulation Design Considerations E-22 - The bused EMU0/1 signals go into a programmable logic array devicePAL R whose function is to generate a low pulse on the EMU0/1-IN signal when a low level is detected on the EMU0/1-OUT signal. This pulse mustbe longer than one TCK period to affect the devices b...

Emulation Design Considerations E-23 Design Considerations for Using XDS510 Emulator Figure E–13. EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements of Greater Than 25 ns Open- collector drivers EMU0/1-IN Backplane Target board m TCK XCNT_ENABLE To Emulator EMU0 PAL Pullupresi...

Emulation Design Considerations E-24 You do not need to have devices on one target board stop devices on anothertarget board using the EMU0/1 signals (see the circuit in Figure E–14). In thisconfiguration, the global-stop capability is lost. It is important not to overloadEMU0/1 with more than 16 de...

Emulation Design Considerations E-25 Design Considerations for Using XDS510 Emulator Figure E–15. TBC Emulation Connections for n JTAG Scan Paths JTAG0 JTAGN TDI EMU1 TMS TDO EMU0 TRST TCK TDO TCK TRST EMU1 EMU0 TMS TDI Clock TDI1 TDI0 TCKO TMS5/EVNT3 TMS4/EVNT2 TMS3/EVNT1 TMS2/EVNT0 TMS1 TMS0 TDO T...

F-1 Appendix A Glossary A A0–A15: Collectively, the external address bus; the 16 pins are used in par- allel to address external data memory, program memory, or I/O space. ACC: See accumulator. ACCH: Accumulator high word. The upper 16 bits of the accumulator. See also accumulator. ACCL: Accumulator...

F-5 Glossary clock mode (clock generator): One of the modes which sets the internal CPU clock frequency to a fraction or multiple of the frequency of the inputclock signal CLKIN. The ’C209 has two clock modes ( ÷ 2 and × 2); other ’C2xx devices have four clock modes ( ÷ 2, × 1, × 2, and × 4). clock ...

F-7 Glossary decode phase: The phase of the pipeline in which the instruction is de- coded. See also pipeline; instruction-fetch phase; operand-fetch phase; instruction-execute phase. delta interrupt: An asynchronous serial port interrupt (TXRXINT) that is generated if a change takes place on one of...

F-11 Glossary IC: (Used in earlier documentation.) See interrupt control register (ICR). ICR: See interrupt control register (ICR). IFR: See interrupt flag register (IFR). immediate addressing: One of the methods for obtaining data values used by an instruction; the data value is a constant embedded...

F-12 INT1–INT3: Three external pins used to generate general-purpose hard- ware interrupts. internal interrupt: A hardware interrupt caused by an on-chip peripheral. interrupt: A signal sent to the CPU that (when not masked or disabled) forces the CPU into a subroutine called an interrupt service ro...

F-14 LSB: Least significant bit. The lowest order bit in a word. When used in plural form (LSBs), refers to a specified number of low-order bits, beginningwith the lowest order bit and counting to the left. For example, the fourLSBs of a 16-bit value are bits 0 through 3. See also MSB. M machine cyc...

F-15 Glossary MSTACK: See micro stack. multiplier: A part of the CPU that performs 16-bit × 16-bit multiplication and generates a 32-bit product. The multiplier operates using either signedor unsigned 2s-complement arithmetic. N next AR: See next auxiliary register. next auxiliary register: The regi...

F-18 program control logic: Logic circuitry that decodes instructions, manages the pipeline, stores status of operations, and decodes conditional opera-tions. program counter (PC): A register that indicates the location of the next instruction to be executed. program read bus (PRDB): A 16-bit intern...

F-22 status registers ST0 and ST1: Two 16-bit registers that contain bits for de- termining processor modes, addressing pointer values, and indicatingvarious processor conditions and arithmetic logic results. These regis-ters can be stored into and loaded from data memory, allowing the statusof the ...

F-26 Z zero fill: Fill the unused low or high order bits in a register with zeros. Glossary

Index Index-1 Index * operand 6-10 *+ operand 6-10 *– operand 6-10 *0+ operand 6-10 *0– operand 6-10 *BR0+ operand 6-11 *BR0– operand 6-11 14-pin connector, dimensions E-15 14-pin header header signals E-2 JTAG E-2 4-level pipeline operation 5-7 A A0–A15 (external address bus) definition 4-3 shown i...