Texas Instruments PCI7621 - Manuals

vii Section Title Page 7 OHCI Controller Programming Model 7−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Vendor ID Register 7−2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Device ID Register 7−2 . . . . . . . . . . . . . . . . . . ....

viii Section Title Page 8.15 Vendor ID Register 8−12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16 Host Controller Control Register 8−13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.17 Self-ID Buffer Pointer Register 8−14 . . . . . . . . ...

ix Section Title Page 10.4 Vendor-Dependent Register 10−6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Power-Class Programming 10−7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash Media Controller Programming Model 11−1 . . . . . . . . . . ....

x Section Title Page 12.16 Slot Information Register 12−10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.17 Capability ID and Next Item Pointer Registers 12−11 . . . . . . . . . . . . . . . . . 12.18 Power Management Capabilities Register 12−12 . . . . . . . . . . . . . . ...

xi Section Title Page 14 Electrical Characteristics 14−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 Absolute Maximum Ratings Over Operating Temperature Ranges 14−1 . 14.2 Recommended Operating Conditions 14−1 . . . . . . . . . . . . . . . . . . . . . . ....

xii List of Illustrations Figure Title Page 2−1 PCI7621 GHK/ZHK-Package Terminal Diagram 2−1 . . . . . . . . . . . . . . . . . . . . . 2−2 PCI7421 GHK/ZHK-Package Terminal Diagram 2−2 . . . . . . . . . . . . . . . . . . . . . 2−3 PCI7611 GHK/ZHK-Package Terminal Diagram 2−3 . . . . . . . . . . . . ....

xiii List of Tables Table Title Page 1−1 Terms and Definitions 1−7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 Signal Names by GHK Terminal Number 2−5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 CardBus PC Card Signal Names Sorted Alphabeti...

1−1 1 Introduction The Texas Instruments PCI7621 controller is an integrated dual-socket UltraMedia PC Card controller, Smart Cardcontroller, IEEE 1394 open HCI host controller and PHY, and flash media controller. This high-performance integratedsolution provides the latest in PC Card, Smart Card, I...

1−4 1.2 Features The PCI7x21/PCI7x11 controller supports the following features: • PC Card Standard 8.1 compliant • PCI Bus Power Management Interface Specification 1.1 compliant • Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant • PCI Local Bus Specification Revision 2....

1−5 • External cycle timer control for customized synchronization • Extended resume signaling for compatibility with legacy DV components • PHY-Link logic performs system initialization and arbitration functions • PHY-Link encode and decode functions included for data-strobe bit level encoding • PHY...

1−6 • SD Memory Card Specifications, SD Group, March 2000 • Memory Stick Format Specification, Version 2.0 (Memory Stick-Pro) • ISO Standards for Identification Cards ISO/IEC 7816 • SD Host Controller Standard Specification, rev. 1.0 • Memory Stick Format Specification, Sony Confidential, ver. 2.0 •...

1−7 1.5 Terms and Definitions Terms and definitions used in this document are given in Table 1−1. Table 1−1. Terms and Definitions TERM DEFINITIONS AT AT (advanced technology, as in PC AT) attachment interface ATA driver An existing host software component that loads when any flash media adapter and...

2−1 2 Terminal Descriptions The PCI7x21/PCI7x11 controller is available in the 288-terminal MicroStar BGA  package (GHK) or the 288-terminal lead-free (Pb, atomic number 82) MicroStar BGA  package (ZHK). Figure 2−1 is a pin diagram of the PCI7621 package. Figure 2−2 is a pin diagram of the PCI7421...

2−5 Table 2−1. Signal Names by GHK Terminal Number TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER CardBus PC Card 16-Bit PC Card TERMINAL NUMBER CardBus PC Card 16-Bit PC Card A02 A_CAUDIO A_BVD2(SPKR) C06 A_CAD22 A_A4 A03 A_CVS1 A_VS1 C07 A_CAD19 A_A25 A04 A_CAD25 A_A1 C08 ...

2−9 Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER AD0 W13 A_CAD5 A13 A_CPERR F10 B_CAD30 A16 AD1 N11 A_CAD6 F12 A_CREQ E07 B_CAD31 B15 AD2 U12 A_CAD7 C13 A_CRST A06 B_CAUDI...

2−11 Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER AD0 W13 A_A5 B06 A_INPACK E07 B_CE1 M18 AD1 N11 A_A6 G09 A_IORD C11 B_CE2 L19 AD2 U12 A_A7 B07 A_IOWR E11 B_D0 C16 AD3 V12...

2−13 2.1 Detailed Terminal Descriptions Please see Table 2−4 through Table 2−19 for more detailed terminal descriptions. The following list defines thecolumn headings and the abbreviations used in the detailed terminal description tables. • I/O Type: − I = Digital input − O = Digital output − I/O = ...

2−14 Table 2−4. Power Supply Terminals Output description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the power supply terminals. TERMINAL DESCRIPTION I/O INPUT EXTERNAL PIN STRAPPING NAME NUMBER DESCRIPTION I/O TYPE INPUT EXTERNAL COMPONENTS PIN STRAPP...

2−16 Table 2−7. PCI Address and Data Terminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data terminals. TERMINAL DESCRIPTION I/O INPUT OUTPUT POWER NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT POWER RAIL AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD2...

2−17 Table 2−8. PCI Interface Control Terminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control terminals. TERMINAL DESCRIPTION I/O INPUT OUTPUT POWER EXTERNAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT POWER RAIL EXTERNAL COMPONENTS DEVSEL N08 P...

2−18 Table 2−9. Multifunction and Miscellaneous Terminals The power rail designation is not applicable for the multifunction and miscellaneous terminals. TERMINAL DESCRIPTION I/O INPUT OUTPUT PU/ EXTERNAL PIN STRAPPING NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD EXTERNAL COMPONENTS PIN STRAPPI...

2−19 Table 2−10. 16-Bit PC Card Address and Data Terminals External components are not applicable for the 16-bit PC Card address and data terminals. If any 16-bit PC Cardaddress and data terminal is unused, then the terminal may be left floating. SOCKET A TERMINAL SOCKET B TERMINAL† DESCRIPTION I/O ...

2−20 Table 2−11. 16-Bit PC Card Interface Control Terminals External components are not applicable for the 16-bit PC Card interface control terminals. If any 16-bit PC Cardinterface control terminal is unused, then the terminal may be left floating. SKT A TERMINAL SKT B TERMINAL† DESCRIPTION I/O POW...

2−22 Table 2−12. CardBus PC Card Interface System Terminals A 33- Ω to 47- Ω series damping resistor (per PC Card specification) is the only external component needed for terminals B08 (A_CCLK) and H17 (B_CCLK). If any CardBus PC Card interface system terminal is unused, then theterminal may be left...

2−23 Table 2−13. CardBus PC Card Address and Data Terminals External components are not applicable for the 16-bit PC Card address and data terminals. If any CardBus PC Cardaddress and data terminal is unused, then the terminal may be left floating. SKT A TERMINAL SKT B TERMINAL† DESCRIPTION I/O INPU...

2−24 Table 2−14. CardBus PC Card Interface Control Terminals If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating. SKT A TERMINAL SKT B TERMINAL† DESCRIPTION I/O INPUT OUTPUT PU/ POWER NAME NO. NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD POWER RAI...

2−25 Table 2−14. CardBus PC Card Interface Control Terminals (Continued) SKT A TERMINAL SKT B TERMINAL† DESCRIPTION I/O INPUT OUTPUT PU/ POWER NAME NO. NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD POWER RAIL A_CSTOP A09 B_CSTOP J17 CardBus stop. CSTOP is driven by a CardBus targetto request the...

2−29 Table 2−19. Smart Card Terminals † If any Smart Card terminal is unused, then the terminal may be left floating, except for SC_VCC_5V which must beconnected to 5 V. TERMINAL DESCRIPTION I/O INPUT OUTPUT PU/ POWER EXTERNAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD POWER RAIL EXTERNAL PAR...

3−1 3 Feature/Protocol Descriptions The following sections give an overview of the PCI7x21/PCI7x11 controller. Figure 3−1 shows the connections to thePCI7x21/PCI7x11 controller. The PCI interface includes all address/data and control signals for PCI protocol. Theinterrupt interface includes terminal...

3−2 3.2 I/O Characteristics The PCI7x21/PCI7x11 controller meets the ac specifications of the PC Card Standard (release 8.1) and the PCI LocalBus Specification. Figure 3−2 shows a 3-state bidirectional buffer. Section 14.2, Recommended OperatingConditions, provides the electrical characteristics of ...

3−3 3.4.2 Device Resets The following are the requirements for proper reset of the PCI7x21/PCI7x11 controller: 1. GRST and PRST must both be asserted at power on. 2. GRST must be asserted for at least 2 ms at power on 3. PRST must be deasserted either at the same time or after GRST is asserted 4. PC...

3−4 as bus master, by reading and writing PCI configuration registers . Setting bit 3 (SBDETECT) in the serial bus control/status register (PCI offset B3h, see Section 4.50) causes the PCI7x21/PCI7x11 controller to route the SDAand SCL signals to the SDA and SCL terminals, respectively. The read/wri...

3−5 3.4.5 Function 2 (OHCI 1394) Subsystem Identification The subsystem identification register is used for system and option card identification purposes. This register canbe initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCIconfiguration spa...

3−6 3.5.1 PC Card Insertion/Removal and Recognition The PC Card Standard (release 8.1) addresses the card-detection and recognition process through an interrogationprocedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation,card voltage requir...

3−7 Table 3−2. PC Card—Card Detect and Voltage Sense Connections CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Key Interface VCC VPP/VCORE Ground Ground Open Open 5 V 16-bit PC Card 5 V Per CIS (VPP) Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V Per CIS (VPP) Ground Ground Ground Ground 5 V 1...

3−8 3.5.5 Power Switch Interface The power switch interface of the PCI7x21/PCI7x11 controller is a 3-pin serial interface. This 3-pin interface isimplemented such that the PCI7x21/PCI7x11 controller can connect to both the TPS2226 and TPS2228 powerswitches. Bit 10 (12V_SW_SEL) in the general control...

3−9 3.5.7 Integrated Pullup Resistors for PC Card Interface The PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit PC Cardconfigurations. The PCI7x21/PCI7x11 controller has integrated all of these pullup resistors and requires no additionalexternal com...

3−11 • Frequency stability (overtemperature and age): A crystal with ± 30 ppm frequency stability is recommended for adequate margin. NOTE: The total frequency variation must be kept below ± 100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs betw...

3−13 Figure 3−10 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W commandbit must be set to 1 to indicate a read-data transfer. In addition, the PCI7x21/PCI7x11 master must acknowledgereception of the read bytes from the slave transmitter. The slave tr...

3−14 Table 3−9. EEPROM Loading Map SERIAL ROM OFFSET BYTE DESCRIPTION 00h CardBus function indicator (00h) 01h Number of bytes (20h) PCI 04h, command register, function 0, bits 8, 6−5, 2−0 02h [7] Command register, bit 8 [6] Command register, bit 6 [5] Command register, bit 5 [4:3] RSVD [2] Command ...

3−16 Table 3−9. EEPROM Loading Map (Continued) SERIAL ROM OFFSET BYTE DESCRIPTION 49h PCI 94h, slot 0 3.3 V maximum current 4Ah PCI 98h, slot 1 3.3 V maximum current 4Bh PCI 9Ch, slot 2 3.3 V maximum current 4Ch Reserved (PCI A0h, slot 3 3.3 V maximum current) 4Dh Reserved (PCI A4h, slot 4 3.3 V max...

3−17 3.7.1 PC Card Functional and Card Status Change Interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and areindicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by16-bit I/O PC...

3−18 Table 3−11. PC Card Interrupt Events and Description CARD TYPE EVENT TYPE SIGNAL DESCRIPTION Battery conditions CSC BVD1(STSCHG)//CSTSCHG A transition on BVD1 indicates a change in thePC Card battery conditions. 16-bit memory Battery conditions (BVD1, BVD2) CSC BVD2(SPKR)//CAUDIO A transition o...

3−19 Table 3−10 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PCCard-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to theflag bit to clear and the other is by reading the flag bit...

3−20 The INTRTIE and TIEALL bits affect the read-only value provided through accesses to the interrupt pin register (PCIoffset 3Dh, see Section 4.24). Table 3−12 summarizes the interrupt signaling modes. Table 3−12. Interrupt Pin Register Cross Reference INTRTIE Bit TIEALL Bit INTPIN Function 0 (Car...

3−22 3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR) The PCI7x21/PCI7x11 controller requires 1.5-V core voltage. The core power can be supplied by thePCI7x21/PCI7x11 controller itself using the internal LDO-VR. The core power can alternatively be supplied by an external power supply through ...

3−23 3.8.5 16-Bit PC Card Power Management The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWNbit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) are provided for 16-bitPC Card power management. The CO...

3−24 places the PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to thecontroller unless a PCI transaction is currently in process (GNT is asserted). It is important that the PCI bus not beparked on the PCI7x21/PCI7x11 controller when SUSPEND is asserted b...

3−25 3.8.9 PCI Power Management 3.8.9.1 CardBus Power Management (Functions 0 and 1) The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructurerequired to let the operating system control the power of PCI functions. This is done by defining a stand...

3−26 For more information on PCI power management, see the PCI Bus Power Management Interface Specification forPCI to CardBus Bridges. 3.8.9.2 OHCI 1394 (Function 2) Power Management The PCI7x21/PCI7x11 controller complies with the PCI Bus Power Management Interface Specification. Thecontroller supp...

3−27 The Texas Instruments PCI7x21/PCI7x11 controller addresses these D3 wake-up issues in the following manner: • Two resets are provided to handle preservation of PME context bits: − Global reset (GRST) is used only on the initial boot up of the system after power up. It places thePCI7x21/PCI7x11 ...

3−30 3.9 IEEE 1394 Application Information 3.9.1 PHY Port Cable Connection TPA+ TPA− TPB+ TPB− Cable Port CPS TPBIAS 56 Ω 56 Ω 56 Ω 56 Ω 5 k Ω 1 µ F 400 k Ω 220 pF (see Note A) PCI7x21/ PCI7x11 Cable Power Pair Cable Pair A Cable Pair B Outer Shield Termination NOTE A: IEEE Std 1394-1995 calls for a...

3−31 Outer Cable Shield Chassis Ground Figure 3−19. Non-DC Isolated Outer Shield Termination 3.9.2 Crystal Selection The PCI7x21/PCI7x11 controller is designed to use an external 24.576-MHz crystal connected between the XI andXO terminals to provide the reference for an internal oscillator circuit. ...

3−32 X124.576 MHz IS X1 CPHY + CBD X0 C10 C9 Figure 3−20. Load Capacitance for the PCI7x21/PCI7x11 PHY The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noiseintroduced into the PHY phase-lock loop, and minimizing any emissions from the...

4−1 4 PC Card Controller Programming Model This chapter describes the PCI7x21/PCI7x11 PCI configuration registers that make up the 256-byte PCI configurationheader for each PCI7x21/PCI7x11 function. There are some bits which affect both CardBus functions, but which, inorder to work properly, must be...

4−2 Table 4−2. Functions 0 and 1 PCI Configuration Register Map (Continued) REGISTER NAME OFFSET CardBus I/O base register 0 2Ch CardBus I/O limit register 0 30h CardBus I/O base register 1 34h CardBus I/O limit register 1 38h Bridge control † Interrupt pin Interrupt line 3Ch Subsystem ID ‡ Subsyste...

4−3 4.3 Device ID Register Functions 0 and 1 This read-only register contains the device ID assigned by TI to the PCI7x21/PCI7x11 CardBus controller functions(PCI functions 0 and 1). Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Device ID—Smart Card enabled Type R R R R R R R R R R R R R R R R Defa...

4−4 4.4 Command Register The PCI command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functionsadhere to the definitions in the PCI Local Bus Specification (see Table 4−3). None of the bit functions in this registerare shared among the PCI7x21/PCI7x11 PCI func...

4−5 Table 4−3. Command Register Description (continued) BIT SIGNAL TYPE FUNCTION 1 MEM_EN RW Memory space enable. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cyclesin PCI memory space. 0 = Disables the PCI7x21/PCI7x11 response to memory space accesses (default)1 = Enabl...

4−6 Table 4−4. Status Register Description (continued) BIT SIGNAL TYPE FUNCTION 4 CAPLIST R Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCIcapabilities are implemented. The linked list of PCI power-management capabilities is implement...

4−7 4.9 Latency Timer Register The latency timer register specifies the latency timer for the PCI7x21/PCI7x11 controller, in units of PCI clock cycles.When the PCI7x21/PCI7x11 controller is a PCI bus initiator and asserts FRAME, the latency timer begins countingfrom zero. If the latency timer expire...

4−8 4.12 CardBus Socket Registers/ExCA Base Address Register This register is programmed with a base address referencing the CardBus socket registers and the memory-mappedExCA register set. Bits 31−12 are read/write, and allow the base address to be located anywhere in the 32-bit PCImemory address s...

4−9 4.14 Secondary Status Register The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicatesCardBus-related device information to the host system. This register is very similar to the PCI status register (PCIoffset 06h, see Section 4.5), and status b...

4−10 4.15 PCI Bus Number Register The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to whichthe PCI7x21/PCI7x11 controller is connected. The PCI7x21/PCI7x11 controller uses this register in conjunction withthe CardBus bus number and subordinate bu...

4−11 4.18 CardBus Latency Timer Register The CardBus latency timer register is programmed by the host system to specify the latency timer for thePCI7x21/PCI7x11 CardBus interface, in units of CCLK cycles. When the PCI7x21/PCI7x11 controller is a CardBusinitiator and asserts CFRAME, the CardBus laten...

4−12 4.20 CardBus Memory Limit Registers 0, 1 These registers indicate the upper address of a PCI memory address range. They are used by the PCI7x21/PCI7x11controller to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward aCardBus cycle to PCI. Bits 31−12...

4−13 4.22 CardBus I/O Limit Registers 0, 1 These registers indicate the upper address of a PCI I/O address range. They are used by the PCI7x21/PCI7x11controller to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward aCardBus cycle to PCI. The lower 16 bits ...

4−14 4.24 Interrupt Pin Register The value read from this register is function dependent. The default value for function 0 is 01h (INTA), the default valuefor function 1 is 02h (INTB), the default value for function 2 is 03h (INTC), the default value for function 3 is 01h (INTA),the default value fo...

4−15 Register: Interrupt pin Offset: 3Dh Type: Read-only Default: 01h (function 0), 02h (function 1), 03h (function 2), 04h (function 3), 04h (function 4), 04h (function 5) Table 4−6. Interrupt Pin Register Cross Reference INTRTIE BIT (BIT 29, OFFSET 80h) TIEALL BIT (BIT 28, OFFSET 80h) INTPIN FUNCT...

4−16 Table 4−7. Bridge Control Register Description (Continued) BIT SIGNAL TYPE FUNCTION 6 † CRST RW CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRSTsignal can also be asserted by passing a PRST assertion to CardBus. 0 = CRST is deasserted.1 = CRST ...

4−17 4.27 Subsystem ID Register The subsystem ID register, used for system and option card identification purposes, may be required for certainoperating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in thesystem control register (PCI offset 80h, see ...

4−18 4.29 System Control Register System-level initializations are performed through programming this doubleword register. Some of the bits are globalin nature and must be accessed only through function 0. See Table 4−8 for a complete description of the registercontents. Bit 31 30 29 28 27 26 25 24 ...

4−19 Table 4−8 . System Control Register Description (continued) BIT SIGNAL TYPE FUNCTION 22 ‡ CBRSVD RW CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are drivenlow when a CardBus card has been inserted. When this bit is low, these signals are placed in ahigh...

4−21 4.31 General Control Register The general control register provides top level PCI arbitration control. It also provides the ability to disable the 1394OHCI function and provides control over miscellaneous new functionality. See Table 4−9 for a complete descriptionof the register contents. Bit 1...

4−22 Table 4−9. General Control Register Description BIT SIGNAL TYPE FUNCTION 15 ‡ FM_PWR_CTRL _POL RW Flash media power control pin polarity. This bit controls the polarity of the MC_PWR_CTRL_0 andMC_PWR_CTRL_1 terminals. 0 = MC_PWR_CTRL_x terminals are active low (default)1 = MC_PWR_CTRL_x termina...

4−23 4.32 General-Purpose Event Status Register The general-purpose event status register contains status bits that are set when general events occur, and can beprogrammed to generate general-purpose event signaling through GPE. See Table 4−10 for a complete descriptionof the register contents. Bit ...

4−24 4.33 General-Purpose Event Enable Register The general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4−11 for acomplete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name General-purpose event enable Type RW RW R RW RW RW RW RW Default 0 0...

4−26 4.36 Multifunction Routing Status Register The multifunction routing status register is used to configure the MFUNC6−MFUNC0 terminals. These terminals maybe configured for various functions. This register is intended to be programmed once at power-on initialization. Thedefault value for this re...

4−27 Table 4−14. Multifunction Routing Status Register Description (Continued) BIT SIGNAL TYPE FUNCTION 7−4 ‡ MFUNC1 RW Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminalas follows: 0000 = GPI1 0100 = OHCI_LED 1000 = CAUDPWM 1100 = LEDA1 0001...

4−28 4.38 Card Control Register The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register, and theenable bit is shared between functions 0 and 1. See Table 4−16 for a complete description of the register contents. The RI_OUT signal is enabled through th...

4−29 4.39 Device Control Register The device control register is provided for PCI1130 compatibility. It contains bits that are shared between functions0 and 1. The interrupt mode select is programmed through this register. The socket-capable force bits are alsoprogrammed through this register. See T...

4−30 4.40 Diagnostic Register The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s must be writtento it. See Table 4−18 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name Diagnostic Type RW R RW RW RW RW RW RW Default ...

4−31 4.41 Capability ID Register The capability ID register identifies the linked list item as the register for PCI power management. The register returns01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer andthe value. Bit 7 6 5 4 3 2 1 0 N...

4−32 4.43 Power Management Capabilities Register The power management capabilities register contains information on the capabilities of the PC Card function relatedto power management. Both PCI7x21/PCI7x11 CardBus bridge functions support D0, D1, D2, and D3 power states.Default register value is FE1...

4−33 4.44 Power Management Control/Status Register The power management control/status register determines and changes the current power state of thePCI7x21/PCI7x11 CardBus function. The contents of this register are not affected by the internally generated resetcaused by the transition from the D3 ...

4−34 4.45 Power Management Control/Status Bridge Support Extensions Register This register supports PCI bridge-specific functionality. It is required for all PCI-to-PCI bridges. See Table 4−21 fora complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name Power management control/statu...

4−35 4.47 Serial Bus Data Register The serial bus data register is for programmable serial bus byte reads and writes. This register represents the datawhen generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data,the serial bus index register mus...

4−36 4.49 Serial Bus Slave Address Register The serial bus slave address register is for programmable serial bus byte read and write transactions. To write a byte,the serial bus data register must be programmed with the data, the serial bus index register must be programmedwith the byte address, and...

5−1 5 ExCA Compatibility Registers (Functions 0 and 1) The ExCA (exchangeable card architecture) registers implemented in the PCI7x21/PCI7x11 controller areregister-compatible with the Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value,which is compatible with the l...

5−2 16-Bit Legacy-Mode Base Address PCI7x21/PCI7x11 Configuration Registers 10h CardBus Socket/ExCA Base Address Note: The 16-bit legacy-mode base addressregister is shared by function 0 and 1 asindicated by the shading. 44h Index Data Host I/O Space PC Card A ExCA Registers PC Card B ExCA Registers...

5−3 Table 5−1. ExCA Registers and Offsets EXCA REGISTER NAME PCI MEMORY ADDRESS OFFSET (HEX) EXCA OFFSET (CARD A) EXCA OFFSET (CARD B) Identification and revision ‡ 800 00 40 Interface status 801 01 41 Power control † 802† 02 42 Interrupt and general control † 803† 03 43 Card status change † 804† 04...

5−5 5.1 ExCA Identification and Revision Register This register provides host software with information on 16-bit PC Card support and 82365SL-DF compatibility. SeeTable 5−2 for a complete description of the register contents. NOTE: If bit 5 (SUBSYRW) in the system control register is 1, then this re...

5−6 5.2 ExCA Interface Status Register This register provides information on current status of the PC Card interface. An X in the default bit values indicatesthat the value of the bit after reset depends on the state of the PC Card interface. See Table 5−3 for a completedescription of the register c...

5−7 5.3 ExCA Power Control Register This register provides PC Card power control. Bit 7 of this register enables the 16-bit outputs on the socket interface,and can be used for power management in 16-bit PC Card applications. See Table 5−5 for a complete descriptionof the register contents. Bit 7 6 5...

5−8 5.4 ExCA Interrupt and General Control Register This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. SeeTable 5−6 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name ExCA interrupt and general control Type RW RW...

5−9 5.5 ExCA Card Status-Change Register The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PCCard functions. The register enables these interrupt sources to generate an interrupt to the host. When the interruptsource is disabled, the ...

5−10 5.6 ExCA Card Status-Change Interrupt Configuration Register This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC interrupt sources. SeeTable 5−8 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name ExCA card status-change interrupt ...

5−11 5.7 ExCA Address Window Enable Register The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. Bydefault, all windows to the card are disabled. The PCI7x21/PCI7x11 controller does not acknowledge PCI memoryor I/O cycles to the card if the corr...

5−12 5.8 ExCA I/O Window Control Register The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. SeeTable 5−10 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window control Type RW RW RW RW RW RW RW RW Default 0...

5−15 5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4.The 8 bits of these registers correspond to bits A19−A12 of the start address. Bit 7 6 5 4 3 2 1 0 Name ExCA memory w...

5−16 5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the start address. In addition, the memorywindo...

5−17 5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4.The 8 bits of these registers correspond to bits A19−A12 of the end address. Bit 7 6 5 4 3 2 1 0 Name ExCA memory windows...

5−19 5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,and 4. The 8 bits of these registers correspond to bits A19−A12 of the offset address. Bit 7 6 5 4 3 2 1 0 Name ExCA memor...

5−20 5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,and 4. The lower 6 bits of these registers correspond to bits A25−A20 of the offset address. In addition, the writepro...

5−21 5.19 ExCA Card Detect and General Control Register This register controls how the ExCA registers for the socket respond to card removal. It also reports the status of theVS1 and VS2 signals at the PC Card interface. Table 5−14 describes each bit in the ExCA card detect and generalcontrol regist...

5−22 5.20 ExCA Global Control Register This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits inthis register are retained for 82365SL-DF compatibility. See Table 5−15 for a complete description of the registercontents. Bit 7 6 5 4 3 2 1 0 Na...

5−24 5.23 ExCA Memory Windows 0−4 Page Registers The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decodingaddresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. Byprogramming this register to a nonzer...

6−1 6 CardBus Socket Registers (Functions 0 and 1) The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report andcontrol socket-specific functions. The PCI7x21/PCI7x11 controller provides the CardBus socket/ExCA base addressregister (PCI offset 10h, s...

6−2 6.1 Socket Event Register This register indicates a change in socket status has occurred. These bits do not indicate what the change is, onlythat one has occurred. Software must read the socket present state register for current status. Each bit in this registercan be cleared by writing a 1 to t...

6−3 6.2 Socket Mask Register This register allows software to control the CardBus card events which generate a status change interrupt. The stateof these mask bits does not prevent the corresponding bits from reacting in the socket event register (offset 00h, seeSection 6.1). See Table 6−3 for a com...

6−4 6.3 Socket Present State Register This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, seeSection 6.4), as well as general socket interface status, are reflected here. Information about PC Card V CC support and card type is only upd...

6−5 Table 6−4. Socket Present State Register Description (Continued) BIT SIGNAL TYPE FUNCTION 9 † BADVCCREQ R Bad VCC request. This bit indicates that the host software has requested that the socket be powered atan invalid voltage. 0 = Normal operation (default)1 = Invalid VCC request by host softwa...

6−6 Table 6−5. Socket Force Event Register Description BIT SIGNAL TYPE FUNCTION 31−15 RSVD R Reserved. These bits return 0s when read. 14 CVSTEST W Card VS test. When this bit is set, the PCI7x21/PCI7x11 controller reinterrogates the PC Card, updatesthe socket present state register (offset 08h, see...

6−7 6.5 Socket Control Register This register provides control of the voltages applied to the socket V PP and V CC . The PCI7x21/PCI7x11 controller ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6−6for a complete description of the regist...

6−8 6.6 Socket Power Management Register This register provides power management control over the socket through a mechanism for slowing or stopping theclock on the card interface when the card is idle. See Table 6−7 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23...

7−1 7 OHCI Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 1394 open hostcontroller interface. All registers are detailed in the same format: a brief description for each register is followed bythe register offset and a...

7−2 7.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.The vendor ID assigned to Texas Instruments is 104Ch. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default 0 ...

7−5 7.5 Class Code and Revision ID Register The class code and revision ID register categorizes the PCI7x21/PCI7x11 controller as a serial bus controller (0Ch),controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision isindicated in the least signifi...

7−6 7.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the PCI7x21/PCI7x11 PCI header type and no built-inself-test. See Table 7−6 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Header type and BIST ...

7−7 7.9 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TIextension registers. When BIOS writes all 1s to this register, the value read back is FFFF C000h, indicating that atleast 16K bytes of memory address sp...

7−8 7.10 CardBus CIS Base Address Register The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0s when read. SeeTable 7−9 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CardBus CIS base address T...

7−9 7.12 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register canbe initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCIconfiguration space (see Section...

7−10 7.14 Interrupt Line Register The interrupt line register communicates interrupt line routing information. See Table 7−11 for a complete descriptionof the register contents. Bit 7 6 5 4 3 2 1 0 Name Interrupt line Type RW RW RW RW RW RW RW RW Default 1 1 1 1 1 1 1 1 Register: Interrupt line Offs...

7−11 7.16 Minimum Grant and Maximum Latency Register The minimum grant and maximum latency register communicates to the system the desired setting of bits 15−8 inthe latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6).If a serial EEPROM is ...

7−12 7.18 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to thenext capability item. See Table 7−15 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4...

7−13 7.19 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the PCI7x21/PCI7x11 controller related toPCI power management. See Table 7−16 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ...

7−14 7.20 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power-managementfunction. This register is not affected by the internally generated reset caused by the transition from the D3 hot to D0 state. See Tab...

7−15 7.22 PCI PHY Control Register The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 7−19 for a completedescription of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PCI PHY control Type R R R R R R R R R R R R R R R R Default ...

7−16 7.23 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 7−20 fora complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PCI miscellaneous configuratio...

7−17 Table 7−20. PCI Miscellaneous Configuration Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 1 ‡ DISABLE_ PCIGATE RW When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test featureonly and must be cleared to 0 (all applications). 0 ‡ K...

7−18 Table 7−21. Link Enhancement Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 11 RSVD R Reserved. Bit 11 returns 0 when read. 10 ‡ enab_mpeg_ts RW Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled forMPEG CIP transmit streams (FMT ...

7−19 7.26 GPIO Control Register The GPIO control register has the control and status bits for GPIO0, GPIO1, GPIO2, and GPIO3 ports. Upon reset,GPIO0 and GPIO1 default to bus manager contender (BMC) and link power status terminals, respectively. The BMCterminal can be configured as GPIO0 by setting b...

8−1 8 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (seeSection 7.8). These registers are the primary interface ...

8−4 8.1 OHCI Version Register The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. SeeTable 8−2 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name OHCI version Type R R R R R R R RU R ...

8−5 8.2 GUID ROM Register The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCIversion register at OHCI offset 00h (see Section 8.1) is set to 1. See Table 8−3 for a complete description of theregister contents. Bit 31 30 29 28 27 26 25 24 23 22 21...

8−6 8.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the PCI7x21/PCI7x11 controller attemptsa retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. SeeTable 8−4 for a complete descriptio...

8−7 8.5 CSR Compare Register The CSR compare register accesses the bus management CSR registers from the host through compare-swapoperations. This register contains the data to be compared with the existing value of the CSR resource. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CSR compa...

8−8 8.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offsetFFFF F000 0400h. See Table 8−6 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Confi...

8−9 8.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8−7 for a completedescription of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Bus options Type RW RW RW RW RW R R R RW RW RW RW RW RW RW RW ...

8−10 8.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the thirdquadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializesto 0s on a system (hardware) reset, which i...

8−11 8.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the startaddress of 1394 configuration ROM for this node. See Table 8−8 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23...

8−12 8.14 Posted Write Address High Register The posted write address high register communicates error information if a write request is posted and an error occurswhile writing the posted data packet. See Table 8−10 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 ...

8−13 8.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the PCI7x21/PCI7x11 controller. SeeTable 8−11 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Host controller co...

8−14 Table 8−11. Host Controller Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 22 aPhyEnhanceEnable RSC When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to1 to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is ...

8−15 8.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-IDpacket errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8−12 for a complete descriptionof the register contents. Bit 31 30...

8−16 8.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32isochronous data channels. A read from either the set register or clear register returns the content of the isochronousreceive channel mask h...

8−17 Table 8−13. Isochronous Receive Channel Mask High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 6 isoChannel38 RSC When bit 6 is set to 1, the controller is enabled to receive from isochronous channel number 38. 5 isoChannel37 RSC When bit 5 is set to 1, the controller is ena...

8−18 8.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various PCI7x21/PCI7x11 interrupt sources. Theinterrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in thecorresponding bit in the set register. The ...

8−20 8.22 Interrupt Mask Register The interrupt mask set/clear register enables the various PCI7x21/PCI7x11 interrupt sources. Reads from either theset register or the clear register always return the contents of the interrupt mask register. In all cases exceptmasterIntEnable (bit 31) and vendorSpec...

8−22 8.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmitcontexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* commandcompletes and its int...

8−23 8.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channelbasis. Reads from either the set register or the clear register always return the contents of the isochronous transmitinterrupt mask ...

8−24 8.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receivecontexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completesand its interrupt bi...

8−25 8.26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channelbasis. Reads from either the set register or the clear register always return the contents of the isochronous receiveinterrupt mask reg...

8−26 8.28 Initial Channels Available High Register The initial channels available high register value is loaded into the corresponding bus management CSR register ona system (hardware) or software reset. See Table 8−20 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 ...

8−27 8.30 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmitmultiple asynchronous requests during a fairness interval. See Table 8−22 for a complete description of the registercontents. Bit 31 30 29 28 27 26 25 24...

8−28 8.31 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portionsof the PCI7x21/PCI7x11 controller. It contains controls for the receiver and cycle timer. See Table 8−23 for a completedescription of the register c...

8−29 8.32 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynx  chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and theNodeNumber field (bits 5−0) is referred to as t...

8−30 8.33 PHY Layer Control Register The PHY layer control register reads from or writes to a PHY register. See Table 8−25 for a complete description ofthe register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PHY layer control Type RU R R R RU RU RU RU RU RU RU RU RU RU RU RU ...

8−31 8.34 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the PCI7x21/PCI7x11controller is cycle master, this register is transmitted with the cycle start message. When the PCI7x21/PCI7x11controller is not cycle master, this r...

8−32 8.35 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis,and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQcontext, the source node ...

8−34 8.36 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis,and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to theasynchronous request fi...

8−35 8.37 Physical Request Filter High Register The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handlesthe upper node IDs. When a packet is destined for the physical request context, and the node ID has been comparedagainst the ARRQ regi...

8−37 8.38 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handlesthe lower node IDs. When a packet is destined for the physical request context, and the node ID has been comparedagainst the asynchronou...

8−38 8.40 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. SeeTable 8−31 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Asynchronous con...

8−39 8.41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor blockthat the PCI7x21/PCI7x11 controller accesses when software enables the context by setting bit 15 (run) in theasynchronous context c...

8−40 8.42 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronoustransmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, … , 7). See ...

8−41 8.43 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptorblock that the PCI7x21/PCI7x11 controller accesses when software enables an isochronous transmit context bysetting bit 15...

8−43 8.45 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptorblock that the PCI7x21/PCI7x11 controller accesses when software enables an isochronous receive context bysetting bit 15 (r...

8−44 8.46 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cyclenumber, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value.The n value in the...

9−1 9 TI Extension Registers The TI extension base address register provides a method of accessing memory-mapped TI extension registers. SeeSection 7.9, TI Extension Base Address Register, for register bit field details. See Table 9−1 for the TI extensionregister listing. Table 9−1. TI Extension Reg...

9−2 9.2 Isochronous Receive Digital Video Enhancements The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV datathat is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors(see 1394 Open Host Cont...

9−4 9.4 Link Enhancement Register This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCIoffset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM,if one is present, as noted in the ...

9−5 Table 9−3. Link Enhancement Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 9 RSVD R Reserved. Bit 9 returns 0 when read. 8 ‡ enab_dv_ts RW Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DVCIP transmit streams (FMT = 00h). The default...

10−1 10 PHY Register Configuration There are 16 accessible internal registers in the PCI7x21/PCI7x11 controller. The configuration of the registers ataddresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8hthrough Fh (the paged registers) is d...

10−2 Table 10−2. Base Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Physical ID 6 R This field contains the physical address ID of this node determined during self-ID. The physical ID is invalidafter a bus reset until self-ID has completed as indicated by an unsolicited register-0 status t...

10−4 10.2 Port Status Register The port status page provides access to configuration and status information for each of the ports. The port is selectedby writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 10−3shows the configuration of t...

10−5 Table 10−4. Page 0 (Port Status) Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION Int_enable 1 RW Port event interrupt enable. When the Int_enable bit is set to 1, a port event on the selected port sets the portevent interrupt (Port_event) bit and notifies the link. This bit ...

10−7 10.5 Power-Class Programming The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field(bits 21–23) of the transmitted self-ID packet. Table 10−9 shows the descriptions of the various power classes. Thedefault power-class value is loaded followin...

11−1 11 Flash Media Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 flash mediacontroller interface. All registers are detailed in the same format: a brief description for each register is followed bythe register offset...

11−2 11.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.The vendor ID assigned to Texas Instruments is 104Ch. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default ...

11−3 11.3 Command Register The command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhereto the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 11−2 for acomplete description of the register conte...

11−5 11.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of thefunction. The base class is 01h, identifying the controller as a mass storage controller. The subclass is 80h, identifyingthe function as other ...

11−6 11.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the flash media controller PCI header type and nobuilt-in self-test. See Table 11−6 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Header type...

11−7 11.9 Subsystem Vendor Identification Register The subsystem identification register, used for system and option card identification purposes, may be required forcertain operating systems. This read-only register is initialized through the EEPROM and can be written through thesubsystem access re...

11−8 11.12 Interrupt Line Register The interrupt line register is programmed by the system and indicates to the software which interrupt line the flashmedia interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has notyet been assigned to the func...

11−9 11.14 Minimum Grant Register The minimum grant register contains the minimum grant value for the flash media controller core. Bit 7 6 5 4 3 2 1 0 Name Minimum grant Type RU RU RU RU RU RU RU RU Default 0 0 0 0 0 1 1 1 Register: Minimum grant Offset: 3Eh Type: Read/Update Default: 07h Table 11−9...

11−10 11.16 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to thenext capability item. See Table 11−11 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 ...

11−11 11.17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the flash media controller related to PCIpower management. See Table 11−12 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name P...

11−12 11.18 Power Management Control and Status Register The power management control and status register implements the control and status of the flash media controller.This register is not affected by the internally generated reset caused by the transition from the D3 hot to D0 state. See Table 11...

11−13 11.20 Power Management Data Register The power management bridge support extension register provides extended power-management features notapplicable to the flash media controller; thus, it is read-only and returns 0 when read. Bit 7 6 5 4 3 2 1 0 Name Power management data Type R R R R R R R ...

11−14 11.22 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registersat PCI offsets 2Ch and 2Eh, respectively. See Table 11−15 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 ...

12−1 12 SD Host Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 SD hostcontroller interface. All registers are detailed in the same format: a brief description for each register is followed bythe register offset and a b...

12−2 12.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.The vendor ID assigned to Texas Instruments is 104Ch. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default ...

12−3 12.3 Command Register The command register provides control over the SD host controller interface to the PCI bus. All bit functions adhereto the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 12−2 for acomplete description of the register co...

12−5 12.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of thefunction. The base class is 08h, identifying the controller as a generic system peripheral. The subclass is 05h,identifying the function as an S...

12−6 12.6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line sizeand the latency timer associated with the SD host controller. See Table 12−5 for a complete description of the registercontents...

12−7 12.8 SD Host Base Address Register The SD host base address register specifies the base address of the memory-mapped interface registers for eachstandard SD host socket. The size of each base address register (BAR) is 256 bytes. The number of BARs isdependent on the number of SD sockets in the ...

12−8 12.10 Subsystem Identification Register The subsystem identification register, used for system and option card identification purposes, may be required forcertain operating systems. This read-only register is initialized through the EEPROM and can be written through thesubsystem access register...

12−9 12.13 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 12−8,indicating that the SD host controller uses an interrupt. If one of the USE_INTx terminals is asserted, the interruptselect bits are ignored, and this regist...

12−10 12.15 Maximum Latency Register The maximum latency register contains the maximum latency value for the SD host controller core. Bit 7 6 5 4 3 2 1 0 Name Maximum latency Type RU RU RU RU RU RU RU RU Default 0 0 0 0 0 1 0 0 Register: Maximum latency Offset: 3Fh Type: Read/Update Default: 04h Tab...

12−11 12.17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to thenext capability item. See Table 12−12 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 ...

12−12 12.18 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the SD host controller related to PCI powermanagement. See Table 12−13 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power...

12−13 12.19 Power Management Control and Status Register The power management control and status register implements the control and status of the SD host controller. Thisregister is not affected by the internally generated reset caused by the transition from the D3 hot to D0 state. See Table 12−14 ...

12−14 12.21 Power Management Data Register The power management bridge support extension register provides extended power-management features notapplicable to the SD host controller; thus, it is read-only and returns 0 when read. Bit 7 6 5 4 3 2 1 0 Name Power management data Type R R R R R R R R De...

12−15 12.23 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registersat PCI offsets 2Ch and 2Eh, respectively. See Table 12−16 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 ...

13−1 13 Smart Card Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 Smart Cardcontroller interface. All registers are detailed in the same format: a brief description for each register is followed bythe register offset a...

13−2 13.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.The vendor ID assigned to Texas Instruments is 104Ch. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default ...

13−3 13.3 Command Register The command register provides control over the Smart Card controller interface to the PCI bus. All bit functionsadhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. The SERR_ENand PERR_EN enable bits in this register are ...

13−5 13.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of thefunction. The base class is 07h, identifying the controller as a communication device. The subclass is 80h, identifyingthe function as other mas...

13−6 13.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the Smart Card controller PCI header type and nobuilt-in self-test. See Table 13−6 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Header type ...

13−7 13.9 Smart Card Base Address Register 1−4 Each socket has its own base address register. For example, a device supports three Smart Card sockets uses threebase address registers, BA1 (socket 0), BA2 (socket 1) and BA3 (socket 2). These registers are used by this function to determine where to f...

13−8 13.11 Subsystem Identification Register This register is read-update and can be modified through the subsystem ID alias register. This register has no effectto the functionality. Default value is 8035h. This default value complies with the WLP (Windows Logo Program)requirements without BIOS or ...

13−9 13.14 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 13−7,indicating that the Smart Card interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interruptselect bits are ignored, and this regi...

13−10 13.16 Maximum Latency Register The maximum latency register contains the maximum latency value for the Smart Card controller core. Bit 7 6 5 4 3 2 1 0 Name Maximum latency Type RU RU RU RU RU RU RU RU Default 0 0 0 0 0 0 0 0 Register: Maximum latency Offset: 3Fh Type: Read/Update Default: 00h ...

13−11 13.18 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the Smart Card controller related to PCIpower management. See Table 13−11 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Po...

13−12 13.19 Power Management Control and Status Register The power management control and status register implements the control and status of the Smart Card controller.This register is not affected by the internally generated reset caused by the transition from the D3 hot to D0 state. See Table 13−...

13−13 13.21 Power Management Data Register The power management bridge support extension register provides extended power-management features notapplicable to the Smart Card controller; thus, it is read-only and returns 0 when read. Bit 7 6 5 4 3 2 1 0 Name Power management data Type R R R R R R R R...

13−14 13.23 Subsystem ID Alias Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registersat PCI offsets 2Ch and 2Eh, respectively. See Table 13−14 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 2...

13−15 13.25 Smart Card Configuration 1 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register. Informationof this register can be read from the Smart Card configuration 1 alias register in the Smart Card global control registerset. The software util...

13−16 Table 13−15. Smart Card Configuration 1 Register Description BIT FIELD NAME TYPE DESCRIPTION 31−28 SCRTCH_PAD RW Scratch pad 27 CLASS_B_SKT3 R Socket 3 Class B Smart Card support. Since socket 3 is not implemented in the controller, thisbit is a read-only 0. 26 CLASS_B_SKT2 RW Socket 2 Class B...

13−17 13.26 Smart Card Configuration 2 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register. Informationof this register can be read from the Smart Card configuration 2 alias in the Smart Card global control register set.The software utilizes this...

14−1 14 Electrical Characteristics 14.1 Absolute Maximum Ratings Over Operating Temperature Ranges † Supply voltage range, VR_PORT −0.2 V to 2.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD −0.3 V to 4 V . . . . . . . . . . . . . . . . ...

14−2 Recommended Operating Conditions (continued) OPERATION MIN NOM MAX UNIT PCI k 3.3 V 0.5 VCCP VCCP PCI k 5 V 2 VCCP 3.3 V CardBus 0.475 VCC(A/B) VCC(A/B) VIH† High-level input PC Card 3.3 V 16-bit 2 VCC(A/B) V VIH† High-level inputvoltage PC Card 5 V 16-bit 2.4 VCC(A/B) V voltage PC(0−2) 0.7 VCC...

14−5 14.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions (unless otherwise noted) 14.4.1 Device PARAMETER TEST CONDITION MIN MAX UNIT VTH Power status threshold, CPS input† 400-k Ω resistor† 4.7 7.5 V VO TPBIAS output voltage At rated IO current 1.665 2.015 V II Input cur...

15−1 15 Mechanical Information The PCI7x21/PCI7x11 device is available in the 288-terminal MicroStar BGA  package (GHK) or the 288-terminal lead (Pb atomic number 82) free MicroStar BGA  package (ZHK). The following figure shows the mechanical dimensions for the GHK package. The GHK and ZHK packag...

PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) PCI7411GHK ACTIVE BGA GHK 288 1 TBD Call TI Level-3-220C-168 HR PCI7411ZHK ACTIVE BGA MI CROSTA R ZHK 288 1 Green (RoHS & no Sb/Br) Call TI Level-3-260C...