Texas Instruments MSP50C6xx - Manuals

Information About Cautions and Warnings v Read This First .byte value 1 [, ... , value n ] This syntax shows that .byte must have at least one value parameter, butyou have the option of supplying additional value parameters, separatedby commas. Information About Cautions and Warnings This book may c...

Contents vii Contents 1 Introduction to the MSP50C6xx 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features of the MSP50C6xx 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Appl...

Contents viii 3 Peripheral Functions 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 I/O 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Contents ix Contents 4.4 Instruction Classification 4-22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Class 2 Instructions: Accumulator and Constant Reference 4-28 . . . . . . . . . . . . . . 4.4.3 Class 3 Instruction: Accumulator Refe...

Contents x 5.6 Implementation Details 5-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Comparisons 5-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Division 5-26 ...

Figures xi Contents Figures 1–1 Functional Block Diagram for the MSP50C614/MSP50P614 1-5 . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Oscillator and PLL Connection 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 RESET Circuit 1-8 . ....

Tables xii Tables 2–1 Signed and Unsigned Integer Representation 2-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Summary of MSP50C614’s Peripheral Communications Ports 2-17 . . . . . . . . . . . . . . . . . . . . . 2–3 Programmable Bits Needed to Control Reduced Pow...

1-1 Introduction to the MSP50C6xx The MSP50C6xx is a low cost, mixed signal controller, that combines a speechsynthesizer, general-purpose input/output (I/O), onboard ROM, and directspeaker-drive in a single package. The computational unit utilizes a powerfulnew DSP which gives the MSP50C6xx unprece...

Applications 1-3 Introduction to the MSP50C6xx 1.2 Applications Due to its low cost, low-power consumption, and high programmability, theMSP50C6xx is suitable for a wide variety of applications incorporating flexibleI/O and high-quality speech: - Consumer - Education Toys and Games Electronic Learni...

Functional Description for the MSP50C614 1-5 Introduction to the MSP50C6xx 1.4 Functional Description for the MSP50C614 The MSP50C614 device consists of a micro-DSP core, embedded programand data memory, and a self-contained clock generation system. General-pur-pose periphery is comprised of 64 bits...

Functional Description for the MSP50C614 1-7 Introduction to the MSP50C6xx Figure 1–2. Oscillator and PLL Connection MSP50P614 MSP50C6xx OSCIN OSCOUT PLL C(PLL) = 3300 pF† 22 pF† 22 pF† 10 M Ω † 10 M Ω † 32.768 kHz† † Keep these components as close as possible to the OSCIN, OSCOUT, and PLL pins. a) ...

Functional Description for the MSP50C614 1-8 Rounding out the MSP50C6xx periphery is a built in pulse-density-modulated(PDM) digital-to-analog converter (DAC) with direct speaker-drive capability. Typical connections to implement reset functionality are shown in Figure 1–3. An external reset circuit...

2-1 MSP50C6xx Architecture A detailed description of the MSP50C6xx architecture is included in this chap-ter. After reading this chapter, the reader will have in-depth knowledge of inter-nal blocks, memory organization, interrupt system, timers, clock control mech-anism, and various low power modes....

2-2 2.1 Architecture Overview The core processor in the C6xx is a medium performance mixed signal proces-sor with enhanced microcontroller features and a limited DSP instruction set.In addition to its basic multiply/accumulate structure for DSP routines, the coreprovides for a very efficient handlin...

2-3 MSP50C6xx Architecture Figure 2–1. MSP50C6xx Core Processor Block Diagram Multiplier (MR)† Shift Value (SV)† 17 x 17 Multiplier Product High (PH)† 16 bit ALU MUX 32 Accumulators (AC0–AC31)† Column Exchange Loop (R4) Index (R5) Page (R6) Stack (R7) R0 R1 R2 R3 Arithmetic Unit MUX MUX Data Memory ...

2-4 Figure 2–2. Computational Unit Block Diagram Accumulators 5 16 AC3 AC2 AC1 AC0 Read/Write AC7 AC6 AC5 AC4 AC11 AC10 AC9 AC8 AC15 AC14 AC13 AC12 AC19 AC18 AC17 AC16 AC23 AC22 AC21 AC20 AC27 AC26 AC25 AC24 AC31 AC30 AC29 AC28 AP3 AP2 AP1 AP0 5 Internal Databus – 16 bit Shift Value (SV) Multiplier ...

Computation Unit 2-5 MSP50C6xx Architecture 2.2 Computation Unit The computational unit (CU) is comprised of a (17-bit by 17-bit) Booth’salgorithm multiplier and a 16-bit arithmetic logic unit (ALU). The block diagramof the CU is shown in Figure 2–2. The multiplier block is served by 4 systemregiste...

Computation Unit 2-7 MSP50C6xx Architecture Figure 2–3. Overview of the Multiplier Unit Operation MULTIPLIER UNIT INPUTS Multiplicand 16-bit - latched in a write-only registerfrom one of the following sources ... Data MemoryAccumulator Offset Accumulator X Multiplier - writeable and readable by Data...

Computation Unit 2-8 The all-zero values are necessary for data transfers and unitary operations.All-zeros also serve as default values for the registers, which helps to minimizeresidual power consumption. The databus path through ALU-A is used to inputmemory values (RAM) and constant values (progra...

Computation Unit 2-9 MSP50C6xx Architecture Figure 2–4. Overview of the Arithmetic Logic Unit ALU INPUTS ALU-A 16-bit - selects between ... all 0’sOffset Accumulator Register Data Memory ALU-B 16-bit - selects between ... (PH) (PL) ARITHMETIC LOGIC UNIT performs arithmetic, comparison, and logic ALU...

Computation Unit 2-10 When writing an accumulator-referenced instruction, therefore, the workingaccumulator address is stored in one of AP0 to AP3. The C6xx instruction setprovides a two-bit field for all accumulator referenced instructions. The two-bitfield serves as a reference to the accumulator ...

Data Memory Address Unit 2-11 MSP50C6xx Architecture For some instructions, the 5-bit string processor can also preincrement orpredecrement the AP pointer-value by +1 or –1, before being used by theaccumulator register block. This utility can be effectively used to minimizesoftware overhead in manip...

Data Memory Address Unit 2-12 Figure 2–6. Data Memory Address Unit R3 R2 R1 R0 R7 R6 R5 R4 InternalDatabus Arithmetic Block RAM Address Internal Program Bus Register Addressing Mode STACK PAGE INDEX LOOP 2.3.1 RAM Configuration The data memory block (RAM) is physically organized into 17-bit parallel...

Data Memory Address Unit 2-13 MSP50C6xx Architecture There are two-byte instructions, for example MOVB, which cause the proces-sor to read or write data in a byte (8-bit) format. (The B appearing at the endof MOVB designates it as an instruction that uses byte-addressable argu-ments.) The byte-addre...

Program Counter Unit 2-14 2.4 Program Counter Unit The program counter unit provides addressing for program memory (onboardROM). It includes a 16-bit arithmetic block for incrementing and loadingaddresses. It also consists of the program counter (PC), the data pointer (DP),a buffer register, a code ...

Memory Organization: RAM and ROM 2-15 MSP50C6xx Architecture 2.6 Memory Organization: RAM and ROM Data memory (RAM) and program memory (ROM) are each restricted tointernal blocks on the C6xx. The program memory is read-only and limited to32K, 17-bit words. The lower 2048 of these words is reserved f...

Memory Organization: RAM and ROM 2-17 MSP50C6xx Architecture When writing to any of the locations in the I/O address map, therefore, thebit-masking need only extend as far as width of location. Within a 16-bitaccumulator, the desired bits (width of location) should be right-justified. Thewrite opera...

Memory Organization: RAM and ROM 2-18 Table 2–2. Summary of C614’s Peripheral Communications Ports (Continued) I/O Map Address Width of Location Allowable Access Control Register Name Abbreviation State after RESET LOW Section for Reference 0x39 8 bits Read & Write Interrupt flag IFR Same state ...

Memory Organization: RAM and ROM 2-19 MSP50C6xx Architecture The branch to the program location that is specified in the interrupt vector is,of course, contingent on the occurrence of the trigger event. Refer to Section3.1.5, Internal and External Interrupts, for more information regarding thespecif...

Memory Organization: RAM and ROM 2-20 Note: Instructions with References Care must be taken when employing instructions that have either long stringconstant references or look-up table references. These instructions willexecute properly only if the address of the instruction and the address of theda...

Memory Organization: RAM and ROM 2-21 MSP50C6xx Architecture [(N TM + 1) * 512 – 1] = highest ROM address within the block to be protected (N TM + 1) * 512 = lowest ROM address which is left unprotected N TM = the value programmed at TM5 … TM0 (true protection marker) N FM ≡ the binary complement of...

Interrupt Logic 2-22 When the device is powered up, the hardware initialization circuit reads thevalue stored in the block protection word. The value is then loaded to an inter-nal register and the security state of the ROM is identified. Until this occurs,execution of any instructions is suspended....

Interrupt Logic 2-23 MSP50C6xx Architecture automatically SET in the interrupt flag register (IFR). The IFR is an 8-bit wideport-addressed register; wherein, each interrupt level is represented. A set bitin the IFR indicates that the interrupt is pending and waiting to be serviced. Aclear bit indica...

Interrupt Logic 2-24 Note: Setting a Bit in the IFR Using the OUT Instruction Setting a bit within the IFR using the OUT instruction is a valid way of obtain-ing a software interrupt. An IFR bit may also be cleared, using OUT, at anytime. Assuming the global interrupt enable is set and the specific ...

Interrupt Logic 2-25 MSP50C6xx Architecture Figure 2–8 provides an overview of the interrupt control sequence. INT0 is thehighest priority interrupt, and INT7 is the lowest priority interrupt. Figure 2–8. Interrupt Initialization Sequence INTD instruction CLEAR INTE instruction SET Global Interrupt ...

Clock Control 2-26 In addition to being individually enabled, all interrupts must be GLOBALLYenabled before any one can be serviced. Whenever interrupts are globallydisabled, the interrupt flag register may still receive updates on pending triggerevents. Those trigger events, however, are not servic...

Clock Control 2-27 MSP50C6xx Architecture therefore, is 131.07 kHz, and the multiplier operates in increments of this basefrequency. The minimum multiplication of the base frequency is 1, and themaximum multiplication is 256. The resulting master clock frequency, there-fore, can be varied from a min...

Clock Control 2-28 2.8.3 Clock Speed Control Register The ClkSpdCtrl is a 16-bit memory mapped register located at address 0x3D.The reference oscillator (RTO or CRO) is selected by setting one of the twocontrol bits located at bits 8 and 9. Setting bit 8 configures the C6xx for the RTOreference opti...

Clock Control 2-29 MSP50C6xx Architecture The configuration of bits in the clock speed control register appears below: ClkSpdCtrl register address 0x3D (16-bit wide location) WRITE only 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 T5 T4 T3 T2 T1 I C or T0 R M M M M M M M M T : RTO oscillator-Trim...

Clock Control 2-30 RTRIM Register (Read Only) (Applies to MSP50C6xx Device Only) I/O Address 0x2Fh (17-bit wide location) 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 R R R R R R R R R R R T5 T4 T3 T2 T1 T0 T: RTO oscillator-trim storage (device specific) R: reserved for Texas Instruments use ...

Timer Registers 2-31 MSP50C6xx Architecture This software-controlled trim for the RTO is not a replacement for the externalreference-resistor mounted at pins OSC IN and OSC OUT . Also, note that this adjustment has no effect on the rate of the CRO reference oscillator. 2.9 Timer Registers The C6xx c...

Timer Registers 2-32 Reading from either the PRD or the TIM returns the current state of the register.This can be used to monitor the progress of the TIM register at any time. Writing to the PRD register does not change the TIM register until the TIMregister has finished decrementing to 0x0000. The ...

Reduced Power Modes 2-33 MSP50C6xx Architecture enable bit for TIMER2. Setting the enable bit enables the TIMER, i.e., startscount-down running. Clearing the enable bit disables the TIMER, i.e., stopsthe count-down. The default setting after a RESET LOW is zero: both TIMERsdisabled. Refer to Section...

Reduced Power Modes 2-35 MSP50C6xx Architecture If either of bits 8 or 9 are set, then the reference oscillator enable is consideredset. This enables the PLL circuitry to regulate to the reference frequency, 32kHz (assuming the idle state clock control is clear). Whichever state thereference oscilla...

Reduced Power Modes 2-36 Note: Idle State Clock Control Bit If the idle state clock control bit is set and the ARM bit is clear, the only eventthat can wake the C6xx after an IDLE instruction is a hardware RESET low-to-high. When at sleep, the device will not respond to the input ports, nor tothe in...

Reduced Power Modes 2-39 MSP50C6xx Architecture Under normal operation the DAC timer, when IMR enabled, triggers aninterrupt on underflow. Before any IDLE instruction, however, the entire DACcircuitry should be disabled. This ensures the effectiveness of the reducedpower mode and prevents any wake-u...

Execution Timing 2-40 2.11 Execution Timing For executing program code, the C6xx’s core processor has a three-levelpipeline. The pipeline consists of instruction fetch, instruction decode, andinstruction execution. A single instruction cycle is limited to one program Fetchplus one data memory read o...

3-1 Peripheral Functions This chapter describes in detail the MSP50C6xx peripheral functions, i.e., I/Ocontrol ports, general purpose I/O ports, interrupt control registers, compara-tor and digital-to-analog (DAC) control mechanisms. Topic Page 3.1 I/O . . . 3–2 . . . . . . . . . . . . . . . . . . ....

I/O 3-3 Peripheral Functions Port A Port B Port C Port D Port E Control register address 0x04h † 0x0Ch 0x14h 0x1Ch 0x24h Possible control values 0 = High-Z INPUT 1 = TOTEM-POLE OUTPUT Value after RESET low 0 = High-Z INPUT Data register address 0x00h 0x08h 0x10h 0x18h 0x20h Possible input data value...

I/O 3-4 The following table shows the bit locations of the I/O port mapping: (8-bit wide location)07 06 05 04 03 02 01 00 A port data register address 0x00 . . . . . A7 A6 A5 A4 A3 A2 A1 A0 A port control register address 0x04 . . . C C C C C C C C B port data register address 0x08 . . . . . B7 B6 B...

I/O 3-5 Peripheral Functions and setting the EP bit enables the eight pullups. After RESET low, the defaultsetting for the EP bit is 0 (F-port pullups disabled). Input Port F Data register address 0x28h Possible input data values Low = 0 High = 1 Possible output data values N/A Value after RESET low...

I/O 3-6 Totem-Pole Output Port G Data register address 0x2Ch Possible input data values N/A Possible output data values 0 = Low 1 = High Value after RESET low 0 = Low The following table shows the bit locations of the port G address mapping: G port Data address 0x2Cread and write (16-bit wide locati...

I/O 3-7 Peripheral Functions 3.1.5 Internal and External Interrupts INT3, INT4, INT6, and INT7 are external interrupts which may be triggered byevents on the PD 2 , PD 3 , PD 4 , and PD 5 pins. These interrupts are supported whether the D-port pins are programmed as inputs or outputs. (Whenprogramme...

I/O 3-8 A summary of the interrupts is given in Table 3–1. Table 3–1. Interrupts Interrupt Vector Source Trigger Event Priority Comment INT0 0x7FF0 DAC Timer Timer underflow Highest Used to synch. speech data INT1 0x7FF1 TIMER1 Timer underflow 2 nd INT2 0x7FF2 TIMER2 Timer underflow 3 rd INT3 0x7FF3...

Digital-to-Analog Converter (DAC) 3-9 Peripheral Functions 3.2 Digital-to-Analog Converter (DAC) The MSP50C6xx incorporates a two-pin pulse-density-modulated DAC whichis capable of driving a 32- Ω loudspeaker directly. To drive loud speakers other than 32 Ω , an external impedance-matching circuit i...

Digital-to-Analog Converter (DAC) 3-10 DAC Control registerAddress 0x34 (4-bit wide location)03 02 01 00 Set DAC resolution to 8 bits:Set DAC resolution to 9 bits:Set DAC resolution to 10 bits: DM E 0 0DM E 0 1DM E 1 0 DM : Drive Mode selection (0 = C3x style : 1 = C5x style) E : pulse-density-modul...

Digital-to-Analog Converter (DAC) 3-11 Peripheral Functions style. Their selection is made at bit 3 of the DAC control register (0x34). TheC3x style is selected by clearing bit 3, and the C5x style is selected by settingbit 3. The default value of the selection is zero which yields the C3x style. Th...

Digital-to-Analog Converter (DAC) 3-12 For a given sampling rate and DAC resolution, the CPU clock rate may beincreased, if necessary, through the use of over-sampling. In the previousexample, an original sampling rate of 8 kHz and a PDM rate of 4 MHz wasused. A 2-times over-sampling, therefore, wou...

Comparator 3-16 The INT6 Flag may also be SET or CLEARed deliberately, at any time, insoftware. Use the OUT instruction with the associated I/O port address (IFR,address 0x39). INT7 flag refers to bit 7 within the interrupt flag register. This bit is automaticallySET anytime that an INT7 event occur...

Interrupt/General Control Register 3-18 3.4 Interrupt/General Control Register The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped registerlocated at address 0x38. The primary component in the IntGenCtrl is the 8-bitinterrupt mask register (IMR). The IMR is used to individually e...

Hardware Initialization States 3-20 3.5 Hardware Initialization States The RESET pin is configured at all times as an external interrupt. It providesfor a hardware initialization of the MSP50C6xx. When the RESET pin is heldlow, the device assumes a deep sleep state and various control registers arei...

Hardware Initialization States 3-21 Peripheral Functions Note: Internal RAM State after Reset The RESET low will not change the state of the internal RAM, assuming thereis no interruption in power. This applies also to the interrupt flag register. Thesame applies to the states of the accumulators in...

Hardware Initialization States 3-22 Table 3–2. State of the Status Register (17 bit) after RESET Low-to-High (Bits 5 through 16 are left uninitialized) Bit Bit Name Initialized Value Description 0 XM 0 Extended sign mode disabled 1 UM 0 Unsigned multiplier mode disabled (allows signed multiplier mod...

4-1 Assembly Language Instructions This chapter describes in detail about MSP50P614/MSP50C614 assemblylanguage. Instruction classes, addressing modes, instruction encoding andexplanation of each instruction is described. Topic Page 4.1 Introduction 4–2 . . . . . . . . . . . . . . . . . . . . . . . ....

Introduction 4-2 4.1 Introduction In this chapter each MSP50P614/MSP50C614 class of instructions isexplained in detail with examples and restrictions. Most instructions canindividually address bits, bytes, words or strings of words or bytes. Usableprogram memory is 30K by 17-bit wide and the entire ...

System Registers 4-6 value of the STACK register should be stored before use and restored afteruse. This register must point to the beginning of the stack in the RESETinitialization routine before any CALL instruction or maskable interrupts can beused. CALL instructions increment R7 by 2., RET instr...

Instruction Syntax and Addressing Modes 4-8 4.3 Instruction Syntax and Addressing Modes MSP50P614/MSP50C614 instructions can perform multiple operations perinstruction. Many instructions may have multiple source arguments. They canpremodify register values and can have only one destination. The addr...

Instruction Syntax and Addressing Modes 4-9 Assembly Language Instructions 4.3.2 Addressing Modes The addressing modes on the MSP50P614/MSP50C614 are immediate, di-rect, indirect with post modification, and three relative modes. The relativemodes are: - Relative to the INDEX or R5 register. The effe...

Instruction Syntax and Addressing Modes 4-10 Table 4–3. Rx Bit Description Rx Operation 0 0 0 R0 0 0 1 R1 0 1 0 R2 0 1 1 R3 1 0 0 R4 or LOOP 1 0 1 R5 or INDEX 1 1 0 R6 or PAGE 1 1 1 R7 or STACK Table 4–4. Addressing Mode Bits and {adrs} Field Description Relative Repeat addressing mode encoding, adr...

Instruction Syntax and Addressing Modes 4-11 Assembly Language Instructions Table 4–5. MSP50P614/MSP50C614 Addressing Modes Summary ADDRESSING SYNTAX OPERATION Direct name [dest,] [src,] *dma16 [*2] [, next A]name *dma16 [*2] [,src] [, next A] Second word operand (dma16) used directly as memoryaddre...

Instruction Syntax and Addressing Modes 4-12 For any particular addressing mode, replace the {adrs} with the syntax shownin Table 4–4. To encode the instruction, replace the am, Rx and pm bits withthe bits required by the addressing mode (Table 4–4). For example, theinstruction MOV An[~], {adrs} [, ...

Instruction Syntax and Addressing Modes 4-13 Assembly Language Instructions 4.3.3 Immediate Addressing The address of the memory location is encoded in the instruction word or theword following the opcode is the immediate value. Single word instructionstake one clock cycle and double word instructio...

Instruction Syntax and Addressing Modes 4-14 4.3.4 Direct Addressing Direct addressing always requires two instruction words. The second wordoperand is used directly as the memory address. The memory operand maybe a label or an expression. Syntax: name [dest,] [src,] *dma16 [* 2] [, next A]name *dma...

Instruction Syntax and Addressing Modes 4-15 Assembly Language Instructions 4.3.5 Indirect Addressing Indirect addressing uses one of 8 registers (R0...R7) to point memoryaddresses. The selected register can be post-modified. Modifications includeincrements, decrements, or increments by the value in...

Instruction Syntax and Addressing Modes 4-16 Example 4.3.12 MOV *R5++R5, A0~, ++A Refer to the initial processor state in Table 4–8 before execution of thisinstruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ isAC19. The contents of AC19 are stored in the data memory location in R5. ...

Instruction Syntax and Addressing Modes 4-17 Assembly Language Instructions Address + Rx (x = 0 – 7) Index Register (R5) Operand Example 4.3.17 AND A0, *R3+R5 Refer to the initial processor state in Table 4–8 before execution of this instruc-tion. A0 is accumulator AC2. The contents of the data memo...

Instruction Syntax and Addressing Modes 4-18 Example 4.3.20 MOV A3, *R6+0x10 Refer to the initial processor state in Table 4–8 before execution of this instruc-tion. Load A3 (AC29) with the contents of byte address, R6+0x10. The valueof R6 is unchanged. Final result, AC29=0x0112. Example 4.3.21 ADD ...

Instruction Syntax and Addressing Modes 4-19 Assembly Language Instructions 4.3.7 Flag Addressing This addressing mode addresses only the 17 th bit (the flag/tag bit) located in data memory. This addressing applies to Class 8a instructions as explainedin section 4.4. Using flag addressing, the flag ...

Instruction Syntax and Addressing Modes 4-20 4.3.8 Tag/Flag Bits The words TAG and flag may be used interchangeably in this manual. TheTAG bit is the 17 th bit of a word of data memory. There are 640 words of RAM, each 17 bits wide, on the C614. Therefore, there are 640 TAG bits on the C614.When an ...

Instruction Syntax and Addressing Modes 4-21 Assembly Language Instructions However, xFLAG instructions use {flagadrs} addressing modes. This includesglobal (dma6) and relative (R6 + 6–bit offset). Both take only one clock cycle. Possible sources of confusion: Consider the following code, ram0 equ 0...

Instruction Classification 4-22 4.4 Instruction Classification The machine level instruction set is divided into a number of classes. Theclasses are primarily divided according to field references associated withmemory, hardware registers, and control fields. The following descriptionsgive class-enc...

Instruction Classification 4-23 Assembly Language Instructions Table 4–11. Symbols and Explanation (Continued) Symbol Explanation next A Accumulator control bits as described in Table 4–6. [next A] The preincrement (++A) or predecrement (– –A) operation on accumulator pointers An or An~. Not NOT con...

Instruction Classification 4-25 Assembly Language Instructions Table 4–12. Classes and Opcode Definition Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class 1a 0 0 C1a ~A~ next A An am Rx pm Class 1b 0 1 C1b s An am Rx pm Class 2a 1 0 1 0 C2a An imm8 Class 2b 1 1 1 0 0 next A An C2b 0 0 1 A~ ~A Class...

Instruction Classification 4-26 Class 1a provides the four basic instructions of load, store, add, and subtractbetween accumulator and data memory. Either the accumulator or the offsetaccumulator (A~ bit dependent) can be stored in memory with the MOVinstruction. The MOV instruction can load the acc...

Instruction Classification 4-27 Assembly Language Instructions Table 4–15. Class 1b Instruction Description C1b Mnemonic Description 0 0 0 0 OR An, {adrs}ORS An, {adrs} Logical OR the contents of the data memory location in {adrs}and the selected accumulator. Result(s) stored inaccumulator(s). ALU s...

Instruction Classification 4-28 Table 4–15. Class 1b Instruction Description (Continued) C1b Mnemonic Description 1 0 1 1 MULAPL An, {adrs}MULAPLS An, {adrs} Multiply the MR register by the addressing mode {adrs} and addthe lower 16 bits of the product to the accumulator. Latch theupper 16 bits into...

Instruction Classification 4-29 Assembly Language Instructions constants. Long constants (16 bits) and long string constants differ in that ref-erences are made to constants in the second word of the two-word instructionword. References made to a single 16-bit integer constant are immediate. Thatis,...

Instruction Classification 4-30 Table 4–18. Class 2b Instruction Description C2b Mnemonic Description 0 0 0 ADD An[~], An[~], imm16 [, next A]ADDS An[~], An[~], pma16 Add long constant to accumulator (or offset accumulator ifA~=1) and store result to accumulator (~A=0) or offsetaccumulator (~A=1). A...

Instruction Classification 4-31 Assembly Language Instructions between the accumulator and the MR, SV, or PH register. As with all accumula-tor referenced instructions, string operations are possible as well as premodi-fication of one of 4 indirectly referenced accumulator pointer registers (AP). Ta...

Instruction Classification 4-34 Table 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 1 1 1 1 0 MUL An[~] [, next A]MULS An[~] Multiply MR register by accumulator (A~=1) or offsetaccumulator (A~=0) and latch the rounded upper 16 bits ofthe resulting product into the PH regi...

Instruction Classification 4-35 Assembly Language Instructions Table 4–22. Class 4a Instruction Description C4a Mnemonic Description 0 MOV {adrs}, Rx Store Rx register to data memory referred by addressing mode {adrs}. Modifytransfer status. 1 MOV Rx, {adrs} Load Rx with the value in data memory ref...

Instruction Classification 4-36 4.4.5 Class 5 Instructions: Memory Reference Class 5 instructions provide transfer to and from data memory and all registersexcept accumulators and Rx which are included in classes 1 and 4. Theregisters referenced for both read and write operations are the multiplierr...

Instruction Classification 4-38 Table 4–27. Class 5 Instruction Description (Continued) C5 Mnemonic Description 1 1 1 1 0 RPT {adrs} 8 Load repeat counter with lower 8 bits of data memory location referred byaddressing mode {adrs}. Interrupts are queued during execution. 1 1 1 1 1 MOV STAT, {adrs} L...

Instruction Classification 4-39 Assembly Language Instructions Table 4–30. Class 6b Instruction Description C6b Mnemonic Description 0 IN An[~], port6INS An[~], port6 Transfer the port’s 16-bit value to an accumulator. Port addresses 0–63are valid. ALU status is modified. 1 OUT port6, An[~]OUTS port...

Instruction Classification 4-40 Table 4–31. Class 7 Instruction Encoding and Description Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VCALL vector8 1 1 1 1 1 1 1 0 1 vector8 Jcc 1 0 0 0 0 0 Not cc Rx pm JMP *An 1 0 0 0 1 0 x An x Ccc 1 0 0 0 0 1 Not cc x CALL *An 1 0 0 0 1 1 x An x cc cc names Descr...

Instruction Classification 4-41 Assembly Language Instructions Table 4–31. Class 7 Instruction Encoding and Description (Continued) cc cc names Description cc cc name Not cc name 1 0 1 0 1 Unconditional 1 0 1 1 0 Not assigned 1 0 1 1 1 Not assigned 1 1 0 0 0 XZ XNZ Conditional on XSF 1 1 0 0 1 XS XN...

Instruction Classification 4-42 Table 4–33. Class 8a Instruction Description C8a Mnemonic Description 0 0 0 MOV TFn, {flagadrs} Load flag bit (17 th bit) from data memory referred by flag addressing mode {flagadrs} to either TF1 or TF2 in status register. Load with inverted value ifNot =1. 0 1 0 OR ...

Instruction Classification 4-43 Assembly Language Instructions Table 4–35. Class 9a Instruction Encoding Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class 9a 1 1 1 0 1 0 0 An C9a 0 Rx 1 1 Class 9b 1 1 1 1 1 1 0 C9a imm8 Class 9c 1 1 1 1 1 0 1 APn 0 C9c x imm5 Class 9d 1 1 1 1 1 1 1 1 0 C9d 0 0 0 0 ...

Bit, Byte, Word and String Addressing 4-44 Table 4–38. Class 9c Instruction Description C9c Mnemonic Description 0 MOV APn, imm6 Load the accumulator pointer (AP) with a 5-bit constant. 1 ADD APn, imm5 Add a 5-bit constant imm5 to the referenced accumulator pointer(AP). Table 4–39. Class 9d Instruct...

Bit, Byte, Word and String Addressing 4-45 Assembly Language Instructions is a string of bytes. The length of the byte string is stored in the string register(STR). To define the length of a string, the STR register should hold the lengthof the string minus 2. For example, if the length of a byte st...

Bit, Byte, Word and String Addressing 4-46 Flag Address: The flag (or TAG) address uses linear addressing from 0 to thesize of data memory in 17-bit wide words (0 to 639 for MSP50P614/MSP50C614). Only the 17 th bit is accessible. When a word memory location is read, the corresponding flag for that l...

Bit, Byte, Word and String Addressing 4-47 Assembly Language Instructions Figure 4–4. Data Memory Example Absolute Word Memory Location Data Memory Location (even) = 2 * (Absolute word memory location) MS Byte LS Byte Data Memory Location (odd) 0x0000 0x0000 0x12 0x34 0x0001 0x0001 0x0002 0x56 0x78 ...

MSP50P614/MSP50C614 Computational Modes 4-49 Assembly Language Instructions Example 4.5.10 MOV STR, 0 SFLAG *0x00032 MOVS A0, *0x0031 * 2 RFLAG *0x00032 MOVS A0, *0x0031 * 2 Refer to Figure 4–4 for this example. This example is to illustrate the effect ofthe tag/flag bit when used with a string inst...

MSP50P614/MSP50C614 Computational Modes 4-50 Table 4–41. MSP50P614/MSP50C614 Computational Modes ComputationalMode SettingInstruction Resetting Instruction Function Sign extension SXM RXM STAT.XM = 1 produces sign extension on data as it ispassed into accumulators. This mode copies the 16 th bit of ...

MSP50P614/MSP50C614 Computational Modes 4-51 Assembly Language Instructions Example 4.6.2 SXM MOV STR, 2–2 ; string length=2 MOV MR, 0x8000 MOV A0, 0x8000, ++A ; load MS Byte MOV A0, 0x0000, ––A ; load LS Byte MULTPLS A0, A0 This example illustrates the sign extension mode on a string duringmultipli...

Hardware Loop Instructions 4-53 Assembly Language Instructions high word of the result is stored in the PH register and is 0x3FFF. The low wordis stored in A0~ as 0x0001. If the two numbers are considered as Q15 fraction-al numbers (all bits are to the right of the decimal point), then the result wi...

String Instructions 4-55 Assembly Language Instructions 4.8 String Instructions Class 1, 2, 3, and 6 instructions can have string modes. During the executionof string instruction, STR register value plus 2 is assumed as string length. Anaccumulator string is a group of consecutive accumulators spann...

String Instructions 4-56 A1 string is 0x233EFBCA1223 and *0x200 = 0x9086EE3412AC. STR =3–2=1, defines a string length of 3. Final result, A1~ string =0x233EFBCA1223 + 0x9086EE3412AC = 0xB3C5E9FE24CF, AC5=0x24CF,AC6=0xE9FE, AC7=0xB3C5, STR=2 (unchanged). Notice that this instructionhas accumulated a ...

Lookup Instructions 4-57 Assembly Language Instructions 4.9 Lookup Instructions Table lookup instructions transfer data from program memory (ROM) to datamemory or accumulators. These instructions are useful for reading permanentROM data into the user program for manipulation. For example, lookup tab...

Input/Output Instructions 4-59 Assembly Language Instructions 4.10 Input/Output Instructions The MSP50P614/MSP50C614 processor communicates with other on-chiplogic as well as external hardware through a parallel I/O interface. Up to 40 I/Oports are addressable with instructions that provide bidirect...

Special Filter Instructions 4-61 Assembly Language Instructions theory requires). The second to last RAM location in the circular buffer istagged using an STAG instruction. Below is an example of how to set up circu-lar buffering with FIR or COR. When using the FIR or COR instruction with circular b...

Special Filter Instructions 4-62 After the FIR or COR instruction executes, the new startOfBuff will be the last location in the circular buffer. After another FIR/COR instruction, the new startOfBuff will be the second to last location in the circular buffer, and so on. The second detail is the STA...

Special Filter Instructions 4-64 Any combination of registers different from the above will yield incorrectresults with the FIR/COR instruction. Use R5 to wrap around R0 0x010 0x0100 0x0106 0x0102 x[k] x[k–1] x[k–2] x[k–3] tag After FIR/COR execution The STAT register is saved in the filterSTAT_tag ...

Special Filter Instructions 4-65 Assembly Language Instructions Important Note About Setting the STAT Register It is very important to consider the initial value of the filterSTAT_tag variable.Failure to set up the filterSTAT_tag variable can cause incorrect results in FIR/COR operations. Overflow m...

Special Filter Instructions 4-66 mov STAT,*filterSTAT_tag ;load STAT with last filter tag status rpt N–2 firk A0,*R0++ ;Do one sample ––> 32 bit result mov *filterSTAT_tag,STAT ;save STAT with last filter tag status ;R0 now points to the last sample movs *ySampleOut,A0 ;FIR outputs bits 0–15 in A...

Conditionals 4-69 Assembly Language Instructions 4.12 Conditionals The condition bits in the status register (STAT) are used to modify programcontrol through conditional branches and calls. Various combinations of bitsare available to provide a rich set of conditional operations. These conditionbits...

Legend 4-70 4.13 Legend All instructions of the MSP50P614/MSP50C614 use the following syntax: name [dest] [, src] [, src1] [, mod] name Name of the instruction. Instruction names are shown in bold letter through out the text. dest Destination of the data to be stored after the execution of the instr...

Legend 4-73 Assembly Language Instructions Table 4–45. Auto Increment and Decrement Operation next A b9 b8 No modification 0 0 Auto increment ++A 0 1 Auto Decrement – –A 1 0 Table 4–46. Addressing Mode Bits and adrs Field Description String† Addressing Mode Encoding Relative Addressing Clocks Words ...

Individual Instruction Descriptions 4-74 4.14 Individual Instruction Descriptions In this section, individual instructions are discussed in detail. Use theconditionals in Section 4.12 and the legend in Section 4.13 to help withindividual instruction descriptions. Each instruction is discussed in det...

Individual Instruction Descriptions 4-75 Assembly Language Instructions 4.14.1 ADD Add word Syntax [label] name dest, src [, src1] [,mod] Clock, clk Words, w With RPT, clk Class ADD An[~], An, {adrs} [, next A] Table 4–46 Table 4–46 Table 4–46 1a ADD An[~], An[~], imm16 [, next A] 2 2 N/R 2b ADD An[...

Individual Instruction Descriptions 4-76 Description Syntax Description ADD dest, src ADD src with dest and store the result to dest. ADD dest, src, src1 [,mod] ADD src1 with src and store the result to dest. Premodify the mod beforeexecution. (if provided) See Also ADDB, ADDS, SUB, SUBB, SUBS Examp...

Individual Instruction Descriptions 4-77 Assembly Language Instructions 4.14.2 ADDB ADD BYTE Syntax [label] name dest, src Clock, clk Words, w With RPT, clk Class ADDB An, imm8 1 1 N/R 2a ADDB Rx, imm8 1 1 N/R 4b Execution dest ⇐ dest + src PC ⇐ PC + 1 Flags Affected dest is An: OF, SF, ZF, CF are s...

Individual Instruction Descriptions 4-78 4.14.3 ADDS Add String Syntax [label] name dest, src, src1 Clock, clk Words, w With RPT, clk Class ADDS An[~], An, {adrs} Table 4–46 Table 4–46 Table 4–46 1a ADDS An[~], An[~], pma16 n S +4 2 N/R 2b ADDS An[~], An~, An n S +2 1 n R +2 3 ADDS † An[~], An[~], P...

Individual Instruction Descriptions 4-80 4.14.4 AND Bitwise AND Syntax [label] name dest, src [, src1] [, mod] Clock, clk Word, w With RPT, clk Class AND An, {adrs} Table 4–46 Table 4–46 1b AND An[~], An[~], imm16 [, next A] 2 2 N/R 2b AND An[~], An~, An [, next A] 1 1 n R +3 3 AND TFn, [!]{flagadrs...

Individual Instruction Descriptions 4-81 Assembly Language Instructions See Also ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XORS Example 4.14.4.1 AND A3, *R4— – And word at address in R4 to A3, store result in A3. Decrement value in R4 by 2 (word mode) after theAND operation. Example 4.14.4.2 AND A0~, A0,...

Individual Instruction Descriptions 4-82 4.14.5 ANDB Bitwise AND Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class ANDB An, imm8 1 1 N/R 2a Execution dest ⇐ dest AND src byte PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions 16 15 14 13 12 11 1...

Individual Instruction Descriptions 4-83 Assembly Language Instructions 4.14.6 ANDS Bitwise AND String Syntax [label] name dest, src [, src1] Clock, clk Word, w With RPT, clk Class ANDS An, {adrs} Table 4–46 Table 4–46 1b ANDS An[~], An[~], pma16 n R +4 1 N/R 2b ANDS An[~], An~, An n R +3 1 n R +3 3...

Individual Instruction Descriptions 4-84 4.14.7 BEGLOOP Begin Loop Syntax [label] name Clock, clk Word, w With RPT, clk Class BEGLOOP † 1 1 N/R 9d † Loop must end with ENDLOOP. Execution Save next instruction address (PC + 1)(mask interrupts)PC ⇐ PC + 1 Flags Affected none Opcode Instructions 16 15 ...

Individual Instruction Descriptions 4-85 Assembly Language Instructions 4.14.8 CALL Unconditional Subroutine Call Syntax [label] name address Clock, clk Word, w With RPT, clk Class CALL pma16 2 2 N/R 7c CALL *An 2 1 N/R 7c Execution R7 ⇐ R7 + 2 *R7 ⇐ TOS TOS ⇐ PC + 2 PC ⇐ *An or pma16 Flags Affected...

Individual Instruction Descriptions 4-87 Assembly Language Instructions 4.14.9 Ccc Conditional Subroutine Call Syntax [label] name address Clock, clk Word, w With RPT, clk Class Ccc † pma16 2 2 N/R 7c † Cannot immediately follow a CALL instruction with a return instruction. If true If Not true [labe...

Individual Instruction Descriptions 4-88 Table 4–48. Names for cc cc cc names Description cc cc name Not cc name p True condition (Not true condition) 0 0 0 0 0 Z NZ Conditional on ZF=1 (Not condition ZF=0) 0 0 0 0 1 S NS Conditional on SF=1 (Not condition SF=0) 0 0 0 1 0 C NC Conditional on CF=1 (N...

Individual Instruction Descriptions 4-91 Assembly Language Instructions 4.14.10 CMP Compare Two Words [label] name src, src1 [, mod] Clock, clk Word, w With RPT, clk Class CMP An, {adrs} Table 4–46 Table 4–46 1b CMP An[~], imm16 [, next A] 2 2 N/R 2b CMPCMP An, An~ [, next A]An~, An [, next A] 1 1 n...

Individual Instruction Descriptions 4-92 Example 4.14.10.3 CMP R2, 0xfe20 Compare value at R2 to immediate value 0xfe20 and change the STAT flags accordingly. Example 4.14.10.4 CMP R0, R5 Compare value at R0 to R5 and change the STAT flags accordingly.

Individual Instruction Descriptions 4-93 Assembly Language Instructions 4.14.11 CMPB Compare Two Bytes Syntax [label] name src, src1 Clock, clk Word, w With RPT, clk Class CMPB An, imm8 1 1 N/R 2a CMPB Rx, imm8 1 1 N/R 4b Execution status flags set by src – src1 bytePC ⇐ PC + 1 Flags Affected src is...

Individual Instruction Descriptions 4-95 Assembly Language Instructions 4.14.13 COR Correlation Filter Function Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class COR An, *Rx 3 1 3(n R +2) 9a Execution With RPT N–2:(mask interrupts)RPT counter = N–2MR = h[0] = first filter coeffici...

Individual Instruction Descriptions 4-96 4.14.14 CORK Correlation Filter Function Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class CORK An, *Rx 3 1 3(n R +2) 9a Execution With RPT N–2:(mask interrupts)RPT counter = N–2MR = h[0] = first filter coefficientx = sample data pointed at...

Individual Instruction Descriptions 4-97 Assembly Language Instructions 4.14.15 ENDLOOP End Loop Syntax [label] name # Clock, clk Word, w With RPT, clk Class ENDLOOP [n] 1 1 N/R 9d Execution If (R4 ≥ 0) decrement R4 by n (1 or 2) PC ⇐ first address after BEGLOOP else NOP PC ⇐ PC + 1 Flags Affected N...

Individual Instruction Descriptions 4-98 4.14.16 EXTSGN Sign Extend Word Syntax [label] name dest [, mod] Clock, clk Word, w With RPT, clk Class EXTSGN An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified]new most significant word of dest ⇐ STAT.SF PC ⇐ PC + 1 Flags Affected None O...

Individual Instruction Descriptions 4-99 Assembly Language Instructions 4.14.17 EXTSGNS Sign Extend String Syntax [label] name dest Clock, clk Word, w With RPT, clk Class EXTSGNS An[~] n R +3 1 n R +3 3 Execution new most significant word of dest ⇐ STAT.SF PC ⇐ PC + 1 Flags Affected None Opcode Inst...

Individual Instruction Descriptions 4-100 MOV AP1, 3 ; Point to loc corresponding to ; extended word in acc MOVS A0, *R0 ; R0 POINTS TO VALUE IN MEMORY EXTSGN A1 ; not string version as above Alternatively, the following code can do the same thing but requires more code: MOV AP0, 0 ; POINT TO LSW OF...

Individual Instruction Descriptions 4-101 Assembly Language Instructions 4.14.18 FIR FIR Filter Function (Coefficients in RAM) Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class FIR An, *Rx 2 1 2(n R +2) 9a Execution With RPT N–2:(mask interrupts)RPT counter = N–2MR = h[0] = first ...

Individual Instruction Descriptions 4-103 Assembly Language Instructions 4.14.19 FIRK FIR Filter Function (Coefficients in ROM) Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class FIRK An, *Rx 2 1 2(n R +2) 9a Execution With RPT N–2:(mask interrupts)RPT counter = N–2MR = h[0] = firs...

Individual Instruction Descriptions 4-104 4.14.20 IDLE Halt Processor Syntax [label] name Clock, clk Word, w With RPT, clk Class IDLE 1 1 N/R 9d Execution Stop processor clocksPC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDLE 1 1 1 1 1 1 1 1 0 0 0 1 0 ...

Individual Instruction Descriptions 4-105 Assembly Language Instructions 4.14.21 IN Input From Port Into Word Syntax [label] name dest, src1 Clock, clk Word, w With RPT, clk Class IN {adrs}, port4 Table 4–46 Table 4–46 6a IN An[~], port6 1 1 n R +3 6b Execution dest ⇐ content of port6 or port4 PC ⇐ ...

Individual Instruction Descriptions 4-106 4.14.22 INS Input From Port Into String Syntax [label] name src, src1 Clock, clk Word, w With RPT, clk Class INS An[~], port6 n S +2 1 n R +2 6b Execution dest ⇐ content of port6 PC ⇐ PC + 1 Flags Affected dest is An: OF, SF, ZF, CF are set accordingly Opcod...

Individual Instruction Descriptions 4-107 Assembly Language Instructions 4.14.23 INTD Interrupt Disable Syntax [label] name Clock, clk Word, w With RPT, clk Class INTD 1 1 N/R 9d Execution STAT.IM ⇐ 0 (IM is STAT bit 4) PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6...

Individual Instruction Descriptions 4-108 4.14.24 INTE Interrupt Enable Syntax [label] name Clock, clk Word, w With RPT, clk Class INTE 1 1 N/R 9d Execution STAT.IM ⇐ 1 (IM is STAT bit 4) PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTE 1 1 1 1 1 1 1 ...

Individual Instruction Descriptions 4-109 Assembly Language Instructions 4.14.25 IRET Return From Interrupt Syntax [label] name Clock, clk Word, w With RPT, clk Class IRET 2 1 N/R 5 Execution PC ⇐ TOS R7 ⇐ R7 – 2 TOS ⇐ *R7 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Individual Instruction Descriptions 4-110 4.14.26 Jcc Conditional Jumps Syntax [label] name pma16 [, Rmod] Clock, clk Word, w With RPT, clk Class Jcc pma16 [, Rmod] 2 2 N/R 7b If true If Not true [label][label][label][label][label][label][label][label][label][label][label][label][label][label][label...

Individual Instruction Descriptions 4-113 Assembly Language Instructions Syntax Description AlternateInstruction JRNLZP pma16 [, Rmod] Conditional jump on Rx ≥ 0 after post-mod JRZP pma16 [, Rmod] Conditional jump on Rx = 0 after post-mod JRNZP pma16 [, Rmod] Conditional jump on Rx ≠ 0 after post-mo...

Individual Instruction Descriptions 4-114 4.14.27 JMP Unconditional Jump Syntax [label] name dest [, mod] Clock, clk Word, w With RPT, clk Class JMP pma16 2 2 N/R 7b JMP pma16, Rx++ 2 2 N/R 7b JMP pma16, Rx– – 2 2 N/R 7b JMP pma16, Rx++R5 2 2 N/R 7b JMP *An 2 1 N/R 7b Execution PC ⇐ dest [Post–modif...

Individual Instruction Descriptions 4-115 Assembly Language Instructions 4.14.28 MOV Move Data Word From Source to Destination Syntax [label] name dest, src, [, next A] Clock, clk Word, w With RPT, clk Class MOV {adrs}, An[~] [, next A] Table 4–46 Table 4–46 1a MOV An[~], {adrs} [, next A] Table 4–4...

Individual Instruction Descriptions 4-116 [label] Class With RPT, clk Word, w Clock, clk dest, src, [, next A] name MOV TFn, {cc} [, Rx] 1 1 N/R 8b MOV STR, imm8 1 1 N/R 9b MOV SV, imm4 1 1 N/R 9b MOV APn, imm5 1 1 N/R 9c Execution [premodify AP if mod specified]dest ⇐ src PC ⇐ PC + w Flags Affected...

Individual Instruction Descriptions 4-119 Assembly Language Instructions Syntax Description MOV STR, imm8 Move immediate byte to String Register (STR) MOV APn, imm5 Move immediate 5-bit value to APn register † Accumulator condition flags are modified to reflect the value loaded into either An or An~...

Individual Instruction Descriptions 4-120 Example 4.14.28.13 MOV R1, 0x0200 * 2 Load immediate word memory address 0x0200 to R1. Example 4.14.28.14 MOV R7, (0x0280 – 32) * 2 Load R7 (stack register) with the starting value of stack, i.e., 0x0260. Example 4.14.28.15 MOV *0x0200 * 2, R0 Store R0 to da...

Individual Instruction Descriptions 4-121 Assembly Language Instructions 4.14.29 MOVAPH Move With Adding PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVAPH An, MR, {adrs} Table 4–46 Table 4–46 1b Execution An ⇐ An + PH MR ⇐ contents of {adrs} PC ⇐ PC + w Flags Affec...

Individual Instruction Descriptions 4-122 4.14.30 MOVAPHS Move With Adding PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVAPHS An, MR, {adrs} Table 4–46 Table 4–46 1b Execution An ⇐ An + PH MR ⇐ contents of {adrs} PC ⇐ PC + w Flags Affected TAG, OF, SF, ZF, CF are s...

Individual Instruction Descriptions 4-123 Assembly Language Instructions 4.14.31 MOVB Move Byte From Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVB An, {adrs} Table 4–46 Table 4–46 1b MOVB {adrs}, An Table 4–46 Table 4–46 1b MOVB An, imm8 1 1 N/R 2a M...

Individual Instruction Descriptions 4-124 Example 4.14.29.2 MOVB *R2, A0 Copy lower 8 bits of accumulator A0 to the data memory byte pointed by R2. Example 4.14.29.3 MOVB A0, 0xf2 Load accumulator A0 with value of 0xf2. Example 4.14.29.4 MOVB MR, 34 Load MR register with immidiate value of 34 (decim...

Individual Instruction Descriptions 4-125 Assembly Language Instructions 4.14.32 MOVBS Move Byte String from Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVBS An, {adrs} 8 Table 4–46 Table 4–46 1b MOVBS {adrs}, An Table 4–46 Table 4–46 1b Execution dest...

Individual Instruction Descriptions 4-126 4.14.33 MOVS Move String from Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVS An[~], {adrs} Table 4–46 Table 4–46 1a MOVS {adrs}, An[~] Table 4–46 Table 4–46 1a MOVS {adrs}, *An Table 4–46 Table 4–46 1b MOVS An...

Individual Instruction Descriptions 4-128 4.14.34 MOVSPH Move With Subtract from PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVSPH An, MR, {adrs} Table 4–46 Table 4–46 1b Execution An ⇐ An – PH MR ⇐ contents of {adrs} PC ⇐ PC + w Flags Affected TAG, OF, SF, ZF, CF ...

Individual Instruction Descriptions 4-129 Assembly Language Instructions 4.14.35 MOVSPHS Move String With Subtract From PH Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class MOVSPHS An, MR, {adrs} Table 4–46 Table 4–46 1b Execution An ⇐ An (second word) – PH MR ⇐ contents of ...

Individual Instruction Descriptions 4-130 4.14.36 MOVT Move Tag From Source to Destination Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MOVT {adrs}, TFn Table 4–46 Table 4–46 5 Execution dest ⇐ src PC ⇐ PC + w Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7...

Individual Instruction Descriptions 4-131 Assembly Language Instructions 4.14.37 MOVU Move Data Unsigned Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class MOVU MR, An[~] [, next A] 1 1 n R +3 3 MOVU MR, {adrs} Table 4–46 Table 4–46 5 Execution [premodify AP if mod specifie...

Individual Instruction Descriptions 4-133 Assembly Language Instructions 4.14.38 MUL Multiply (Rounded) Syntax [label] name src [, mod] Clock, clk Word, w With RPT, clk Class MUL An[~] [, next A] 1 1 n R +3 3 MUL {adrs} Table 4–46 Table 4–46 5 Execution [premodify AP if mod specified]PH,PL ⇐ MR * sr...

Individual Instruction Descriptions 4-134 4.14.39 MULR Multiply (Rounded) With No Data Transfer Syntax [label] name src Clock, clk Word, w With RPT, clk Class MULR {adrs} Table 4–0–46 Table 4–0–46 5 Execution PH,PL ⇐ MR * src PC ⇐ PC + 1 Flags Affected TAG bit is set accordingly Opcode Instructions ...

Individual Instruction Descriptions 4-135 Assembly Language Instructions 4.14.40 MULS Multiply String With No Data Transfer Syntax [label] name src Clock, clk Word, w With RPT, clk Class MULS An [~] n S +3 1 n R +3 3 Execution PH,PL ⇐ MR * src string PC ⇐ PC + 1 Flags Affected None Opcode Instructio...

Individual Instruction Descriptions 4-136 4.14.41 MULAPL Multiply and Accumulate Result Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class MULAPL An, {adrs} Table 4–46 Table 4–46 1b MULAPL An[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified]PH,PL ⇐...

Individual Instruction Descriptions 4-137 Assembly Language Instructions 4.14.42 MULAPLS Multiply String and Accumulate Result Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class MULAPLS An, {adrs} Table 4–46 Table 4–46 1b MULAPLS An[~], An[~] n S +3 1 n R +3 3 Execution PH,...

Individual Instruction Descriptions 4-138 4.14.43 MULSPL Multiply and Subtract PL From Accumulator Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class MULSPL An, {adrs} Table 4–46 Table 4–46 1b MULSPL An[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specif...

Individual Instruction Descriptions 4-139 Assembly Language Instructions 4.14.44 MULSPLS Multiply String and Subtract PL From Accumulator Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MULSPLS An, {adrs} Table 4–46 Table 4–46 1b MULSPLS An[~], An[~] n S +3 1 n R +3 3 Execution ...

Individual Instruction Descriptions 4-140 4.14.45 MULTPL Multiply and Transfer PL to Accumulator Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class MULTPL An, {adrs} Table 4–46 Table 4–46 1b MULTPL An[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specifie...

Individual Instruction Descriptions 4-141 Assembly Language Instructions 4.14.46 MULTPLS Multiply String and Transfer PL to Acumulator Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class MULTPLS An, {adrs} Table 4–46 Table 4–46 1b MULTPLS An[~], An[~] n S +3 1 n R +3 3 Execution PH,...

Individual Instruction Descriptions 4-142 4.14.47 NEGAC Two’s Complement Negation of Accumulator Syntax [label] name dest, src [,mod] Clock, clk Word, w With RPT, clk Class NEGAC An[~], An[~] [, next A] n S +3 1 n R +3 3 Execution [premodify AP if mod specified]dest ⇐ –src PC ⇐ PC + 1 Flags Affected...

Individual Instruction Descriptions 4-143 Assembly Language Instructions 4.14.48 NEGACS Two’s Complement Negation of Accumulator String Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class NEGACS An[~], An[~] n S +3 1 n R +3 3 Execution dest ⇐ –src PC ⇐ PC + 1 Flags Affected OF, SF, ...

Individual Instruction Descriptions 4-144 4.14.49 NOP No Operation Syntax [label] name Clock, clk Word, w With RPT, clk Class NOP 1 1 n R +3 9d Execution PC ⇐ PC + 1 (No operation) Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ...

Individual Instruction Descriptions 4-145 Assembly Language Instructions 4.14.50 NOTAC One’s Complement Negation of Accumulator Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class NOTAC An[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified]dest ⇐ NOT ...

Individual Instruction Descriptions 4-146 4.14.51 NOTACS One’s Complement Negation of Accumulator String Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class NOTACS An[~], An[~] n S +2 1 n R +2 3 Execution dest ⇐ NOT src PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly O...

Individual Instruction Descriptions 4-147 Assembly Language Instructions 4.14.52 OR Bitwise Logical OR Syntax [label] name dest, src [, src1] [, mod] Clock, clk Word, w With RPT, clk Class OR An, {adrs} Table 4–46 Table 4–46 1b OR An[~], An[~], imm16 [, next A] 2 2 N/R 2b OR An[~], An~, An [, next A...

Individual Instruction Descriptions 4-149 Assembly Language Instructions 4.14.53 ORB Bitwise OR Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class ORB An, imm8 1 1 N/R 2a Execution dest ⇐ dest OR src PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instruct...

Individual Instruction Descriptions 4-150 4.14.54 ORS Bitwise OR String Syntax [label] name dest, src [, src1] Clock, clk Word, w With RPT, clk Class ORS An, {adrs} Table 4–46 Table 4–46 1b ORS An[~], An[~], pma16 n S +4 2 N/R 2b ORS An[~], An~, An n S +2 1 n R +2 3 Execution dest ⇐ dest OR src (for...

Individual Instruction Descriptions 4-151 Assembly Language Instructions 4.14.55 OUT Output to Port Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class OUT port4, {adrs} Table 4–46 n R +3 6a OUT port6, An[~] Table 4–46 n R +3 6a Execution port4 or port6 ⇐ src PC ⇐ PC + w Flags Affec...

Individual Instruction Descriptions 4-152 4.14.56 OUTS Output String to Port Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class OUTS port6, An[~] n R +2 1 n R +2 6b Execution port6 ⇐ src PC ⇐ PC + 1 Flags Affected XSF, XZF are set accordingly Opcode Instructions 16 15 14 13 12 11 1...

Individual Instruction Descriptions 4-153 Assembly Language Instructions 4.14.57 RET Return From Subroutine (CALL, Ccc) Syntax [label] name Clock, clk Word, w With RPT, clk Class RET 1 1 N/R 5 Execution PC ⇐ TOS TOS ⇐ *R7 R7 ⇐ R7 – 2 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7...

Individual Instruction Descriptions 4-154 4.14.58 RFLAG Reset Memory Flag Syntax [label] name src Clock, clk Word, w With RPT, clk Class RFLAG {flagadrs} 1 1 N/R 8a Execution memory flag bit at {flagadrs} data memory location ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 ...

Individual Instruction Descriptions 4-155 Assembly Language Instructions 4.14.59 RFM Reset Fractional Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class RFM 1 1 N/R 9d Execution STAT.FM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM ...

Individual Instruction Descriptions 4-156 4.14.60 ROVM Reset Overflow Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class ROVM 1 1 N/R 9d Execution STAT.OM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0...

Individual Instruction Descriptions 4-157 Assembly Language Instructions 4.14.61 RPT Repeat Next Instruction Syntax [label] name src Clock, clk Word, w With RPT, clk Class RPT {adrs} 8 Table 4–46 N/R 5 RPT imm8 1 1 N/R 9b Execution IF RPT {adrs} 8 load src to repeat counter. ELSE load imm8 to repeat...

Individual Instruction Descriptions 4-158 4.14.62 RTAG Reset Tag Syntax [label] name dest Clock, clk Word, w With RPT, clk Class RTAG {adrs} Table 4–46 Table 4–46 5 Execution memory tag bit at {adrs} data memory location ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 ...

Individual Instruction Descriptions 4-159 Assembly Language Instructions 4.14.63 RXM Reset Extended Sign Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class RXM 1 1 N/R 9d Execution STAT.XM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R...

Individual Instruction Descriptions 4-160 4.14.64 SFLAG Set Memory Flag Syntax [label] name dest Clock, clk Word, w With RPT, clk Class SFLAG {flagadrs} 1 1 N/R 8a Execution memory flag bit at {flagadrs} data memory location ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 1...

Individual Instruction Descriptions 4-161 Assembly Language Instructions 4.14.65 SFM Set Fractional Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SFM 1 1 N/R 9d Execution STAT.FM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 ...

Individual Instruction Descriptions 4-162 4.14.66 SHL Shift Left Syntax [label] name dest [, mod] Clock, clk Word, w With RPT, clk Class SHL An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified]PH, PL ⇐ src << SV PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly O...

Individual Instruction Descriptions 4-163 Assembly Language Instructions 4.14.67 SHLAC Shift Left Accumulator Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class SHLAC An[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified]dest ⇐ src << 1 PC ⇐ PC...

Individual Instruction Descriptions 4-164 4.14.68 SHLACS Shift Left Accumulator String Individually Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SHLACS An[~], An[~] n S +2 1 n R +2 3 Execution dest ⇐ src << 1 PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly...

Individual Instruction Descriptions 4-165 Assembly Language Instructions 4.14.69 SHLAPL Shift Left with Accumulate Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class SHLAPL An, {adrs} Table 4–46 Table 4–46 1b SHLAPL An[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify ...

Individual Instruction Descriptions 4-166 4.14.70 SHLAPLS Shift Left String With Accumulate Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SHLAPLS An, {adrs} Table 4–46 Table 4–46 1b SHLAPLS An[~], An[~] n S +3 1 n R +3 3 Execution PH, PL ⇐ src << SV dest ⇐ dest + PL PC ⇐...

Individual Instruction Descriptions 4-167 Assembly Language Instructions 4.14.71 SHLS Shift Left Accumulator String to Product Syntax [label] name dest Clock, clk Word, w With RPT, clk Class SHLS An[~] n S +3 1 n R +3 3 Execution PH, PL ⇐ src << SV PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are...

Individual Instruction Descriptions 4-168 4.14.72 SHLSPL Shift Left With Subtract PL Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class SHLSPL An, {adrs} Table 4–46 Table 4–46 1b SHLSPL An[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified]PH, PL ⇐ s...

Individual Instruction Descriptions 4-169 Assembly Language Instructions 4.14.73 SHLSPLS Shift Left String With Subtract PL Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SHLSPLS An, {adrs} Table 4–46 Table 4–46 1b SHLSPLS An[~], An[~] n S +3 1 n R +3 3 Execution PH, PL ⇐ src &...

Individual Instruction Descriptions 4-170 4.14.74 SHLTPL Shift Left and Transfer PL to Accumulator Syntax [label] name dest, src [, mod] Clock, clk Word, w With RPT, clk Class SHLTPL An, {adrs} Table 4–46 Table 4–46 1b SHLTPL An[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specif...

Individual Instruction Descriptions 4-171 Assembly Language Instructions 4.14.75 SHLTPLS Shift Left String and Transfer PL to Accumulator Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SHLTPLS An, {adrs} Table 4–46 Table 4–46 1b SHLTPLS An[~], An[~] n S +3 1 n R +3 3 Execution ...

Individual Instruction Descriptions 4-172 4.14.76 SHRAC Shift Accumulator Right Syntax [label] name dest, src, [, mod] Clock, clk Word, w With RPT, clk Class SHRAC An[~], An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified]dest ⇐ src >> 1 PC ⇐ PC + 1 Flags Affected OF, SF, Z...

Individual Instruction Descriptions 4-173 Assembly Language Instructions 4.14.77 SHRACS Shift Accumulator String Right Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SHRACS An[~], An[~] n S +3 1 n R +3 3 Execution dest ⇐ src >> 1 PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF ...

Individual Instruction Descriptions 4-174 4.14.78 SOVM Set Overflow Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SOVM 1 1 N/R 9d Execution STAT.OM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOVM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 ...

Individual Instruction Descriptions 4-175 Assembly Language Instructions 4.14.79 STAG Set Tag Syntax [label] name dest Clock, clk Word, w With RPT, clk Class STAG {adrs} Table 4–46 Table 4–46 5 Execution memory tag bit at address adrs ⇐ 1 PC ⇐ PC + w Flags Affected None Opcode Instructions 16 15 14 ...

Individual Instruction Descriptions 4-176 4.14.80 SUB Subtract Syntax [label] name dest, src, src1, [next A]] Clock, clk Word, w With RPT, clk Class SUB An[~], An, {adrs} [, next A] Table 4–46 Table 4–46 1a SUB An[~], An[~], imm16 [, next A] 2 2 N/R 2b SUB An[~], An[~], PH [, next A] 1 1 n R +3 3 SU...

Individual Instruction Descriptions 4-178 4.14.81 SUBB Subtract Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class SUBB An, imm8 1 1 N/R 2a SUBB Rx, imm8 1 1 N/R 4b Execution dest ⇐ dest – imm8 PC ⇐ PC + 1 Flags Affected dest is An: OF, SF, ZF, CF are set accordingly dest is R...

Individual Instruction Descriptions 4-179 Assembly Language Instructions 4.14.82 SUBS Subtract Accumulataor String Syntax [label] name dest, src, src1 Clock, clk Word, w With RPT, clk Class SUBS An[~], An, {adrs} Table 4–46 Table 4–46 1a SUBS An[~], An[~], pma16 n s +4 2 N/R 32b SUBS An[~], An, An~ ...

Individual Instruction Descriptions 4-182 4.14.84 VCALL Vectored Call Syntax [label] name dest Clock, clk Word, w With RPT, clk Class VCALL vector8 2 1 N/R 7a Execution Push PC + 1PC ⇐ *(0x7F00 + vector8) R7 ⇐ R7 + 2 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VC...

Individual Instruction Descriptions 4-183 Assembly Language Instructions 4.14.85 XOR Logical XOR Syntax [label] name dest, src, src1 [, mod] Clock, clk Word, w With RPT, clk Class XOR An, {adrs} Table 4–46 Table 4–46 1a XOR An[~], An[~], imm16 [, next A] 2 2 N/R 2b XOR An[~], An~, An [, next A] 1 1 ...

Individual Instruction Descriptions 4-185 Assembly Language Instructions 4.14.86 XORB Logical XOR Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class XORB An, imm8 1 1 N/R 2a Execution An ⇐ An XOR imm8 (for two operands) PC ⇐ PC + 1 Flags Affected dest is An: OF, SF, ZF, CF are...

Individual Instruction Descriptions 4-186 4.14.87 XORS Logical XOR String Syntax [label] name dest, src [, src1] Clock, clk Word, w With RPT, clk Class XORS An, {adrs} Table 4–46 Table 4–46 1b XORS An[~], An[~], pma16 n S +4 2 N/R 2b XORS An[~], An~, An n S +3 1 n R +3 3 Execution dest ⇐ dest XOR sr...

Individual Instruction Descriptions 4-187 Assembly Language Instructions 4.14.88 ZAC Zero Accumulator Syntax [label] name dest [, mod] Clock, clk Word, w With RPT, clk Class ZAC An[~] [, next A] 1 1 n R +3 3 Execution [premodify AP if mod specified]dest ⇐ 0 PC ⇐ PC + 1 Flags Affected ZF = 1 Instruct...

Individual Instruction Descriptions 4-188 4.14.89 ZACS Zero Accumulator String Syntax [label] name dest Clock, clk Word, w With RPT, clk Class ZAC An n S +3 1 n R +3 3 Execution dest ⇐ 0 PC ⇐ PC + 1 Flags Affected ZF = 1 Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ZACS An[~] 1 1 1 0 0 1 1 ...

Instruction Set Encoding 4-189 Assembly Language Instructions 4.15 Instruction Set Encoding Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADD An[~], An, {adrs} [, next A] 1 1 1 0 ~A next A An adrs x dma16 (for direct) or offset16 (long relative) [see section 4.13] ADD An[~], An[~], imm16 [, ...

Instruction Set Summary 4-198 4.16 Instruction Set Summary Use the legend in Section 4.13 and the following table to obtain a summary ofeach instruction and its format. For detail about the instruction refer to thedetail description of the instruction. name dest [, src] [, src1] [,mod] Clock, clk Wo...

5-1 Code Development Tools This chapter describes the code development tools for the MSP50C6xx familyof devices. The MSP50C6xx code development tool is used to compile,assemble, link, and debug programs. A reduced function C compiler,(called C– –) is also part of the code development tool. Topic Pag...

Introduction 5-2 5.1 Introduction The MSP50C6xx code development tool is a system made up of a personalcomputer (PC), the EMUC6xx software, an MSP scanport interface, and aMSP50P614 connected to the application circuits. EMUC6xx is the software that executes on the PC and provides a userinterface to...

Introduction 5-3 Code Development Tools Figure 5–1. 10-Pin IDC Connector (top view looking at the board) IDC2X5M RESET VPP SCANCLK PGMPULSE SYNC GND N/C SCANIN VDD SCANOUT 1 3 5 7 9 2 4 6 8 10 PINOUT DETAILS 10-PIN HEADER (3M PART# 2510–6002UB) LAYOUT DETAILS 0.1 I 0.800 I 0.1 I IDC2X5M HOLE DIA 0.0...

MSP50C6xx Development Tools Guidelines 5-4 amplifiers, an 8-position DIP switch and two momentary switches connectedto I/O pins. These boards are discussed more in Sections 5.2.2 and 5.2.4. 5.2 MSP50C6xx Development Tools Guidelines This is a summary of the tools needed for code development and spee...

MSP50C6xx Development Tools Guidelines 5-5 Code Development Tools - If the user is developing host code to be used with a catalog MSP50C604operating in slave mode: J Hardware H Catalog device H SPEECH-EVM † H PC50C604 † † These items are not needed if the customer designs their own preproduction app...

MSP50C6xx Development Tools Guidelines 5-6 The emulation personality card, for the speech-EVM, that supports codedevelopment on the MSP50C614, MSP50C605, MSP50C601, andMSP50C604 (being used in master mode). A MSP50P614 is used on thisboard to emulate the MSP50C6xx core. An EPROM is used on theSPEECH...

MSP50C6xx Development Tools Guidelines 5-7 Code Development Tools - EVA50C605 (see the following note) Same as SPEECH-EVM. Note: The SPEECH-EVM and EVA50C605 have similar functionality. They bothfunction as basic target boards that support code development. One of thedifferences is that the SPEECH-E...

MSP50C6xx Development Tools Guidelines 5-8 5.2.3 Documentation - MSP50C6xx Product Folders http://www.ti.com/sc/docs/products/speechh/index.htm - MSP50C6xx User’s Guide - Datasheet MSP50C614: MSP50C605: MSP50C601: MSP50C604: - Applications Notes Documents that help users in developing code for MSP50...

MSP50C6xx Development Tools Guidelines 5-9 Code Development Tools 5.3.2 Hardware Tools Setup Step 1: Plug in an appropriate personality card (see the following note) on the SPEECH-EVM or EVA50C605. Note: EPC50C605: developing code for MSP50C604 (in master mode,MSP50C601, MSP50C605, or MSP50C614). EP...

MSP50C6xx Development Tools Guidelines 5-10 Note: There is a three-way switch at the edge of the SPEECH-EVM board. Afteryou apply power to the SPEECH-EVM, you have to turn on the SPEECH-EVM. There are two ways to turn on the board depending on the powersources: - If you are using the on board with A...

Assembler 5-11 Code Development Tools 5.4 Assembler 5.4.1 Assembler Directives Assembler directives are texts which have special meaning to the assembler.Some of these directives are extremely helpful during conditional compiling,debugging, adding additional features to existing codes, multiple hard...

Assembler 5-12 | (expression) (~ indicates bitwise complement) symbol is any alphanumeric text starting with an alphabetic character, a number, or an expression. Examples: SYM1 EQU (12 * 256) SYM2 EQU SYM1 * (32 / 4) SYM3 EQU SYM1 * SYM2 – *0x200 From the above example SYM1, SYM2 and SYM3 are symbol...

Assembler 5-14 Example: #IFDEF symbol ; do something here#ELSE; do other things here#ENDIF #IFNDEF symbol ; do something here#ELSE; do other things here#ENDIF #START_FT: This directive is created by the C– – compiler when it outputs assembly code to a file. It marks the beginning of the function tab...

Assembler 5-15 Code Development Tools END expression: Expression defines the start vector for the current assembly program. This directive generates the following assembly code; AORG 0xFFFF DATA expression which defines the start vector of the program, i.e., the program address whereexecution begins...

C– – Compiler 5-16 label RESW expression: This directive is used to reserve the number of words indicated by expression, starting at the current RAM address. label is given thevalue of the current RAM address. If the current RAM address is not EVEN,the assembler increments it by 1 before allocating ...

C– – Compiler 5-17 Code Development Tools 5.5.2 Variable Types Type Name Mnemonic Range Size in Bytes Example Integer int [–32768,32767] 2 int i,j; Character char [0,255] 1 char c,d; Array of integer int Not Applicable Not Applicable int array[12]; Array of characters char Not Applicable forced to e...

C– – Compiler 5-18 5.5.4 C– – Directives C– – has a limited number of directives and some additional directives notfound in ANSI C compilers. The following directives are recognized by thecompiler. 5.5.4.1 #define This directive is used to introduce 2 types of macros, in typical C fashion: Without A...

C– – Compiler 5-19 Code Development Tools Example:#include “file.h”#include <stdio.h> The include directories are defined on the cmm_input structure passed to the compiler. There is no limit to the nesting of include files. 5.5.4.4 #asm All text following this directive is inserted as is in th...

C– – Compiler 5-20 /********************************/ /* Prototypes for C– –functions */ /********************************/ cmm_func add_string(int *result,int *str1,int *str2,int lg); cmm_func sub_string(int *result,int *str1,int *str2,int lg); cmm_func mul_string(int *result,int *str1,int mult,int...

C– – Compiler 5-21 Code Development Tools Although we have tried to keep the differences between regular C and C– –to a minimum, there are still a few that require explanation. 5.5.6 Function Prototypes and Declarations C– – function prototypes and declarations MUST be preceded with thekeyword cmm_f...

C– – Compiler 5-22 5.5.9 String Functions Arithmetic string functions are special functions that perform string arithmetic.The functions currently implemented are shown in Table 5–1. Table 5–1. String Functions add_string(int *result,int *str1,int *str2,int lg) adds strings str1 and str2, of length ...

C– – Compiler 5-23 Code Development Tools the MSP50C6xx length of the string. It is included in the cmm_macr.h file, and is called STR_LENGTH(lstr). For example, STR_LENGTH(8) is 8–2 = 6. Also note that the user has to supply the length of the input string and the lengthof the output string in the s...

Implementation Details 5-24 5.6 Implementation Details This section is C– – specific. 5.6.1 Comparisons We use the CMP instruction for both signed and unsigned comparisons. Thetwo integers a and b to be compared are in A0 and A0~. CMP A0,A0~ : A0 contains a, A0~ contains b A0 A0~ ACO AZ ANEG 5 0 1 0...

Implementation Details 5-25 Code Development Tools - Unsigned comparison of a and b. (a is in A0, b is in A0~) Assembly Test Condition _ult a < b AULT _ule a <= b !AUGT _uge a >= b !AULT _ugt a > b AUGT The small number of comparisons was an invitation to use them as vectorcalls. We retu...

Implementation Details 5-26 5.6.2 Division Integer division currently requires the use of several accumulator pointers. Wedivide a 16 bit integer located in A0 by a 16 bit integer located in A0~. We returnthe quotient in A0~, and the remainder in A0. We make use of A3~ and A3 forscratch pads. We als...

Implementation Details 5-27 Code Development Tools declarations ( or function prototypes) are introduced by the mnemonic cmm_func . We only allow the new style of function declarations /prototypes, where the type of the arguments is declared within the function’s parentheses.For example: cmm_func bi...

Implementation Details 5-28 #include “cmm_macr.h” constant int M1[4]={0x04CB,0x71FB,0x011F,0x0}; constant int M2[4]={0x85EB,0x8FD9,0x08FB,0x0}; cmm_func string_multiply(int *p,int lgp,int *m1,int lgm1,int *m2,int lgm2) { /* note: length of p,(lgp+2) must be at least (lgm1+2) + (lgm2+2) +1 */ /* this...

Implementation Details 5-29 Code Development Tools add_string(p,pp,p,lgm1+i+1); } if(sign == –1) { neg_string(pp,p,STR_LENGTH((lgp+2))); copy_string(p,pp,STR_LENGTH((lgp+2))); } free(mm1); free(mm2); free(pp); } cmm_func main(int argc,char *argv) { int m1[4],m2[4],product[9]; xfer_const(m1,M1,STR_LE...

Implementation Details 5-31 Code Development Tools | | | | | | |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| | | | | | | |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| | | | | | | |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| | | | | | | |–––––––––––––––| |–––––––––––––––| |––...

C– – Efficiency 5-37 Code Development Tools C to ASM function return | | | | |––––––––––––––| |––––––––––––––| | | | | |––––––––––––––| |––––––––––––––| | | | | |––––––––––––––| |––––––––––––––| | | | | |––––––––––––––| |––––––––––––––| | | | | |––––––––––––––| |––––––––––––––| |Return Addr | |Retur...

C– – Efficiency 5-39 Code Development Tools 5.7.1 Real Time Clock Example The C– – clock works as follows. The Timer2 ISR is set to fire at 1-secondintervals. Inside the ISR a counter is incremented by one each time it fires. Anassembly routine in cmm1.asm (_getSecondsPassed) disables the interrupts...

C– – Efficiency 5-41 Code Development Tools Seven of the files are important to the functionality of this project. The Timer2ISR (tim2_isr.asm) forms the basis for the RTC so it will be discussed first. timer2_isr mov *save_tim2_stat,STAT ;save status mov *save_tim2_a0,a0 ;save a0 ; timer fired so 1...

C– – Efficiency 5-50 inteiret Cmm1.asm was modified to include routines for sleeping and speaking fromC– –. global _inportD global _getSecondsPassed global _sleepQuarterSec global _speakDays global _speakOnes global _speakTens global _speakTeens global _speakAMPM New C– – callable functions were dec...

C– – Efficiency 5-54 Descriptions of files that are also in Project 2 have been omitted. [lcd] Directory holding files for writing to an LCD screen. lcd.asm Routines for writing to an LCD screen. lcd.irx Mnemonics used by lcd.asm. lcd_ram.irx Allocates RAM for lcd.asm. The only changes to the assemb...

Beware of Stack Corruption 5-57 Code Development Tools 5.8 Beware of Stack Corruption MSP50C614/MSP50P614 stack (pointed by R7 register) can easily getcorrupted if care is not taken. Notice the following table read code: SUBB R7, 4 MOV A0, *R7–– ADD A0, address MOV A0, *A0 ADD A0, *R7–– MOV A0, *A0 ...

Reported Bugs With Code Development Tool 5-58 5.9 Reported Bugs With Code Development Tool The following are reported bugs for code development tool version 2.39. Breakpoint: Placement of hardware breakpoints is important for reliableoperation. Pipeline latency and sleep modes affect the scan logic ...

6-1 Applications This chapter contains application information on application circuits,processor initialization sequence, resistor trim setting, synthesis code,memory overlays, and ROM usage. Topic Page 6.1 Application Circuits 6–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Application Circuits 6-2 6.1 Application Circuits Figure 6–1. Minimum Circuit Configuration for the C614/P614 Using a Resistor-TrimmedOscillator To pin 2 of Scan Port Connector † MSP50C614/MSP50P614 To pin 1 of Scan Port Connector † (optional ) 5 V 0.1 µ F (5) R REFERENCE 470 k Ω (1%) 3300 pF OSC IN...

Application Circuits 6-3 Applications It is of particular importance to provide a separate decoupling capacitor for theV DD , V SS pair which services the DAC. These pins are pad numbers 21 and 19, respectively. The relatively high current demands of the digital-to-analogcircuitry make this a requir...

Initializing the MSP50C6xx 6-4 In any MSP50C614 application, it is important for certain components to belocated as close as possible to the MSP50C614 die or package. These includeany of the decoupling capacitors at V DD (0.1 µ F). It also includes all of the components in the crystal-reference netw...

Initializing the MSP50C6xx 6-5 Applications 6.2.1 File init.asm ;****************************************************************; INIT.ASM;; Revision 1.04;; Modified from revision 1.03: if not CRO, we check port 0x2F; to distinguish between P and ; C parts.;; Turn off TIMER 2 rather than leave it r...

TI-TALKS Example Code 6-8 6.3 TI-TALKS Example Code The TI-TALKS code contains the four vocoders (MELP, CELP, ADPCM, andLPC) and demonstrates how to use the interrupts to scan the keys and flashthe LEDs. An LCD driver module is also included. TI-TALKS should be used as a starting point for code deve...

RAM Overlay 6-9 Applications Creating a New Project The easiest way to create a new project is to copy the entire TI–TALKS604directory into another directory and renaming the project file as desired. It isnot necessary to change the paths of the files in the project – this will be doneautomatically ...

RAM Overlay 6-11 Applications save_tim2_stat equ save_tim1_a0a + 2 * 1 save_tim2_a0 equ save_tim2_stat + 2 * 1 save_tim2_a0a equ save_tim2_a0 + 2 * 1 ;End of RAM RAMEND_CUSTOMER equ save_tim2_a0a RAMLENGTH_CUSTOMER equ RAMEND_CUSTOMER – RAMSTART_CUSTOMER After adding new_var the MAIN_RAM.IRX file wo...

7-1 Customer Information Customer information regarding package configurations, development cycle,and ordering forms are included in this chapter. Topic Page 7.1 Mechanical Information 7–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Customer Information Fields...

Mechanical Information 7-2 7.1 Mechanical Information The MSP50C614, MSP50C605, and the MSP50C601 are normally sold in dieform, but are also available in a 100-pin QFP package. The MSP50C604 is aavailable in die form and in a 64-pin QFP package. The MSP50P614 isavailable in a 120-pin, PGA-windowed c...

Mechanical Information 7-3 Customer Information Table 7–1. Signal and Pad Descriptions for the MSP50C614 SIGNAL PIN NUMBER PAD NUMBER I/O DESCRIPTION Input/Output Ports PA0 – PA7 66 – 59 75 – 68 I/O Port A general-purpose I/O (1 Byte) PB0 – PB7 76 – 69 85 – 78 I/O Port B general-purpose I/O (1 Byte)...

Mechanical Information 7-4 Table 7–2. Signal and Pad Descriptions for the MSP50C605 SIGNAL PIN NUMBER PAD NUMBER I/O DESCRIPTION Input/Output Ports PC0 – PC7 89 – 82 8 – 1 I/O Port C general-purpose I/O (1 Byte) PD0 – PD7 99 – 92 18 – 11 I/O Port D general-purpose I/O (1 Byte) PE0 – PE7 46 – 39 48 –...

Mechanical Information 7-5 Customer Information Table 7–3. Signal and Pad Descriptions for the MSP50C601 SIGNAL PIN NUMBER PAD NUMBER I/O DESCRIPTION Input/Output Ports PC0 – PC7 89 – 82 8 – 1 I/O Port C general-purpose I/O (1 Byte) PD0 – PD7 99 – 92 18 – 11 I/O Port D general-purpose I/O (1 Byte) P...

Mechanical Information 7-6 Table 7–4. Signal and Pad Descriptions for the MSP50C604 SIGNAL PIN NUMBER PAD NUMBER I/O DESCRIPTION Input/Output Ports PC0 – PC7 89 – 82 8 – 1 I/O Port C general-purpose I/O (1 Byte) PD0 – PD7 99 – 92 18 – 11 I/O Port D general-purpose I/O (1 Byte) PE0 – PE7 46 – 39 48 –...

Mechanical Information 7-7 Customer Information Figure 7–1. 100-Pin QFP Mechanical Information 4040022 / B 03/95 0,16 NOM 14,20 17,45 13,80 16,95 50 51 31 30 12,35 TYP 1,030,73 0,25 Seating Plane 0,25 MIN Gage Plane 0,380,22 80 1 81 100 22,95 23,45 20,2019,80 2,50 2,90 3,40 MAX 18,85 TYP 0 ° – 7 ° M...

Mechanical Information 7-8 Figure 7–2. 64-Pin QFP Mechanical Information 4040152 / C 11/96 32 17 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN Gage Plane 0,27 33 16 48 1 0,17 49 64 SQ SQ 10,20 11,80 12,20 9,80 7,50 TYP 1,60 MAX 1,451,35 0,08 0,50 M 0,08 0 ° – 7 ° NOTES: A. All linear dimensions are...

Mechanical Information 7-9 Customer Information The MSP50C614 is available in a windowed-ceramic, 120-pin, grid array(PGA) packaged for use in software development and prototyping. This PGApackage is shown in Figure 7–3. Figure 7–3. 120-Pin, Grid Array Package for the Development Device, MSP50P614 e...

Customer Information Fields in the ROM 7-11 Customer Information 7.2 Customer Information Fields in the ROM Customer code information is inserted in the ROM by Texas Instruments. Thisinformation appears as seven distinct fields within the ROM test-area. TheROM test-area extends from address 0x0000 t...

Speech Development Cycle 7-12 7.3 Speech Development Cycle A sample speech development cycle is shown in Figure 7–5. Some of thecomponents, such as speech recording, speech analysis, speech editing, andspeech evaluation, require different hardware and software. TI provides aspeech development tool, ...

Ordering Information 7-14 7.5 Ordering Information Because the MSP50C6xx are custom devices, they receive a distinct identifi-cation, as follows: CSM Gate Code CSM: Custom Synthesizer With Memory 6xx XXX X X Family Member (614, 605, etc.) ROM Code Revision Letter Package or Die PJM: Loopin 100-Pin Q...

New Product Release Forms (NPRF) 7-15 Customer Information NEW PRODUCT RELEASE FORM FOR MSP50C614 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi-croprocessor code and speech data. Company:_________________ Division:______________ Project ...

New Product Release Forms (NPRF) 7-17 Customer Information NEW PRODUCT RELEASE FORM FOR MSP50C604 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi-croprocessor code and speech data. Company:_________________ Division:______________ Project ...

New Product Release Forms (NPRF) 7-19 Customer Information NEW PRODUCT RELEASE FORM FOR MSP50C605 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi-croprocessor code and speech data. Company:_________________ Division:______________ Project ...

New Product Release Forms (NPRF) 7-21 Customer Information NEW PRODUCT RELEASE FORM FOR MSP50C601 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi-croprocessor code and speech data. Company:_________________ Division:______________ Project ...

A-1 Appendix A Additional Information This appendix contains additional information for the MSP50C6xx mixed-sig-nal processor. Topic Page A.1 Additional Information A–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A

Additional Information A-2 A.1 Additional Information For current information regarding the MSP50C6xx devices (data sheets, de-velopment tools, etc.), visit the TI Speech Web site: http://www.ti.com/sc/speech