Page 3 - Preface; About This Manual; Program examples, are shown in a
Related Documentation From Texas Instruments iii Preface About This Manual This manual discusses modules and peripherals of the MSP430x1xx family ofdevices. Each discussion presents the module or peripheral in a generalsense. Not all features and functions of all modules or peripherals are presenton...
Page 4 - Glossary
Glossary iv Glossary ACLK Auxiliary Clock See Basic Clock Module ADC Analog-to-Digital Converter BOR Brown-Out Reset See System Resets, Interrupts, and Operating Modes BSL Bootstrap Loader See www.ti.com/msp430 for application reports CPU Central Processing Unit See RISC 16-Bit CPU DAC Digital-to-An...
Page 5 - Register Bit Conventions; Key
Register Bit Conventions v Register Bit Conventions Each register is shown with a key indicating the accessibility of the eachindividual bit, and the initial condition: Register Bit Accessibility and Initial Condition Key Bit Accessibility rw Read/write r Read only r0 Read as 0 r1 Read as 1 w Write ...
Page 7 - Introduction
Contents vii 1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Architecture 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....
Page 8 - Basic Clock Module
Contents viii 3 RISC 16-Bit CPU 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 CPU Introduction 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....
Page 9 - Supply Voltage Supervisor
Contents ix 6 Supply Voltage Supervisor 6-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 SVS Introduction 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2...
Page 10 - Contents; 0 Watchdog Timer
Contents x 10 Watchdog Timer 10-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Watchdog Timer Introduction 10-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2...
Page 11 - 4 USART Peripheral Interface, SPI Mode
Contents xi 14 USART Peripheral Interface, SPI Mode 14-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 USART Introduction: SPI Mode 14-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 USART Operation: SPI ...
Page 13 - This chapter describes the architecture of the MSP430.; Topic; Architecture; Chapter 1
1-1 Introduction This chapter describes the architecture of the MSP430. Topic Page 1.1 Architecture 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Flexible Clock System 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 14 - Ref; Flexible Clock System
Architecture 1-2 Introduction 1.1 Architecture The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clocksystem that interconnect using a von-Neumann common memory addressbus (MAB) and memory data bus (MDB). Partnering a modern CPU withmodular memory-mapped analog and digital perip...
Page 15 - Embedded Emulation; The benefits of embedded emulation include:
Embedded Emulation 1-3 Introduction Figure 1−1. MSP430 Architecture ACLK Bus Conv. Peripheral MAB 16-Bit MDB 16-Bit MCLK SMCLK Clock System Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Watchdog RAM Flash/ RISC CPU 16-Bit JT AG/Debug ACLK SMCLK ROM MDB 8-Bit JTAG 1.3 Embedded Emu...
Page 16 - Address Space; Figure 1−2. Memory Map; RAM
Address Space 1-4 Introduction 1.4 Address Space The MSP430 von-Neumann architecture has one address space shared withspecial function registers (SFRs), peripherals, RAM, and Flash/ROM memoryas shown in Figure 1−2. See the device-specific data sheets for specificmemory maps. Code access are always p...
Page 17 - Peripheral Modules; Organized Memory
Address Space 1-5 Introduction 1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address spacefrom 0100 to 01FFh is reserved for 16-bit peripheral modules. These modulesshould be accessed with word instructions. If byte instructions are used, onlyeven addresses are p...
Page 19 - System Resets, Interrupts, and Operating Modes; System Reset and Initialization; Chapter 2
2-1 System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x1xx system resets, interrupts, andoperating modes. Topic Page 2.1 System Reset and Initialization 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Interrupts 2-6 . . . . . . . . . . . . . . ...
Page 21 - Figure 2−2. POR Timing
System Reset and Initialization 2-3 System Resets, Interrupts, and Operating Modes 2.1.1 Power-On Reset (POR) When the V CC rise time is slow, the POR detector holds the POR signal active until V CC has risen above the V POR level, as shown in Figure 2−2. When the V CC supply provides a fast rise ti...
Page 22 - Figure 2−3. Brownout Timing; min
System Reset and Initialization 2-4 System Resets, Interrupts, and Operating Modes 2.1.2 Brownout Reset (BOR) Some devices have a brownout reset circuit (see device-specific datasheet)that replaces the POR detect and POR delay circuits. The brownout resetcircuit detects low supply voltages such as w...
Page 23 - Device Initial Conditions After System Reset; After a POR, the initial MSP430 conditions are:; Software Initialization; Initialize the SP, typically to the top of RAM.
System Reset and Initialization 2-5 System Resets, Interrupts, and Operating Modes 2.1.3 Device Initial Conditions After System Reset After a POR, the initial MSP430 conditions are: - The RST/NMI pin is configured in the reset mode. - I/O pins are switched to input mode as described in the Digital I...
Page 24 - Interrupts; There are three types of interrupts:; Figure 2−4. Interrupt Priority
System Reset and Initialization 2-6 System Resets, Interrupts, and Operating Modes 2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of themodules in the connection chain as shown in Figure 2−4. The nearer a moduleis to the CPU/NMIRS, the higher the priority. Interrupt...
Page 25 - An edge on the RST/NMI pin when configured in NMI mode; Modifying WDTNMIES
System Reset and Initialization 2-7 System Resets, Interrupts, and Operating Modes 2.2.1 (Non)-Maskable Interrupts (NMI) (Non)-maskable NMI interrupts are not masked by the general interrupt enablebit (GIE), but are enabled by individual interrupt enable bits (NMIIE, ACCVIE,OFIE). When a NMI interru...
Page 27 - Flash Access Violation
System Reset and Initialization 2-9 System Resets, Interrupts, and Operating Modes Flash Access Violation The flash ACCVIFG flag is set when a flash access violation occurs. The flashaccess violation can be enabled to generate an NMI interrupt by setting theACCVIE bit. The ACCVIFG flag can then be t...
Page 28 - Example of an NMI Interrupt Handler; Figure 2−6. NMI Interrupt Handler; Enabling NMI Interrupts with ACCVIE, NMIIE, and OFIE; RETI; Maskable Interrupts
System Reset and Initialization 2-10 System Resets, Interrupts, and Operating Modes Example of an NMI Interrupt Handler The NMI interrupt is a multiple-source interrupt. An NMI interrupt automaticallyresets the NMIIE, OFIE and ACCVIE interrupt-enable bits. The user NMIservice routine resets the inte...
Page 29 - Interrupt Processing; ) Any currently executing instruction is completed.; Figure 2−7. Interrupt Processing
System Reset and Initialization 2-11 System Resets, Interrupts, and Operating Modes Each individual peripheral interrupt is discussed in the associated peripheralmodule chapter in this manual. 2.2.3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interruptena...
Page 30 - Return From Interrupt; The interrupt handling routine terminates with the instruction:; (return from an interrupt service routine); Figure 2−8. Return From Interrupt; Interrupt Nesting
System Reset and Initialization 2-12 System Resets, Interrupts, and Operating Modes Return From Interrupt The interrupt handling routine terminates with the instruction: RETI (return from an interrupt service routine) The return from the interrupt takes 5 cycles to execute the following actionsand i...
Page 31 - Interrupt Vectors; Reset
System Reset and Initialization 2-13 System Resets, Interrupts, and Operating Modes 2.2.4 Interrupt Vectors The interrupt vectors and the power-up starting address are located in theaddress range 0FFFFh − 0FFE0h as described in Table 2−1. A vector isprogrammed by the user with the 16-bit address of ...
Page 32 - Operating Modes; The operating modes take into account three different needs:
Operating Modes 2-14 System Resets, Interrupts, and Operating Modes 2.3 Operating Modes The MSP430 family is designed for ultralow-power applications and usesdifferent operating modes shown in Figure 2−10. The operating modes take into account three different needs: - Ultralow-power - Speed and data...
Page 33 - Figure 2−10. MSP430x1xx Operating Modes For Basic Clock System; OSCOFF; Active
Operating Modes 2-15 System Resets, Interrupts, and Operating Modes Figure 2−10. MSP430x1xx Operating Modes For Basic Clock System Active Mode CPU Is Active Peripheral Modules Are Active LPM0 CPU Off, MCLK Off, SMCLK On, ACLK On CPUOFF = 1 SCG0 = 0SCG1 = 0 CPUOFF = 1 SCG0 = 1SCG1 = 0 LPM2 CPU Off, M...
Page 34 - Entering and Exiting Low-Power Modes; Enter interrupt service routine:; Extended Time in Low-Power Modes
Operating Modes 2-16 System Resets, Interrupts, and Operating Modes 2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-poweroperating modes. The program flow is: - Enter interrupt service routine: J The PC and SR are stored on the stack J The C...
Page 35 - Principles for Low; A typical with both a real-time clock function and; Connection of Unused Pins; The correct termination of all unused pins is listed in Table 2−2.; Table 2−2. Connection of Unused Pins
Principles for Low - Power Applications 2-17 System Resets, Interrupts, and Operating Modes 2.4 Principles for Low - Power Applications Often, the most important factor for reducing power consumption is using theMSP430’s clock system to maximize the time in LPM3. LPM3 powerconsumption is less than 2...
Page 37 - CPU Introduction; Chapter 3
3-1 RISC 16-Bit CPU ! This chapter describes the MSP430 CPU, addressing modes, and instructionset. Topic Page 3.1 CPU Introduction 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 CPU Registers 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . ....
Page 39 - Figure 3−1. CPU Block Diagram
CPU Introduction 3-3 RISC 16-Bit CPU Figure 3−1. CPU Block Diagram 0 15 MDB − Memory Data Bus Memory Address Bus − MAB 16 Zero, ZCarry, COverflow, VNegative, N 16−bit ALU dst src R8 General Purpose R9 General Purpose R10 General Purpose R11 General Purpose R12 General Purpose R13 General Purpose R14...
Page 40 - CPU Registers; Figure 3−2. Program Counter; MOV
CPU Registers 3-4 RISC 16-Bit CPU 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 havededicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to beexecuted. E...
Page 41 - Figure 3−4 shows stack usage.; Figure 3−3. Stack Pointer; Figure 3−4. Stack Usage
CPU Registers 3-5 RISC 16-Bit CPU 3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addressesof subroutine calls and interrupts. It uses a predecrement, postincrementscheme. In addition, the SP can be used by software with all instructions andaddressing modes....
Page 42 - Figure 3−6. Status Register Bits; Table 3−1 describes the status register bits.; Table 3−1. Description of Status Register Bits; Bit
CPU Registers 3-6 RISC 16-Bit CPU 3.2.3 Status Register (SR) The status register (SR/R2), used as a source or destination register, can beused in the register mode only addressed with word instructions. The remain-ing combinations of addressing modes are used to support the constant gen-erator. Figu...
Page 43 - Constant Generator Registers CG1 and CG2; Table 3−2. Values of Constant Generators CG1, CG2; Register; Register mode; The constant generator advantages are:; Constant Generator − Expanded Instruction Set
CPU Registers 3-7 RISC 16-Bit CPU 3.2.4 Constant Generator Registers CG1 and CG2 Six commonly-used constants are generated with the constant generatorregisters R2 and R3, without requiring an additional 16-bit word of programcode. The constants are selected with the source-register addressing modes(...
Page 44 - General−Purpose Registers R4 - R15
CPU Registers 3-8 RISC 16-Bit CPU 3.2.5 General−Purpose Registers R4 - R15 The twelve registers, R4−R15, are general-purpose registers. All of theseregisters can be used as data registers, address pointers, or index values andcan be accessed with byte or word instructions as shown in Figure 3−7. Fig...
Page 45 - Addressing Modes; Table 3−3. Source/Destination Operand Addressing Modes; Addressing Mode
Addressing Modes 3-9 RISC 16-Bit CPU 3.3 Addressing Modes Seven addressing modes for the source operand and four addressing modesfor the destination operand can address the complete address space with noexceptions. The bit numbers in Table 3−3 describe the contents of the As(source) and Ad (destinat...
Page 46 - Register Mode; The register mode is described in Table 3−4.; Table 3−4. Register Mode Description; Assembler Code; One or two words; PC; Data in Registers
Addressing Modes 3-10 RISC 16-Bit CPU 3.3.1 Register Mode The register mode is described in Table 3−4. Table 3−4. Register Mode Description Assembler Code Content of ROM MOV R10,R11 MOV R10,R11 Length: One or two words Operation: Move the content of R10 to R11. R10 is not affected. Comment: Valid fo...
Page 47 - Indexed Mode; The indexed mode is described in Table 3−5.; Table 3−5. Indexed Mode Description; Two or three words
Addressing Modes 3-11 RISC 16-Bit CPU 3.3.2 Indexed Mode The indexed mode is described in Table 3−5. Table 3−5. Indexed Mode Description Assembler Code Content of ROM MOV 2(R5),6(R6) MOV X(R5),Y(R6) X = 2 Y = 6 Length: Two or three words Operation: Move the contents of the source address (contents o...
Page 48 - Symbolic Mode; The symbolic mode is described in Table 3−6.; Table 3−6. Symbolic Mode Description
Addressing Modes 3-12 RISC 16-Bit CPU 3.3.3 Symbolic Mode The symbolic mode is described in Table 3−6. Table 3−6. Symbolic Mode Description Assembler Code Content of ROM MOV EDE,TONI MOV X(PC),Y(PC) X = EDE − PC Y = TONI − PC Length: Two or three words Operation: Move the contents of the source addr...
Page 49 - Absolute Mode; The absolute mode is described in Table 3−7.; Table 3−7. Absolute Mode Description
Addressing Modes 3-13 RISC 16-Bit CPU 3.3.4 Absolute Mode The absolute mode is described in Table 3−7. Table 3−7. Absolute Mode Description Assembler Code Content of ROM MOV &EDE,&TONI MOV X(0),Y(0) X = EDE Y = TONI Length: Two or three words Operation: Move the contents of the source addres...
Page 50 - Indirect Register Mode; The indirect register mode is described in Table 3−8.; Table 3−8. Indirect Mode Description
Addressing Modes 3-14 RISC 16-Bit CPU 3.3.5 Indirect Register Mode The indirect register mode is described in Table 3−8. Table 3−8. Indirect Mode Description Assembler Code Content of ROM MOV @R10,0(R11) MOV @R10,0(R11) Length: One or two words Operation: Move the contents of the source address (con...
Page 51 - Indirect Autoincrement Mode; The indirect autoincrement mode is described in Table 3−9.; Table 3−9. Indirect Autoincrement Mode Description; Figure 3−8. Operand Fetch Operation
Addressing Modes 3-15 RISC 16-Bit CPU 3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 3−9. Table 3−9. Indirect Autoincrement Mode Description Assembler Code Content of ROM MOV @R10+,0(R11) MOV @R10+,0(R11) Length: One or two words Operation: Move the contents ...
Page 52 - Immediate Mode; The immediate mode is described in Table 3−10.; Table 3−10. Immediate Mode Description; Valid only for a source operand.
Addressing Modes 3-16 RISC 16-Bit CPU 3.3.7 Immediate Mode The immediate mode is described in Table 3−10. Table 3−10. Immediate Mode Description Assembler Code Content of ROM MOV #45h,TONI MOV @PC+,X(PC) 45 X = TONI − PC Length: Two or three wordsIt is one word less if a constant of CG1 or CG2 can b...
Page 53 - Instruction Set; Destination Address
Instruction Set 3-17 RISC 16-Bit CPU 3.4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24emulated instructions. The core instructions are instructions that have uniqueop-codes decoded by the CPU. The emulated instructions are instructions thatmake code easi...
Page 54 - Figure 3−9. Double Operand Instruction Format; Table 3−11. Double Operand Instructions; Mnemonic; Instructions; CMP
Instruction Set 3-18 RISC 16-Bit CPU 3.4.1 Double-Operand (Format I) Instructions Figure 3−9 illustrates the double-operand instruction format. Figure 3−9. Double Operand Instruction Format B/W D-Reg 15 0 Op-code Ad S-Reg 8 7 14 13 12 11 10 9 6 5 4 3 2 1 As Table 3−11 lists and describes the double ...
Page 55 - Figure 3−10. Single Operand Instruction Format; Table 3−12. Single Operand Instructions; CALL
Instruction Set 3-19 RISC 16-Bit CPU 3.4.2 Single-Operand (Format II) Instructions Figure 3−10 illustrates the single-operand instruction format. Figure 3−10. Single Operand Instruction Format B/W D/S-Reg 15 0 Op-code 8 7 14 13 12 11 10 9 6 5 4 3 2 1 Ad Table 3−12 lists and describes the single oper...
Page 56 - Jumps; Figure 3−11 shows the conditional-jump instruction format.; Figure 3−11. Jump Instruction Format; Table 3−13 lists and describes the jump instructions.; Table 3−13. Jump Instructions
Instruction Set 3-20 RISC 16-Bit CPU 3.4.3 Jumps Figure 3−11 shows the conditional-jump instruction format. Figure 3−11. Jump Instruction Format C 10-Bit PC Offset 15 0 Op-code 8 7 14 13 12 11 10 9 6 5 4 3 2 1 Table 3−13 lists and describes the jump instructions. Table 3−13. Jump Instructions Mnemon...
Page 69 - Clear zero bit
Instruction Set 3-33 RISC 16−Bit CPU * CLRZ Clear zero bit Syntax CLRZ Operation 0 → Z or(.NOT.src .AND. dst −> dst) Emulation BIC #2,SR Description The constant 02h is inverted (0FFFDh) and logically ANDed with thedestination operand. The result is placed into the destination. The clear zerobit ...
Page 73 - Figure 3−12. Decrement Overlap; EDE
Instruction Set 3-37 RISC 16−Bit CPU * DEC[.W] Decrement destination * DEC.B Decrement destination Syntax DEC dst or DEC.W dst DEC.B dst Operation dst − 1 −> dst Emulation SUB #1,dst Emulation SUB.B #1,dst Description The destination operand is decremented by one. The original contents arelost. S...
Page 84 - Jump unconditionally; Syntax; JMP; Operation; Status bits are not affected.
Instruction Set 3-48 RISC 16−Bit CPU JMP Jump unconditionally Syntax JMP label Operation PC + 2 × offset −> PC Description The 10-bit signed offset contained in the instruction LSBs is added to theprogram counter. Status Bits Status bits are not affected. Hint: This one-word instruction replaces ...
Page 93 - Figure 3−13. Main Program Interrupt
Instruction Set 3-57 RISC 16−Bit CPU RETI Return from interrupt Syntax RETI Operation TOS → SR SP + 2 → SP TOS → PC SP + 2 → SP Description The status register is restored to the value at the beginning of the interruptservice routine by replacing the present SR contents with the TOS contents.The sta...
Page 94 - Figure 3−14. Destination Operand—Arithmetic Shift Left
Instruction Set 3-58 RISC 16−Bit CPU * RLA[.W] Rotate left arithmetically * RLA.B Rotate left arithmetically Syntax RLA dst or RLA.W dst RLA.B dst Operation C <− MSB <− MSB−1 .... LSB+1 <− LSB <− 0 Emulation ADD dst,dst ADD.B dst,dst Description The destination operand is shifted left on...
Page 95 - Figure 3−15. Destination Operand—Carry Left Shift
Instruction Set 3-59 RISC 16−Bit CPU * RLC[.W] Rotate left through carry * RLC.B Rotate left through carry Syntax RLC dst or RLC.W dst RLC.B dst Operation C <− MSB <− MSB−1 .... LSB+1 <− LSB <− C Emulation ADDC dst,dst Description The destination operand is shifted left one position as s...
Page 96 - Figure 3−16. Destination Operand—Arithmetic Right Shift
Instruction Set 3-60 RISC 16−Bit CPU RRA[.W] Rotate right arithmetically RRA.B Rotate right arithmetically Syntax RRA dst or RRA.W dst RRA.B dst Operation MSB −> MSB, MSB −> MSB−1, ... LSB+1 −> LSB, LSB −> C Description The destination operand is shifted right one position as shown in Fi...
Page 97 - Figure 3−17. Destination Operand—Carry Right Shift
Instruction Set 3-61 RISC 16−Bit CPU RRC[.W] Rotate right through carry RRC.B Rotate right through carry Syntax RRC dst or RRC.W dst RRC dst Operation C −> MSB −> MSB−1 .... LSB+1 −> LSB −> C Description The destination operand is shifted right one position as shown in Figure 3−17.The ca...
Page 100 - Set negative bit
Instruction Set 3-64 RISC 16−Bit CPU * SETN Set negative bit Syntax SETN Operation 1 −> N Emulation BIS #4,SR Description The negative bit (N) is set. Status Bits N: SetZ: Not affectedC: Not affectedV: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Page 101 - Set zero bit
Instruction Set 3-65 RISC 16−Bit CPU * SETZ Set zero bit Syntax SETZ Operation 1 −> Z Emulation BIS #2,SR Description The zero bit (Z) is set. Status Bits N: Not affectedZ: SetC: Not affectedV: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Page 104 - Figure 3−18. Destination Operand Byte Swap
Instruction Set 3-68 RISC 16−Bit CPU SWPB Swap bytes Syntax SWPB dst Operation Bits 15 to 8 <−> bits 7 to 0 Description The destination operand high and low bytes are exchanged as shown in Figure 3−18. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected...
Page 105 - Extend Sign; Figure 3−19. Destination Operand Sign Extension; SXT
Instruction Set 3-69 RISC 16−Bit CPU SXT Extend Sign Syntax SXT dst Operation Bit 7 −> Bit 8 ......... Bit 15 Description The sign of the low byte is extended into the high byte as shown in Figure 3−19. Status Bits N: Set if result is negative, reset if positiveZ: Set if result is zero, reset oth...
Page 108 - Instruction Cycles and Lengths; Table 3−14 lists the CPU cycles for interrupt overhead and reset.; Table 3−14. Interrupt and Reset Cycles; Return from interrupt (; Table 3−15. Format-II Instruction Cycles and Lengths; Rn; Instruction Format II Immediate Mode; Do not use instructions
Instruction Set 3-72 RISC 16−Bit CPU 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on theinstruction format and the addressing modes used - not the instruction itself.The number of clock cycles refers to the MCLK. Interrupt and Reset Cycles T...
Page 109 - Table 3−16. Format 1 Instruction Cycles and Lengths
Instruction Set 3-73 RISC 16−Bit CPU Format-I (Double Operand) Instruction Cycles and Lengths Table 3−16 lists the length and CPU cycles for all addressing modes of format-Iinstructions. Table 3−16. Format 1 Instruction Cycles and Lengths Addressing Mode No. of Cycles Length of Instruction Src Dst N...
Page 110 - Instruction Set Description; Figure 3−20. Core Instruction Map
Instruction Set 3-74 RISC 16−Bit CPU 3.4.5 Instruction Set Description The instruction map is shown in Figure 3−20 and the complete instruction setis summarized in Table 3−17. Figure 3−20. Core Instruction Map 0xxx4xxx8xxx Cxxx 1xxx 14xx18xx 1Cxx 20xx24xx28xx 2Cxx 30xx34xx38xx 3Cxx 4xxx5xxx6xxx7xxx8...
Page 113 - Basic Clock Module Introduction; Chapter 4
4-1 Basic Clock Module "# " The basic clock module provides the clocks for MSP430x1xx devices. Thischapter describes the operation of the basic clock module. The basic clockmodule is implemented in all MSP430x1xx devices. Topic Page 4.1 Basic Clock Module Introduction 4−2 . . . . . . . . . ....
Page 114 - The basic clock module includes two or three clock sources:
Basic Clock Module Introduction 4-2 Basic Clock Module 4.1 Basic Clock Module Introduction The basic clock module supports low system cost and ultralow-powerconsumption. Using three internal clock signals, the user can select the bestbalance of performance and low power consumption. The basic clock ...
Page 115 - Figure 4−1. Basic Clock Block Diagram; XT2 Oscillator
Basic Clock Module Introduction 4-3 Basic Clock Module Figure 4−1. Basic Clock Block Diagram Divider /1/2/4/8 DIVAx MCLK CPUOFF DCOCLK XIN XOUT DCOR P2.5/Rosc LFXT1 Oscillator XT2IN XT2OUT XT2OFF XT2 Oscillator Divider /1/2/4/8 DIVMx SMCLK SCG1 DIVSx ACLK VCC Main System Clock Auxillary Clock Sub Sy...
Page 116 - Basic Clock Module Operation; Set max DCO frequency; Basic Clock Module Features for Low-Power Applications; Low clock frequency for energy conservation and time keeping
Basic Clock Module Operation 4-4 Basic Clock Module 4.2 Basic Clock Module Operation After a PUC, MCLK and SMCLK are sourced from DCOCLK at ~800 kHz (seedevice-specific datasheet for parameters) and ACLK is sourced from LFXT1in LF mode. Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF con...
Page 117 - LFXT1 Oscillator; Figure 4−2. Off Signals for the LFXT1 Oscillator; LFXT1 Oscillator Characteristics; The LFXT1 oscillator in LF mode requires a 5.1-M; SS; when V
Basic Clock Module Operation 4-5 Basic Clock Module 4.2.2 LFXT1 Oscillator The LFXT1 oscillator supports ultralow-current consumption using a32,768-Hz watch crystal in LF mode (XTS = 0). A watch crystal connects to XINand XOUT without any other external components. Internal 12-pF loadcapacitors are ...
Page 118 - Figure 4−3. Off Signals for Oscillator XT2; Disabling the DCO
Basic Clock Module Operation 4-6 Basic Clock Module 4.2.3 XT2 Oscillator Some devices have a second crystal oscillator, XT2. XT2 sources XT2CLKand its characteristics are identical to LFXT1 in HF mode. The XT2OFF bitdisables the XT2 oscillator if XT2CLK is not used for MCLK or SMCLK asshown in Figur...
Page 119 - Adjusting the DCO frequency; s. The typical DCOx and RSELx ranges and; Figure 4−5. Typical DCOx Range and RSELx Steps
Basic Clock Module Operation 4-7 Basic Clock Module Adjusting the DCO frequency After a PUC, the internal resistor is selected for the DC generator, RSELx =4, and DCOx = 3, allowing the DCO to start at a mid-range frequency. MCLKand SMCLK are sourced from DCOCLK. Because the CPU executes codefrom MC...
Page 120 - Using an External Resistor (R; OSC; Figure 4−6. DCO Frequency vs. Temperature
Basic Clock Module Operation 4-8 Basic Clock Module Using an External Resistor (R OSC ) for the DCO The DCO temperature coefficient can be reduced by using an external resistorR OSC tied to DV CC to source the current for the DC generator. Figure 4−6 shows the typical relationship of f DCO vs. tempe...
Page 121 - DCO Modulator; DCO; Figure 4−7. Modulator Patterns
Basic Clock Module Operation 4-9 Basic Clock Module 4.2.5 DCO Modulator The modulator mixes two DCO frequencies, f DCO and f DCO+1 to produce an intermediate effective frequency between f DCO and f DCO+1 and spread the clock energy, reducing electromagnetic interference (EMI) . The modulator mixes f...
Page 122 - Basic Clock Module Fail-Safe Operation; s. When an oscillator; No Oscillator Fault Detection for LFXT1 in LF Mode; s after the
Basic Clock Module Operation 4-10 Basic Clock Module 4.2.6 Basic Clock Module Fail-Safe Operation The basic clock module incorporates an oscillator-fault detection fail-safefeature. The oscillator fault detector is an analog circuit that monitors theLFXT1CLK (in HF mode) and the XT2CLK. An oscillato...
Page 123 - Oscillator Fault Detection
Basic Clock Module Operation 4-11 Basic Clock Module Oscillator Fault Detection Signal XT_OscFault triggers the OFIFG flag as shown in Figure 4−10. TheLFXT1_OscFault signal is low when LFXT1 is in LF mode. On devices without XT2, the OFIFG flag cannot be cleared when LFXT1 is inLF mode. MCLK may be ...
Page 124 - Sourcing MCLK from a Crystal; ) Switch on the crystal oscillator; BIC
Basic Clock Module Operation 4-12 Basic Clock Module Sourcing MCLK from a Crystal After a PUC, the basic clock module uses DCOCLK for MCLK. If required,MCLK may be sourced from LFXT1 or XT2. The sequence to switch the MCLK source from the DCO clock to the crystalclock (LFXT1CLK or XT2CLK) is: 1) Swi...
Page 125 - Synchronization of Clock Signals; ) The current clock cycle continues until the next rising edge.; Figure 4−11. Switch MCLK from DCOCLK to LFXT1CLK
Basic Clock Module Operation 4-13 Basic Clock Module 4.2.7 Synchronization of Clock Signals When switching MCLK or SMCLK from one clock source to the another, theswitch is synchronized to avoid critical race conditions as shown inFigure 4−11: 1) The current clock cycle continues until the next risin...
Page 126 - Basic Clock Module Registers; The basic clock module registers are listed in Table 4−1:; Table 4−1. Basic Clock Module Registers
Basic Clock Module Registers 4-14 Basic Clock Module 4.3 Basic Clock Module Registers The basic clock module registers are listed in Table 4−1: Table 4−1. Basic Clock Module Registers Register Short Form Register Type Address Initial State DCO control register DCOCTL Read/write 056 h 060 h with PUC ...
Page 127 - DCOCTL, DCO Control Register; DCOx; BCSCTL1, Basic Clock System Control Register 1
Basic Clock Module Registers 4-15 Basic Clock Module DCOCTL, DCO Control Register 7 6 5 4 3 2 1 0 DCOx MODx rw−0 rw−1 rw−1 rw−0 rw−0 rw−0 rw−0 rw−0 DCOx Bits7-5 DCO frequency select. These bits select which of the eight discrete DCOfrequencies of the RSELx setting is selected. MODx Bits4-0 Modulator...
Page 128 - BCSCTL2, Basic Clock System Control Register 2; SELMx
Basic Clock Module Registers 4-16 Basic Clock Module BCSCTL2, Basic Clock System Control Register 2 7 6 5 4 3 2 1 0 SELMx DIVMx SELS DIVSx DCOR rw−(0) rw−(0) rw−(0) rw−(0) rw−0 rw−0 rw−0 rw−0 SELMx Bits7-6 Select MCLK. These bits select the MCLK source.00 DCOCLK 01 DCOCLK 10 XT2CLK when XT2 oscillat...
Page 129 - IE1, Interrupt Enable Register 1; OFIE; IFG1, Interrupt Flag Register 1
Basic Clock Module Registers 4-17 Basic Clock Module IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 OFIE rw−0 Bits7-2 These bits may be used by other modules. See device-specific datasheet. OFIE Bit 1 Oscillator fault interrupt enable. This bit enables the OFIFG interrupt.Because other bits in IE1...
Page 131 - Flash Memory Controller; Flash Memory Introduction; Chapter 5
5-1 Flash Memory Controller " "" This chapter describes the operation of the MSP430 flash memory controller. Topic Page 5.1 Flash Memory Introduction 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Flash Memory Segmentation 5-3 . . . . . . . . . . . . . . ...
Page 132 - Minimum V; During Flash Write or Erase; Figure 5−1. Flash Memory Module Block Diagram
Flash Memory Introduction 5-2 Flash Memory Controller 5.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable andprogrammable. The flash memory module has an integrated controller thatcontrols programming and erase operations. The controller has threeregisters, a t...
Page 133 - Flash Memory Segmentation
Flash Memory Segmentation 5-3 Flash Memory Controller 5.2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments. Single bits, bytes, orwords can be written to flash memory, but the segment is the smallest size offlash memory that can be erased. The flash memory is partitioned in...
Page 134 - Flash Memory Operation; Block write; Flash Memory Timing Generator; Figure 5−3. Flash Memory Timing Generator Block Diagram; FTG; frequency deviates from the
Flash Memory Operation 5-4 Flash Memory Controller 5.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flashmemory is not being erased or written, the flash timing generator and voltagegenerator are off, and the memory operates identically to ROM. MSP430 f...
Page 135 - Erasing Flash Memory; Table 5−1. Erase Modes; MERAS; Segment erase; Figure 5−4. Erase Cycle Timing; BUSY
Flash Memory Operation 5-5 Flash Memory Controller 5.3.2 Erasing Flash Memory The erased level of a flash memory bit is 1. Each bit can be programmed from1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. Thesmallest amount of flash that can be erased is a segment. There are t...
Page 136 - Initiating an Erase from Within Flash Memory; The flow to initiate an erase from flash is shown in Figure 5−5.; Figure 5−5. Erase Cycle from Within Flash Memory; Setup flash controller and erase
Flash Memory Operation 5-6 Flash Memory Controller Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM. Whena flash segment erase operation is initiated from within flash memory, all timingis controlled by the flash controller, and the C...
Page 137 - Initiating an Erase from RAM; Figure 5−6. Erase Cycle from Within RAM
Flash Memory Operation 5-7 Flash Memory Controller Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not heldand can continue to execute code from RAM. The BUSY bit must be polled todetermine the end of the erase cycle before the CPU can access any flas...
Page 138 - Writing Flash Memory; Table 5−2. Write Modes; BLKWRT
Flash Memory Operation 5-8 Flash Memory Controller 5.3.3 Writing Flash Memory The write modes, selected by the WRT and BLKWRT bits, are listed inTable 5−1. Table 5−2. Write Modes BLKWRT WRT Write Mode 0 1 Byte/word write 1 1 Block write Both write modes use a sequence of individual write instruction...
Page 139 - cycles. With each byte or word write, the amount of time the block is; Initiating a Byte/Word Write from Within Flash Memory; Figure 5−8. Initiating a Byte/Word Write from Flash; Setup flash controller
Flash Memory Operation 5-9 Flash Memory Controller In byte/word mode, the internally-generated programming voltage is appliedto the complete 64-byte block, each time a byte or word is written, for 32 of the35 f FTG cycles. With each byte or word write, the amount of time the block is subjected to th...
Page 140 - Initiating a Byte/Word Write from RAM; The flow to initiate a byte/word write from RAM is shown in Figure 5−9.; Figure 5−9. Initiating a Byte/Word Write from RAM
Flash Memory Operation 5-10 Flash Memory Controller Initiating a Byte/Word Write from RAM The flow to initiate a byte/word write from RAM is shown in Figure 5−9. Figure 5−9. Initiating a Byte/Word Write from RAM yes BUSY = 1 yes BUSY = 1 Disable all interrupts and watchdog Setup flash controller and...
Page 141 - Block Write; CPT; must not be exceeded for any block during; End
Flash Memory Operation 5-11 Flash Memory Controller Block Write The block write can be used to accelerate the flash write process when manysequential bytes or words need to be programmed. The flash programmingvoltage remains on for the duration of writing the 64-byte block. Thecumulative programming...
Page 142 - Block Write Flow and Example; A block write flow is shown in Figure 5−8 and the following example.; Figure 5−11. Block Write Flow
Flash Memory Operation 5-12 Flash Memory Controller Block Write Flow and Example A block write flow is shown in Figure 5−8 and the following example. Figure 5−11. Block Write Flow yes BUSY = 1 Disable all interrupts and watchdog Setup flash controller Set BLKWRT=WRT=1 Write byte or word no Block Bor...
Page 144 - Flash Memory Access During Write or Erase; JMP PC; JMP PC
Flash Memory Operation 5-14 Flash Memory Controller 5.3.4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and whileBUSY=1, the CPU may not read or write to or from any flash location.Otherwise, an access violation occurs, ACCVIFG is set, and the ...
Page 145 - Stopping a Write or Erase Cycle; Any write to FCTL2 when the BUSY=1 is an access violation.; Flash Memory Controller Interrupts; Program via JTAG
Flash Memory Operation 5-15 Flash Memory Controller 5.3.5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion bysetting the emergency exit bit EMEX. Setting the EMEX bit stops the activeoperation immediately and stops the flash controller. All fla...
Page 146 - Programming Flash Memory via JTAG; Programming Flash Memory via the Bootstrap loader (BSL); Figure 5−12. User-Developed Programming Solution
Flash Memory Operation 5-16 Flash Memory Controller Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port. The JTAG interfacerequires four signals (5 signals on 20- and 28-pin devices), ground andoptionally V CC and RST/NMI. The JTAG port is protected with a fuse. Blow...
Page 147 - Flash Memory Registers; The flash memory registers are listed in Table 5−4.; Table 5−4. Flash Memory Registers; Flash memory control register 1
Flash Memory Registers 5-17 Flash Memory Controller 5.4 Flash Memory Registers The flash memory registers are listed in Table 5−4. Table 5−4. Flash Memory Registers Register Short Form Register Type Address Initial State Flash memory control register 1 FCTL1 Read/write 0128h 09600h with PUC Flash me...
Page 148 - FCTL1, Flash Memory Control Register; Block-write mode is off; No erase
Flash Memory Registers 5-18 Flash Memory Controller FCTL1, Flash Memory Control Register 15 14 13 12 11 10 9 8 FRKEY, Read as 096h FWKEY, Must be written as 0A5h 7 6 5 4 3 2 1 0 BLKWRT WRT Reserved Reserved Reserved MERAS ERASE Reserved rw−0 rw−0 r0 r0 r0 rw−0 rw−0 r0 FRKEY/FWKEY Bits15-8 FCTLx pass...
Page 149 - FCTL2, Flash Memory Control Register; FWKEYx; FNx
Flash Memory Registers 5-19 Flash Memory Controller FCTL2, Flash Memory Control Register 15 14 13 12 11 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 FSSELx FNx rw−0 rw−1 rw-0 rw-0 rw-0 rw−0 rw-1 rw−0 FWKEYx Bits15-8 FCTLx password. Always read as 096h. Must be written as 0A5h ...
Page 150 - FCTL3, Flash Memory Control Register FCTL3
Flash Memory Registers 5-20 Flash Memory Controller FCTL3, Flash Memory Control Register FCTL3 15 14 13 12 11 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 Reserved Reserved EMEX LOCK WAIT ACCVIFG KEYV BUSY r0 r0 rw-0 rw-1 r-1 rw−0 rw-(0) r(w)−0 FWKEYx Bits15-8 FCTLx password. ...
Page 151 - ACCVIE; or
Flash Memory Registers 5-21 Flash Memory Controller IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 ACCVIE rw−0 Bits7-6,4-0 These bits may be used by other modules. See device-specific datasheet. ACCVIE Bit 5 Flash memory access violation interrupt enable. This bit enables theACCVIFG interrupt. Bec...
Page 153 - SVS Introduction; Chapter 6
6-1 Supply Voltage Supervisor " $" % This chapter describes the operation of the SVS. The SVS is implemented inMSP430x15x and MSP430x16x devices. Topic Page 6.1 SVS Introduction 6−2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 SVS Operation ...
Page 155 - Figure 6−1. SVS Block Diagram
SVS Introduction 6-3 Supply Voltage Supervisor Figure 6−1. SVS Block Diagram + − 1.25V Brownout Reset VCC Set SVSFG tReset ~ 50us Reset SVSCTL Bits 0001 0010 0011 1111 1101 1100 G D S SVSOUT G D S VLD SVSON PORON SVSOP SVSFG ~ 50us SVS_POR SVSIN AVCC AVCC
Page 156 - SVS Operation; Configuring the SVS
SVS Operation 6-4 Supply Voltage Supervisor 6.2 SVS Operation The SVS detects if the AV CC voltage drops below a selectable level. It can be configured to provide a POR or set a flag, when a low-voltage condition occurs.The SVS is disabled after a brownout reset to conserve current consumption. 6.2....
Page 157 - Changing the VLDx Bits; Figure 6−2. SVSON state When Changing VLDx; settle
SVS Operation 6-5 Supply Voltage Supervisor 6.2.3 Changing the VLDx Bits When the VLDx bits are changed, two settling delays are implemented toallows the SVS circuitry to settle. During each delay, the SVS will not setSVSFG. The delays, t d(SVSon) and t settle, are shown in Figure 6−2. The t d(SVSon...
Page 158 - SVS Operating Range; is close to the threshold. The SVS operation and; Figure 6−3. Operating Levels for SVS and Brownout/Reset Circuit
SVS Operation 6-6 Supply Voltage Supervisor 6.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltagechanges when AV CC is close to the threshold. The SVS operation and SVS/Brownout interoperation are shown in Figure 6−3. Figure 6−3. Operating Levels for S...
Page 159 - SVS Registers; Table 6−1. SVS Registers; SVS Control Register; SVSCTL, SVS Control Register
SVS Registers 6-7 Supply Voltage Supervisor 6.3 SVS Registers The SVS registers are listed in Table 6−1. Table 6−1. SVS Registers Register Short Form Register Type Address Initial State SVS Control Register SVSCTL Read/write 055h Reset with BOR SVSCTL, SVS Control Register 7 6 5 4 3 2 1 0 VLDx PORON...
Page 161 - Hardware Multiplier; Hardware Multiplier Introduction; Chapter 7
7-1 Hardware Multiplier &'"" This chapter describes the hardware multiplier. The hardware multiplier isimplemented in MSP430x14x and MSP430x16x devices. Topic Page 7.1 Hardware Multiplier Introduction 7-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Hardware Multipli...
Page 162 - Hardware Multiplier Introduction; Figure 7−1. Hardware Multiplier Block Diagram
Hardware Multiplier Introduction 7-2 Hardware Multiplier 7.1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU.This means, its activities do not interfere with the CPU activities. The multiplierregisters are peripheral registers that are loade...
Page 163 - Hardware Multiplier Operation; NOP; Operand Registers; Table 7−1. OP1 addresses; OP1 Address
Hardware Multiplier Operation 7-3 Hardware Multiplier 7.2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply, signed multiply, unsignedmultiply accumulate, and signed multiply accumulate operations. The type ofoperation is selected by the address the first operand is wr...
Page 164 - Result Registers; Table 7−2. RESHI Contents; Table 7−3. SUMEXT Contents; Mode; No carry for result; MACS Underflow and Overflow
Hardware Multiplier Operation 7-4 Hardware Multiplier 7.2.2 Result Registers The result low register RESLO holds the lower 16-bits of the calculation result.The result high register RESHI contents depend on the multiply operation andare listed in Table 7−2. Table 7−2. RESHI Contents Mode RESHI Conte...
Page 165 - Software Examples
Hardware Multiplier Operation 7-5 Hardware Multiplier 7.2.3 Software Examples Examples for all multiplier modes follow. All 8x8 modes use the absoluteaddress for the registers because the assembler will not allow .B access toword registers when using the labels from the standard definitions file. ; ...
Page 166 - Indirect Addressing of RESLO
Hardware Multiplier Operation 7-6 Hardware Multiplier 7.2.4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access theresult registers, At least one instruction is needed between loading the secondoperand and accessing one of the result registers: ; Acce...
Page 167 - Hardware Multiplier Registers; The hardware multiplier registers are listed in Table 7−4.; Table 7−4. Hardware Multiplier Registers
Hardware Multiplier Registers 7-7 Hardware Multiplier 7.3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 7−4. Table 7−4. Hardware Multiplier Registers Register Short Form Register Type Address Initial State Operand one - multiply MPY Read/write 0130h Unchanged Op...
Page 169 - DMA Introduction; Chapter 8
8-1 () "" The DMA controller module transfers data from one address to anotherwithout CPU intervention. This chapter describes the operation of the DMAcontroller. The DMA controller is implemented in MSP430x15x andMSP430x16x devices. Topic Page 8.1 DMA Introduction 8-2 . . . . . . . . . . . ...
Page 171 - Figure 8−1. DMA Controller Block Diagram
8-3 Figure 8−1. DMA Controller Block Diagram DMA Priority And Control ENNMI DT DMA Channel 2 DMASRSBYTE DMA2SZ DMA2DA DMA2SA DMADSTBYTE DMASRCINCRx DMADSTINCRx 2 2 3 DMADTx DMAEN DT DMA Channel 1 DMASRSBYTE DMA1SZ DMA1DA DMA1SA DMADSTBYTE DMASRCINCRx DMADSTINCRx 2 2 3 DMADTx DMAEN DT DMA Channel 0 D...
Page 172 - DMA Operation; DMA Addressing Modes; Fixed address to fixed address; Figure 8−2. DMA Addressing Modes
8-4 8.2 DMA Operation The DMA controller is configured with user software. The setup and operationof the DMA is discussed in the following sections. 8.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode foreach DMA channel is independently configurable. For exa...
Page 173 - DMA Transfer Modes; Table 8−1. DMA Transfer Modes; DMADTx; Single transfer
8-5 8.2.2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits aslisted in Table 8−1. Each channel is individually configurable for its transfermode. For example, channel 0 may be configured in single transfer mode,while channel 1 is configured for burst-block tra...
Page 174 - Single Transfer
8-6 Single Transfer In single transfer mode, each byte/word transfer requires a separate trigger.The single transfer state diagram is shown in Figure 8−3. The DMAxSZ register is used to define the number of transfers to be made.The DMADSTINCRx and DMASRCINCRx bits select if the destinationaddress an...
Page 175 - Figure 8−3. DMA Single Transfer State Diagram
8-7 Figure 8−3. DMA Single Transfer State Diagram Reset Wait for Trigger Idle Hold CPU, Transfer one word/byte [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] DMAABORT=0 DMAABORT = 1 2 x MCLK DMAEN = 0 Modify T_SourceAdd Modify T_DestAdd Decrement DMAxSZ [ENNMI = 1 AND NMI event] OR [DMAL...
Page 176 - Block Transfers
8-8 Block Transfers In block transfer mode, a transfer of a complete block of data occurs after onetrigger. When DMADTx = 1, the DMAEN bit is cleared after the completion ofthe block transfer and must be set again before another block transfer can betriggered. After a block transfer has been trigger...
Page 177 - Figure 8−4. DMA Block Transfer State Diagram
8-9 Figure 8−4. DMA Block Transfer State Diagram Reset Wait for Trigger Idle Hold CPU, Transfer one word/byte [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] DMAABORT=0 DMAABORT = 1 2 x MCLK DMAEN = 0 Modify T_SourceAdd Modify T_DestAdd Decrement DMAxSZ DMAxSZ > 0 [ENNMI = 1 AND NMI ev...
Page 178 - Burst-Block Transfers
8-10 Burst-Block Transfers In burst-block mode, transfers are block transfers with CPU activityinterleaved. The CPU executes 2 MCLK cycles after every four byte/wordtransfers of the block resulting in 20% CPU execution capacity. After theburst-block, CPU execution resumes at 100% capacity and the DM...
Page 179 - Figure 8−5. DMA Burst-Block Transfer State Diagram
8-11 Figure 8−5. DMA Burst-Block Transfer State Diagram 2 x MCLK Reset Wait for Trigger Idle Hold CPU, Transfer one word/byte Burst State (release CPU for 2xMCLK) [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] DMAABORT=0 DMAABORT = 1 2 x MCLK DMAEN = 0 Modify T_SourceAdd Modify T_DestAdd...
Page 180 - Note: DMAONFETCH Must Be Used When The DMA Writes To Flash
8-12 8.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with theDMAxTSELx bits as described in Table 8−2.The DMAxTSELx bits should bemodified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictableDMA triggers may occur. When selecting the trigg...
Page 181 - Table 8−2. DMA Trigger Operation; DMAxTSELx Operation; A transfer is triggered when USART0 receives new data. In I; URXIFG1 flag will not trigger a transfer.; No transfer is triggered.
8-13 Table 8−2. DMA Trigger Operation DMAxTSELx Operation 0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically resetwhen the transfer starts 0001 A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag isautomatically reset when the transf...
Page 182 - Stopping DMA Transfers; There are two ways to stop DMA transfers in progress:; DMA Channel Priorities; DMA Priority
8-14 8.2.4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress: - A single, block, or burst-block transfer may be stopped with an NMIinterrupt, if the ENNMI bit is set in register DMACTL1. - A burst-block transfer may be stopped by clearing the DMAEN bit. 8.2.5 DMA Channel Pr...
Page 183 - DMA Transfer Cycle Time; Table 8−3. Maximum Single-Transfer DMA Cycle Time; CPU Operating Mode
8-15 8.2.6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronizebefore each single transfer or complete block or burst-block transfer. Eachbyte/word transfer requires two MCLK cycles after synchronization, and onecycle of wait time after the transfer. Becaus...
Page 186 - DMA Registers; The DMA registers are listed in Table 8−4:; Table 8−4. DMA Registers
8-18 8.3 DMA Registers The DMA registers are listed in Table 8−4: Table 8−4. DMA Registers Register Short Form Register Type Address Initial State DMA control 0 DMACTL0 Read/write 0122h Reset with POR DMA control 1 DMACTL1 Read/write 0124h Reset with POR DMA channel 0 control DMA0CTL Read/write 01E0...
Page 187 - DMACTL0, DMA Control Register 0; Reserved; Reserved
8-19 DMACTL0, DMA Control Register 0 15 14 13 12 11 10 9 8 Reserved DMA2TSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 DMA1TSELx DMA0TSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Reserved Bits15−12 Reserved DMA2TSELx Bits11−8 DMA trigger select. These b...
Page 188 - DMACTL1, DMA Control Register 1; The DMA transfer occurs immediately; ENNMI; NMI interrupt does not interrupt DMA transfer
8-20 DMACTL1, DMA Control Register 1 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 0 0 DMA ONFETCH ROUND ROBIN ENNMI r0 r0 r0 r0 r0 rw−(0) rw−(0) rw−(0) Reserved Bits15−3 Reserved. Read only. Always read as 0. DMAONFETCH Bit 2 DMA on fetch0 The DMA transfer occu...
Page 189 - DMAxCTL, DMA Channel x Control Register
8-21 DMAxCTL, DMA Channel x Control Register 15 14 13 12 11 10 9 8 Reserved DMADTx DMADSTINCRx DMASRCINCRx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 DMA DSTBYTE DMA SRCBYTE DMALEVEL DMAEN DMAIFG DMAIE DMA ABORT DMAREQ rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−...
Page 190 - DMAxSA, DMA Source Address Register; DMAxSAx
8-22 DMASRCBYTE Bit 6 DMA source byte. This bit selects the source as a byte or word.0 Word 1 Byte DMALEVEL Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitivetriggers.0 Edge sensitive (rising edge) 1 Level sensitive (high level) DMAEN Bit 4 DMA enable0 Disabled 1 Enabled DM...
Page 191 - DMAxDA, DMA Destination Address Register; DMAxDAx; DMAxSZ, DMA Size Address Register; Transfer is disabled
8-23 DMAxDA, DMA Destination Address Register 15 14 13 12 11 10 9 8 DMAxDAx rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DMAxDAx rw rw rw rw rw rw rw rw DMAxDAx Bits15−0 DMA destination address. The destination address register points to thedestination address for single transfers or the first address fo...
Page 193 - Digital I/O Introduction; Chapter 9
9-1 Digital I/O ("* This chapter describes the operation of the digital I/O ports. Ports P1-P2 areimplemented in MSP430x11xx devices. Ports P1-P3 are implemented inMSP430x12xx devices. Ports P1-P6 are implemented in MSP430x13x,MSP430x14x, MSP430x15x, and MSP430x16x devices. Topic Page 9.1 Digita...
Page 194 - Independently programmable individual I/Os
Digital I/O Introduction 9-2 Digital I/O 9.1 Digital I/O Introduction MSP430 devices have up to 6 digital I/O ports implemented, P1 - P6. Each porthas eight I/O pins. Every I/O pin is individually configurable for input or outputdirection, and each I/O line can be individually read or written to. Po...
Page 195 - Digital I/O Operation; Input Register PxIN; Writing to Read-Only Registers PxIN; Output Registers PxOUT; Bit = 0: The port pin is switched to input direction
Digital I/O Operation 9-3 Digital I/O 9.2 Digital I/O Operation The digital I/O is configured with user software. The setup and operation of thedigital I/O is discussed in the following sections. 9.2.1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at theco...
Page 196 - Function Select Registers PxSEL; Bit = 1: Peripheral module function is selected for the pin; Select ACLK function for pin; P1 and P2 Interrupts Are Disabled When PxSEL = 1
Digital I/O Operation 9-4 Digital I/O 9.2.4 Function Select Registers PxSEL Port pins are often multiplexed with other peripheral module functions. See thedevice-specific data sheet to determine pin functions. Each PxSEL bit is usedto select the pin function − I/O port or peripheral module function....
Page 197 - P1 and P2 Interrupts; PxIFG Flags When Changing PxOUT or PxDIR
Digital I/O Operation 9-5 Digital I/O 9.2.5 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability, configured with thePxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector,and all P2 pins source a different single interrupt vector. The PxIFG registercan ...
Page 198 - Interrupt Edge Select Registers P1IES, P2IES; Writing to PxIESx; May be set; Interrupt Enable P1IE, P2IE; Each PxIE bit enables the associated PxIFG interrupt flag.; Configuring Unused Port Pins
Digital I/O Operation 9-6 Digital I/O Interrupt Edge Select Registers P1IES, P2IES Each PxIES bit selects the interrupt edge for the corresponding I/O pin. Bit = 0: The PxIFGx flag is set with a low-to-high transition Bit = 1: The PxIFGx flag is set with a high-to-low transition Note: Writing to PxI...
Page 199 - Digital I/O Registers
Digital I/O Registers 9-7 Digital I/O 9.3 Digital I/O Registers Seven registers are used to configure P1 and P2. Four registers are used toconfigure ports P3 - P6. The digital I/O registers are listed in Table 9−1. Table 9−1. Digital I/O Registers Port Register Short Form Address Register Type Initi...
Page 201 - Watchdog Timer; Watchdog Timer Introduction
10-1 Watchdog Timer + The watchdog timer is a 16-bit timer that can be used as a watchdog or as aninterval timer. This chapter describes the watchdog timer. The watchdog timeris implemented in all MSP430x1xx devices. Topic Page 10.1 Watchdog Timer Introduction 10-2 . . . . . . . . . . . . . . . . . ...
Page 202 - Watchdog Timer Powers Up Active
Watchdog Timer Introduction 10-2 Watchdog Timer 10.1 Watchdog Timer Introduction The primary function of the watchdog timer (WDT) module is to perform acontrolled system restart after a software problem occurs. If the selected timeinterval expires, a system reset is generated. If the watchdog functi...
Page 203 - Figure 10−1. Watchdog Timer Block Diagram
Watchdog Timer Introduction 10-3 Watchdog Timer Figure 10−1. Watchdog Timer Block Diagram WDTQn Y 1 2 3 4 Q6 Q9 Q13 Q15 16−bit Counter CLK AB 1 1 A EN PUC SMCLK ACLK Clear Password Compare 0 0 0 0 1 1 1 1 WDTCNTCL WDTTMSEL WDTNMI WDTNMIES WDTIS1 WDTSSEL WDTIS0 WDTHOLD EQU EQU Write Enable Low Byte R...
Page 204 - Watchdog Timer Operation; Modifying the Watchdog Timer
Watchdog Timer Operation 10-4 Watchdog Timer 10.2 Watchdog Timer Operation The WDT module can be configured as either a watchdog or interval timer withthe WDTCTL register. The WDTCTL register also contains control bits toconfigure the RST/NMI pin. WDTCTL is a 16-bit, password-protected,read/write re...
Page 205 - The WDT uses two bits in the SFRs for interrupt control.
Watchdog Timer Operation 10-5 Watchdog Timer 10.2.4 Watchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control. - The WDT interrupt flag, WDTIFG, located in IFG1.0 - The WDT interrupt enable, WDTIE, located in IE1.0 When using the WDT in the watchdog mode, the WDTIFG flag sour...
Page 206 - Periodically clear an active watchdog
Watchdog Timer Operation 10-6 Watchdog Timer 10.2.5 Operation in Low-Power Modes The MSP430 devices have several low-power modes. Different clock signalsare available in different low-power modes. The requirements of the user’sapplication and the type of clocking used determine how the WDT should be...
Page 207 - Watchdog Timer Registers; The watchdog timer module registers are listed in Table 10−1.; Table 10−1. Watchdog Timer Registers
Watchdog Timer Registers 10-7 Watchdog Timer 10.3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 10−1. Table 10−1. Watchdog Timer Registers Register Short Form Register Type Address Initial State Watchdog timer control register WDTCTL Read/write 0120h 06900h with PU...
Page 208 - WDTCTL, Watchdog Timer Register
Watchdog Timer Registers 10-8 Watchdog Timer WDTCTL, Watchdog Timer Register 15 14 13 12 11 10 9 8 Read as 069h WDTPW, must be written as 05Ah 7 6 5 4 3 2 1 0 WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx rw−0 rw−0 rw−0 rw−0 r0(w) rw−0 rw−0 rw−0 WDTPW Bits15-8 Watchdog timer password. Alw...
Page 209 - NMIIE
Watchdog Timer Registers 10-9 Watchdog Timer IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 NMIIE WDTIE rw−0 rw−0 Bits7-5 These bits may be used by other modules. See device-specific datasheet. NMIIE Bit 4 NMI interrupt enable. This bit enables the NMI interrupt. Because other bitsin IE1 may be us...
Page 210 - NMIIFG
Watchdog Timer Registers 10-10 Watchdog Timer IFG1, Interrupt Flag Register 1 7 6 5 4 3 2 1 0 NMIIFG WDTIFG rw−(0) rw−(0) Bits7-5 These bits may be used by other modules. See device-specific datasheet. NMIIFG Bit 4 NMI interrupt flag. NMIIFG must be reset by software. Because other bits inIFG1 may b...
Page 212 - Use of the Word Count
Timer_A Introduction 11-2 Timer_A 11.1 Timer_A Introduction Timer_A is a 16-bit timer/counter with three capture/compare registers.Timer_A can support multiple capture/compares, PWM outputs, and intervaltiming. Timer_A also has extensive interrupt capabilities. Interrupts may begenerated from the co...
Page 214 - Modifying Timer_A Registers; Clock Source Select and Divider
Timer_A Operation 11-4 Timer_A 11.2 Timer_A Operation The Timer_A module is configured with user software. The setup andoperation of Timer_A is discussed in the following sections. 11.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TAR, increments or decrements (dependingon mode of opera...
Page 215 - Table 11−1. Timer Modes; MCx; Stop
Timer_A Operation 11-5 Timer_A 11.2.2 Starting the Timer The timer may be started, or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stoppedby writing 0 to TACCR0. The timer may then ...
Page 216 - Up Mode; Figure 11−3. Up Mode Flag Setting; Changing the Period Register TACCR0
Timer_A Operation 11-6 Timer_A Up Mode The up mode is used if the timer period must be different from 0FFFFh counts.The timer repeatedly counts up to the value of compare register TACCR0,which defines the period, as shown in Figure 11−2. The number of timer countsin the period is TACCR0+1. When the ...
Page 217 - Continuous Mode; Figure 11−4. Continuous Mode
Timer_A Operation 11-7 Timer_A Continuous Mode In the continuous mode, the timer repeatedly counts up to 0FFFFh and restartsfrom zero as shown in Figure 11−4. The capture/compare register TACCR0works the same way as the other capture/compare registers. Figure 11−4. Continuous Mode 0h 0FFFFh The TAIF...
Page 218 - Use of the Continuous Mode; and; Figure 11−6. Continuous Mode Time Intervals; is greater than the TACCR0
Timer_A Operation 11-8 Timer_A Use of the Continuous Mode The continuous mode can be used to generate independent time intervals andoutput frequencies. Each time an interval is completed, an interrupt isgenerated. The next time interval is added to the TACCRx register in theinterrupt service routine...
Page 220 - Use of the Up/Down Mode; dead; Time during which both outputs need to be inactive; timer; Cycle time of the timer clock
Timer_A Operation 11-10 Timer_A Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, and counting in the downdirection, the timer continues its descent until it reaches zero. The new periodtakes affect after the counter counts down to zero. When the timer is counting ...
Page 221 - Capture Mode; The timer value is copied into the TACCRx register
Timer_A Operation 11-11 Timer_A 11.2.4 Capture/Compare Blocks Three identical capture/compare blocks, TACCRx, are present in Timer_A.Any of the blocks may be used to capture the timer data, or to generate timeintervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is used to ...
Page 222 - Figure 11−11. Capture Cycle; Capture Initiated by Software; Compare Mode; Interrupt flag CCIFG is set
Timer_A Operation 11-12 Timer_A Figure 11−11. Capture Cycle Second Capture Taken COV = 1 Capture Taken No Capture Taken Read Taken Capture Clear Bit COV in Register TACCTLx Idle Idle Capture Capture Read and No Capture Capture Capture Read Capture Capture Initiated by Software Captures can be initia...
Page 223 - Output Modes; Table 11−2. Output Modes; OUTMODx; Output
Timer_A Operation 11-13 Timer_A 11.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is usedto generate output signals such as PWM signals. Each output unit has eightoperating modes that generate signals based on the EQU0 and EQUx signals. Output Modes The output mo...
Page 224 - Output Example—Timer in Up Mode; Figure 11−12.Output Example—Timer in Up Mode
Timer_A Operation 11-14 Timer_A Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value,and rolls from TACCR0 to zero, depending on the output mode. An exampleis shown in Figure 11−12 using TACCR0 and TACCR1. Figure 11−12.Output Example—Timer in Up Mod...
Page 225 - Output Example—Timer in Continuous Mode; Figure 11−13.Output Example—Timer in Continuous Mode
Timer_A Operation 11-15 Timer_A Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx andTACCR0 values, depending on the output mode. An example is shown inFigure 11−13 using TACCR0 and TACCR1. Figure 11−13.Output Example—Timer in Continuous Mode 0h 0FF...
Page 226 - Output Example—Timer in Up/Down Mode; Figure 11−14.Output Example—Timer in Up/Down Mode; Switching Between Output Modes; BIS
Timer_A Operation 11-16 Timer_A Output Example—Timer in Up/Down Mode The OUTx signal changes when the timer equals TACCRx in either countdirection and when the timer equals TACCR0, depending on the output mode.An example is shown in Figure 11−14 using TACCR0 and TACCR2. Figure 11−14.Output Example—T...
Page 227 - TACCR0 Interrupt; Figure 11−15.Capture/Compare TACCR0 Interrupt Flag; TAIV, Interrupt Vector Generator
Timer_A Operation 11-17 Timer_A 11.2.6 Timer_A Interrupts Two interrupt vectors are associated with the 16-bit Timer_A module: - TACCR0 interrupt vector for TACCR0 CCIFG - TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured i...
Page 229 - The Timer_A registers are listed in Table 11−3:
Timer_A Registers 11-19 Timer_A 11.3 Timer_A Registers The Timer_A registers are listed in Table 11−3: Table 11−3. Timer_A Registers Register Short Form Register Type Address Initial State Timer_A control TACTL Read/write 0160h Reset with POR Timer_A counter TAR Read/write 0170h Reset with POR Timer...
Page 231 - TARx
Timer_A Registers 11-21 Timer_A TAR, Timer_A Register 15 14 13 12 11 10 9 8 TARx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 TARx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) TARx Bits15-0 Timer_A register. The TAR register is the count of Timer_A.
Page 232 - TACCTLx, Capture/Compare Control Register
Timer_A Registers 11-22 Timer_A TACCTLx, Capture/Compare Control Register 15 14 13 12 11 10 9 8 CMx CCISx SCS SCCI Unused CAP rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) r−(0) rw−(0) 7 6 5 4 3 2 1 0 OUTMODx CCIE CCI OUT COV CCIFG rw−(0) rw−(0) rw−(0) rw−(0) r rw−(0) rw−(0) rw−(0) CMx Bit15-14 Capture m...
Page 238 - Modifying Timer_B Registers; TBR Length; , for the selectable lengths
Timer_B Operation 12-4 Timer_B 12.2 Timer_B Operation The Timer_B module is configured with user software. The setup andoperation of Timer_B is discussed in the following sections. 12.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TBR, increments or decrements (dependingon mode of opera...
Page 239 - Table 12−1. Timer Modes
Timer_B Operation 12-5 Timer_B 12.2.2 Starting the Timer The timer may be started or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stoppedby loading 0 to TBCL0. The timer may then be...
Page 240 - The up mode is used if the timer period must be different from TBR; Figure 12−3. Up Mode Flag Setting; Changing the Period Register TBCL0
Timer_B Operation 12-6 Timer_B Up Mode The up mode is used if the timer period must be different from TBR (max) counts. The timer repeatedly counts up to the value of compare latch TBCL0, whichdefines the period, as shown in Figure 12−2. The number of timer counts inthe period is TBCL0+1. When the t...
Page 241 - In continuous mode the timer repeatedly counts up to TBR; Figure 12−4. Continuous Mode; The TBIFG interrupt flag is set when the timer counts from TBR; Figure 12−5. Continuous Mode Flag Setting
Timer_B Operation 12-7 Timer_B Continuous Mode In continuous mode the timer repeatedly counts up to TBR (max) and restarts from zero as shown in Figure 12−4. The compare latch TBCL0 works the sameway as the other capture/compare registers. Figure 12−4. Continuous Mode 0h TBR(max) The TBIFG interrupt...
Page 242 - and t; Figure 12−6. Continuous Mode Time Intervals; is greater than the TBCL0
Timer_B Operation 12-8 Timer_B Use of the Continuous Mode The continuous mode can be used to generate independent time intervals andoutput frequencies. Each time an interval is completed, an interrupt isgenerated. The next time interval is added to the TBCLx latch in the interruptservice routine. Fi...
Page 244 - Changing the Value of Period Register TBCL0
Timer_B Operation 12-10 Timer_B Changing the Value of Period Register TBCL0 When changing TBCL0 while the timer is running, and counting in the downdirection, and when the TBCL0 load mode is immediate, the timer continuesits descent until it reaches zero. The new period takes effect after the counte...
Page 245 - The timer value is copied into the TBCCRx register
Timer_B Operation 12-11 Timer_B 12.2.4 Capture/Compare Blocks Three or seven identical capture/compare blocks, TBCCRx, are present inTimer_B. Any of the blocks may be used to capture the timer data or togenerate time intervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is ...
Page 246 - Figure 12−11. Capture Cycle
Timer_B Operation 12-12 Timer_B Figure 12−11. Capture Cycle Second Capture Taken COV = 1 Capture Taken No Capture Taken Read Taken Capture Clear Bit COV in Register TBCCTLx Idle Idle Capture Capture Read and No Capture Capture Capture Read Capture Capture Initiated by Software Captures can be initia...
Page 247 - Compare Latch TBCLx; Table 12−2. TBCLx Load Events; CLLDx; New data is transferred from TBCCRx to TBCLx when TBR counts to 0; Grouping Compare Latches; Table 12−3. Compare Latch Operating Modes; TBCLGRPx; None
Timer_B Operation 12-13 Timer_B Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to thetimer value in compare mode. TBCLx is buffered by TBCCRx. The bufferedcompare latch gives the user control over when a compare period updates.The user cannot directly access T...
Page 248 - Table 12−4. Output Modes
Timer_B Operation 12-14 Timer_B 12.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is usedto generate output signals such as PWM signals. Each output unit has eightoperating modes that generate signals based on the EQU0 and EQUx signals.The TBOUTH pin function can...
Page 249 - Figure 12−12. Output Example—Timer in Up Mode
Timer_B Operation 12-15 Timer_B Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value, androlls from TBCL0 to zero, depending on the output mode. An example is shownin Figure 12−12 using TBCL0 and TBCL1. Figure 12−12. Output Example—Timer in Up Mode 0...
Page 250 - Figure 12−13. Output Example—Timer in Continuous Mode
Timer_B Operation 12-16 Timer_B Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0values, depending on the output mode, An example is shown in Figure 12−13using TBCL0 and TBCL1. Figure 12−13. Output Example—Timer in Continuous Mode 0h TBR(ma...
Page 251 - Output Example − Timer in Up/Down Mode; Figure 12−14. Output Example—Timer in Up/Down Mode
Timer_B Operation 12-17 Timer_B Output Example − Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either countdirection and when the timer equals TBCL0, depending on the output mode.An example is shown in Figure 12−14 using TBCL0 and TBCL3. Figure 12−14. Output Example—Ti...
Page 252 - Figure 12−15. Capture/Compare TBCCR0 Interrupt Flag; TBIV, Interrupt Vector Generator
Timer_B Operation 12-18 Timer_B 12.2.6 Timer_B Interrupts Two interrupt vectors are associated with the 16-bit Timer_B module: - TBCCR0 interrupt vector for TBCCR0 CCIFG - TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured ...
Page 253 - TBIV, Interrupt Handler Examples; Capture/compare block CCR0
Timer_B Operation 12-19 Timer_B TBIV, Interrupt Handler Examples The following software example shows the recommended use of TBIV and thehandling overhead. The TBIV value is added to the PC to automatically jumpto the appropriate routine. The numbers at the right margin show the necessary CPU clock ...
Page 254 - The Timer_B registers are listed in Table 12−5:
Timer_B Registers 12-20 Timer_B 12.3 Timer_B Registers The Timer_B registers are listed in Table 12−5: Table 12−5. Timer_B Registers Register Short Form Register Type Address Initial State Timer_B control TBCTL Read/write 0180h Reset with POR Timer_B counter TBR Read/write 0190h Reset with POR Timer...
Page 255 - Timer_B Control Register TBCTL
Timer_B Registers 12-21 Timer_B Timer_B Control Register TBCTL 15 14 13 12 11 10 9 8 Unused TBCLGRPx CNTLx Unused TBSSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 IDx MCx Unused TBCLR TBIE TBIFG rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) w−(0) rw−(0) rw−(0) Unused Bit 15 Unuse...
Page 256 - Unused; TBCLR; Interrupt disabled; No interrupt pending
Timer_B Registers 12-22 Timer_B Unused Bit 3 Unused TBCLR Bit 2 Timer_B clear. Setting this bit resets TBR, the TBCLK divider, and the countdirection. The TBCLR bit is automatically reset and is always read as zero. TBIE Bit 1 Timer_B interrupt enable. This bit enables the TBIFG interrupt request.0 ...
Page 257 - TBCCTLx, Capture/Compare Control Register
Timer_B Registers 12-23 Timer_B TBCCTLx, Capture/Compare Control Register 15 14 13 12 11 10 9 8 CMx CCISx SCS CLLDx CAP rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) rw−(0) 7 6 5 4 3 2 1 0 OUTMODx CCIE CCI OUT COV CCIFG rw−(0) rw−(0) rw−(0) rw−(0) r rw−(0) rw−(0) rw−(0) CMx Bit15-14 Capture mode00...
Page 259 - Timer_B interrupt vector value
Timer_B Registers 12-25 Timer_B TBIV, Timer_B Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 0 TBIVx 0 r0 r0 r0 r0 r−(0) r−(0) r−(0) r0 TBIVx Bits15-0 Timer_B interrupt vector value TBIV Contents Interrupt Source Interrupt Flag Interrupt...
Page 261 - USART Peripheral Interface, UART Mode
13-1 USART Peripheral Interface, UART Mode !) " - !) The universal synchronous/asynchronous receive/transmit (USART)peripheral interface supports two serial modes with one hardware module.This chapter discusses the operation of the asynchronous UART mode.USART0 is implemented on the MSP430x12xx,...
Page 263 - Figure 13−1. USART Block Diagram: UART Mode
USART Introduction: UART Mode 13-3 USART Peripheral Interface, UART Mode Figure 13−1. USART Block Diagram: UART Mode Receiver Shift Register Transmit Shift Register Receiver Buffer UxRXBUF Transmit Buffer UxTXBUF LISTEN MM UCLK Clock Phase and Polarity Receive Status SYNC CKPH CKPL SSEL1 SSEL0 UCLKI...
Page 264 - Note: Initializing or Re-Configuring the USART Module; The required USART initialization/re-configuration process is:; Figure 13−2. Character Format
USART Operation: UART Mode 13-4 USART Peripheral Interface, UART Mode 13.2 USART Operation: UART Mode In UART mode, the USART transmits and receives characters at a bit rateasynchronous to another device. Timing for each character is based on theselected baud rate of the USART. The transmit and rece...
Page 265 - Asynchronous Communication Formats; Line Format
USART Operation: UART Mode 13-5 USART Peripheral Interface, UART Mode 13.2.3 Asynchronous Communication Formats When two devices communicate asynchronously, the idle-line format is usedfor the protocol. When three or more devices communicate, the USARTsupports the idle-line and address-bit multiproc...
Page 266 - ) Set TXWAKE, then write any character to UxTXBUF. UxTXBUF must be
USART Operation: UART Mode 13-6 USART Peripheral Interface, UART Mode The URXWIE bit is used to control data reception in the idle-linemultiprocessor format. When the URXWIE bit is set, all non-addresscharacters are assembled but not transferred into the UxRXBUF, andinterrupts are not generated. Whe...
Page 267 - Address; Figure 13−4. Address
USART Operation: UART Mode 13-7 USART Peripheral Interface, UART Mode Address - Bit Multiprocessor Format When MM = 1, the address-bit multiprocessor format is selected. Eachprocessed character contains an extra bit used as an address indicator shownin Figure 13−4. The first character in a block of ...
Page 268 - Automatic Error Detection; will be ignored. See the device-specific datasheet for parameters.; Table 13−1. Receive Error Conditions; Error Condition; Framing error
USART Operation: UART Mode 13-8 USART Peripheral Interface, UART Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started. Anylow-level on URXDx shorter than the deglitch time t τ (approximately 300 ns) will be ignored. See the device-specific datasheet fo...
Page 269 - Figure 13−5. State Diagram of Receiver Enable
USART Operation: UART Mode 13-9 USART Peripheral Interface, UART Mode 13.2.4 USART Receive Enable The receive enable bit, URXEx, enables or disables data reception on URXDxas shown in Figure 13−5. Disabling the USART receiver stops the receiveoperation following completion of any character currently...
Page 270 - Figure 13−6. State Diagram of Transmitter Enable
USART Operation: UART Mode 13-10 USART Peripheral Interface, UART Mode 13.2.5 USART Transmit Enable When UTXEx is set, the UART transmitter is enabled. Transmission is initiatedby writing data to UxTXBUF. The data is then moved to the transmit shiftregister on the next BITCLK after the TX shift regi...
Page 271 - Figure 13−8. BITCLK Baud Rate Timing
USART Operation: UART Mode 13-11 USART Peripheral Interface, UART Mode 13.2.6 UART Baud Rate Generation The USART baud rate generator is capable of producing standard baud ratesfrom non-standard source frequencies. The baud rate generator uses oneprescaler/divider and a modulator as shown in Figure ...
Page 272 - Baud Rate Bit Timing; UxBR; Determining the Modulation Value
USART Operation: UART Mode 13-12 USART Peripheral Interface, UART Mode Baud Rate Bit Timing The first stage of the baud rate generator is the 16-bit counter and comparator.At the beginning of each bit transmitted or received, the counter is loaded withINT(N/2) where N is the value stored in the comb...
Page 273 - Transmit Bit Timing; baud rate
USART Operation: UART Mode 13-13 USART Peripheral Interface, UART Mode Transmit Bit Timing The timing for each character is the sum of the individual bit timings. Bymodulating each bit, the cumulative bit error is reduced. The individual bit errorcan be calculated by: Error [%] + NJ baud rate BRCLK ƪ...
Page 274 - Receive Bit Timing; Figure 13−9. Receive Error; ȧȡȢ
USART Operation: UART Mode 13-14 USART Peripheral Interface, UART Mode Receive Bit Timing Receive timing consists of two error sources. The first is the bit-to-bit timingerror. The second is the error between a start edge occurring and the startedge being accepted by the USART. Figure 13−9 shows the...
Page 275 - 3, since the ideal division factor is 13.65
USART Operation: UART Mode 13-15 USART Peripheral Interface, UART Mode For example, the receive errors for the following conditions are calculated: Baud rate = 2400BRCLK = 32,768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.65 UxMCTL = 6B:m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0,...
Page 276 - Typical Baud Rates and Errors; Table 13−2. Commonly Used Baud Rates, Baud Rate Data, and Errors
USART Operation: UART Mode 13-16 USART Peripheral Interface, UART Mode Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed inTable 13−2 for a 32,768-Hz watch crystal (ACLK) and a typical 1,048,576-HzSMCLK. The receive error is the accumulated time versus t...
Page 277 - USART Transmit Interrupt Operation; Figure 13−10. Transmit Interrupt Operation
USART Operation: UART Mode 13-17 USART Peripheral Interface, UART Mode 13.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vectorfor reception. USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUFis...
Page 278 - USART Receive Interrupt Operation; Figure 13−11. Receive Interrupt Operation; Two types of characters do not set URXIFGx:
USART Operation: UART Mode 13-18 USART Peripheral Interface, UART Mode USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loadedinto UxRXBUF. An interrupt request is generated if URXIEx and GIE are alsoset. URXIFGx and URXIEx are reset by a syst...
Page 279 - Receive-Start Edge Detect Operation; Break Detect With Halted UART Clock
USART Operation: UART Mode 13-19 USART Peripheral Interface, UART Mode Receive-Start Edge Detect Operation The URXSE bit enables the receive start-edge detection feature. Therecommended usage of the receive-start edge feature is when BRCLK issourced by the DCO and when the DCO is off because of low-...
Page 280 - Receive-Start Edge Detect Conditions; Figure 13−12. Glitch Suppression, USART Receive Not Started; When a glitch is longer than; Figure 13−13. Glitch Suppression, USART Activated; URXDx
USART Operation: UART Mode 13-20 USART Peripheral Interface, UART Mode Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from beingaccidentally started. Any low-level on URXDx shorter than the deglitch time t τ (approximately 300 ns) will be ignored by the US...
Page 281 - Table 13−3. USART0 Control and Status Registers; Modifying SFR bits
USART Registers: UART Mode 13-21 USART Peripheral Interface, UART Mode 13.3 USART Registers: UART Mode Table 13−3 lists the registers for all devices implementing a USART module.Table 13−4 applies only to devices with a second USART module, USART1. Table 13−3. USART0 Control and Status Registers Reg...
Page 282 - UxCTL, USART Control Register
USART Registers: UART Mode 13-22 USART Peripheral Interface, UART Mode UxCTL, USART Control Register 7 6 5 4 3 2 1 0 PENA PEV SPB CHAR LISTEN SYNC MM SWRST rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 PENA Bit 7 Parity enable0 Parity disabled. 1 Parity enabled. Parity bit is generated (UTXDx) and expecte...
Page 283 - UxTCTL, USART Transmit Control Register
USART Registers: UART Mode 13-23 USART Peripheral Interface, UART Mode UxTCTL, USART Transmit Control Register 7 6 5 4 3 2 1 0 Unused CKPL SSELx URXSE TXWAKE Unused TXEPT rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 Unused Bit 7 Unused CKPL Bit 6 Clock polarity select0 UCLKI = UCLK 1 UCLKI = inverted UCL...
Page 284 - UxRCTL, USART Receive Control Register
USART Registers: UART Mode 13-24 USART Peripheral Interface, UART Mode UxRCTL, USART Receive Control Register 7 6 5 4 3 2 1 0 FE PE OE BRK URXEIE URXWIE RXWAKE RXERR rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 FE Bit 7 Framing error flag0 No error 1 Character received with low stop bit PE Bit 6 Parity e...
Page 285 - UxBR0, USART Baud Rate Control Register 0; UxBRx; The valid baud-rate control range is 3; UxMCTL, USART Modulation Control Register; UxMCTLx; Modulation bits. These bits select the modulation for BRCLK.
USART Registers: UART Mode 13-25 USART Peripheral Interface, UART Mode UxBR0, USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxBR1, USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 215 214 213 212 211 210 29 28 rw rw rw rw rw rw rw rw UxBRx The v...
Page 286 - UxRXBUF, USART Receive Buffer Register; UxRXBUFx; UxTXBUF, USART Transmit Buffer Register; UxTXBUFx
USART Registers: UART Mode 13-26 USART Peripheral Interface, UART Mode UxRXBUF, USART Receive Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 r r r r r r r r UxRXBUFx Bits7−0 The receive-data buffer is user accessible and contains the last receivedcharacter from the receive shift register. R...
Page 287 - ME1, Module Enable Register 1
USART Registers: UART Mode 13-27 USART Peripheral Interface, UART Mode ME1, Module Enable Register 1 7 6 5 4 3 2 1 0 UTXE0† URXE0† rw−0 rw−0 UTXE0 † Bit 7 USART0 transmit enable. This bit enables the transmitter for USART0.0 Module not enabled 1 Module enabled URXE0 † Bit 6 USART0 receive enable. Th...
Page 288 - IE2, Interrupt Enable Register 2
USART Registers: UART Mode 13-28 USART Peripheral Interface, UART Mode IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 UTXIE0† URXIE0† rw−0 rw−0 UTXIE0 † Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt.0 Interrupt not enabled 1 Interrupt enabled URXIE0 † Bit 6 USART0 ...
Page 289 - UTXIFG0; IFG2, Interrupt Flag Register 2; UTXIFG1
USART Registers: UART Mode 13-29 USART Peripheral Interface, UART Mode IFG1, Interrupt Flag Register 1 7 6 5 4 3 2 1 0 UTXIFG0† URXIFG0† rw−1 rw−0 UTXIFG0 † Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty.0 No interrupt pending 1 Interrupt pending URXIFG0 † Bit 6 USART0 re...
Page 290 - URXIFG0
USART Registers: UART Mode 13-30 USART Peripheral Interface, UART Mode UTXIFG0 ‡ Bit 1 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty.0 No interrupt pending 1 Interrupt pending URXIFG0 ‡ Bit 0 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has receiveda complete cha...
Page 292 - USART Peripheral Interface, SPI Mode
14-1 USART Peripheral Interface, SPI Mode !)"- The universal synchronous/asynchronous receive/transmit (USART)peripheral interface supports two serial modes with one hardware module.This chapter discusses the operation of the synchronous peripheral interfaceor SPI mode. USART0 is implemented on ...
Page 294 - Figure 14−1. USART Block Diagram: SPI Mode
USART Introduction: SPI Mode 14-3 USART Peripheral Interface, SPI Mode Figure 14−1. USART Block Diagram: SPI Mode Receiver Shift Register Transmit Shift Register Receiver Buffer UxRXBUF Transmit Buffer UxTXBUF LISTEN MM UCLK Clock Phase and Polarity Receive Status SYNC CKPH CKPL SSEL1 SSEL0 UCLKI AC...
Page 296 - Figure 14−2. USART Master and External Slave; Four-Pin SPI Master Mode; SIMO and UCLK are set to inputs and no longer drive the bus
USART Operation: SPI Mode 14-5 USART Peripheral Interface, SPI Mode 14.2.2 Master Mode Figure 14−2. USART Master and External Slave Receive Buffer UxRXBUF Receive Shift Register MSB LSB Transmit Buffer UxTXBUF Transmit Shift Register MSB LSB SPI Receive Buffer Data Shift Register (DSR) MSB LSB SOMI ...
Page 297 - Figure 14−3. USART Slave and External Master; Four-Pin SPI Slave Mode; Any receive operation in progress on SIMO is halted
USART Operation: SPI Mode 14-6 USART Peripheral Interface, SPI Mode 14.2.3 Slave Mode Figure 14−3. USART Slave and External Master Receive Buffer UxRXBUF Receive Shift Register LSB MSB Transmit Buffer UxTXBUF Transmit Shift Register LSB MSB SPI Receive Buffer Data Shift Register DSR LSB MSB SOMI SOM...
Page 298 - Transmit Enable; Figure 14−4. Master Mode Transmit Enable
USART Operation: SPI Mode 14-7 USART Peripheral Interface, SPI Mode 14.2.4 SPI Enable The SPI transmit/receive enable bit USPIEx enables or disables the USARTin SPI mode. When USPIEx = 0, the USART stops operation after the currenttransfer completes, or immediately if no operation is active. A PUC o...
Page 299 - Receive Enable; Figure 14−6. SPI Master Receive-Enable State Diagram
USART Operation: SPI Mode 14-8 USART Peripheral Interface, SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 14−6 andFigure 14−7. When USPIEx = 0, UCLK is disabled from shifting data into theRX shift register. Figure 14−6. SPI Master Receive-Enable State Diagram Idle ...
Page 300 - Figure 14−8. SPI Baud Rate Generator; BRCLK
USART Operation: SPI Mode 14-9 USART Peripheral Interface, SPI Mode 14.2.5 Serial Clock Control UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK isprovided by the USART baud rate generator on the UCLK pin as shown inFigure 14−8. When MM = 0, the USART clock is provided on the UCLK ...
Page 301 - Serial Clock Polarity and Phase; Figure 14−9. USART SPI Timing
USART Operation: SPI Mode 14-10 USART Peripheral Interface, SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPLand CKPH control bits of the USART. Timing for each case is shown inFigure 14−9. Figure 14−9. USART SPI Timing CKPH CKPL Cycle#...
Page 302 - SPI Transmit Interrupt Operation; Figure 14−10. Transmit Interrupt Operation; Writing to UxTXBUF in SPI Mode
USART Operation: SPI Mode 14-11 USART Peripheral Interface, SPI Mode 14.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vectorfor reception. SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUFis ready...
Page 303 - SPI Receive Interrupt Operation; Figure 14−11. Receive Interrupt Operation; Figure 14−12. Receive Interrupt State Diagram
USART Operation: SPI Mode 14-12 USART Peripheral Interface, SPI Mode SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loadedinto UxRXBUF as shown in Figure 14−11 and Figure 14−12. An interruptrequest is generated if URXIEx and GIE are also set. ...
Page 304 - Table 14−1. USART0 Control and Status Registers; Modifying the SFR bits
USART Registers: SPI Mode 14-13 USART Peripheral Interface, SPI Mode 14.3 USART Registers: SPI Mode The USART registers, shown in Table 14−1 and Table 14−2, are bytestructured and should be accessed using byte instructions. Table 14−1. USART0 Control and Status Registers Register Short Form Register...
Page 310 - ME2, Module Enable Register 2
USART Registers: SPI Mode 14-19 USART Peripheral Interface, SPI Mode ME1, Module Enable Register 1 7 6 5 4 3 2 1 0 USPIE0† rw−0 Bit 7 This bit may be used by other modules. See device-specific datasheet. USPIE0 † Bit 6 USART0 SPI enable. This bit enables the SPI mode for USART0.0 Module not enabled ...
Page 312 - Interrupt not enabled
USART Registers: SPI Mode 14-21 USART Peripheral Interface, SPI Mode UTXIE0 ‡ Bit 1 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt.0 Interrupt not enabled 1 Interrupt enabled URXIE0 ‡ Bit 0 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt forUSART0.0 ...
Page 315 - C communication in USART0. This chapter; C Module Introduction
15-1 USART Peripheral Interface, I 2 C Mode !) " - . The universal synchronous/asynchronous receive/transmit (USART)peripheral interface supports I 2 C communication in USART0. This chapter describes the I 2 C mode. The I 2 C mode is implemented on the MSP430x15x and MSP430x16x devices. Topic Pa...
Page 317 - C Mode
I 2 C Module Introduction 15-3 USART Peripheral Interface, I 2 C Mode Figure 15−1. USART Block Diagram: I 2 C Mode Receive Shift Register Transmit Shift Register SDA I2C Clock Generator I2CEN SCL MST ACLK SMCLK SMCLK 0 1 00 01 10 11 0 1 LISTEN I2CSSELx 1 No clock I2CIN I2CCLK I2CDRW I2CSCLLOW I2CTXU...
Page 318 - C Module Operation; The I; C Bus Connection Diagram; SDA and SCL Levels
I 2 C Module Operation 15-4 USART Peripheral Interface, I 2 C Mode 15.2 I 2 C Module Operation The I 2 C module supports any slave or master I 2 C-compatible device. Figure 15−2 shows an example of an I 2 C bus. Each I 2 C device is recognized by a unique address and can operate as either a transmit...
Page 319 - C Module Initialization; Note: Configuring the USART Module for I
I 2 C Module Operation 15-5 USART Peripheral Interface, I 2 C Mode 15.2.1 I 2 C Module Initialization The I 2 C module is part of the USART peripheral. Individual bit definitions when using USART0 in I 2 C mode are different from that in SPI or UART mode. The default value for the U0CTL register is ...
Page 320 - C Serial Data; C module operates with byte data. Data is transferred most; C Module Data Transfer
I 2 C Module Operation 15-6 USART Peripheral Interface, I 2 C Mode 15.2.2 I 2 C Serial Data One clock pulse is generated by the master device for each data bittransferred. The I 2 C module operates with byte data. Data is transferred most significant bit first as shown in Figure 15−3. The first byte...
Page 321 - C Addressing Modes; C Module 7-Bit Addressing Format; Repeated START Conditions; C Module Addressing Format with Repeated START Condition
I 2 C Module Operation 15-7 USART Peripheral Interface, I 2 C Mode 15.2.3 I 2 C Addressing Modes The I 2 C module supports 7-bit and 10-bit addressing modes. 7-Bit Addressing In the 7-bit addressing format, shown in Figure 15−5, the first byte is the 7-bitslave address and the R/W bit. The ACK bit i...
Page 322 - C Module Operating Modes; Master Mode; Table 15−1. Master Operation; Condition Or Bus Activity
I 2 C Module Operation 15-8 USART Peripheral Interface, I 2 C Mode 15.2.4 I 2 C Module Operating Modes The I 2 C module operates in master transmitter, master receiver, slave transmitter, or slave receiver mode. Master Mode In master mode, transmit and receive operation is controlled with the I2CRM,...
Page 323 - Figure 15−8. Master Transmitter Mode
I 2 C Module Operation 15-9 USART Peripheral Interface, I 2 C Mode Figure 15−8. Master Transmitter Mode IDLE Generate START I2CBUSY Is Set 4 x I2CPSC I2CBB Is Set I2CSTT Is Cleared 8 x I2CPSC Send Slave Address Bits 6−0 with R/W=0 8 x SCL 1 Send Slave Address Bits 9−8 Extended with R/W = 0 8 x SCL I...
Page 324 - Figure 15−9. Master Receiver Mode
I 2 C Module Operation 15-10 USART Peripheral Interface, I 2 C Mode Figure 15−9. Master Receiver Mode IDLE Generate START 4 x I2CPSC I2CBB Is Set I2CSTT Is Cleared 8 x I2CPSC Send Slave Address Bits 6−0 with R/W = 1 8 x SCL Send Slave Address Bits 9−8 Extended With R/W = 0 8 x SCL STOP State? STOP S...
Page 325 - Arbitration
I 2 C Module Operation 15-11 USART Peripheral Interface, I 2 C Mode Arbitration If two or more master transmitters simultaneously start a transmission on thebus, an arbitration procedure is invoked. Figure 15−10 illustrates thearbitration procedure between two devices. The arbitration procedure uses...
Page 326 - Automatic Data Byte Counting; I2CNDAT Register; Slave Mode; I2CTRX Bit In Slave Mode; The I2CTRX bit must be cleared for proper slave mode operation.
I 2 C Module Operation 15-12 USART Peripheral Interface, I 2 C Mode Automatic Data Byte Counting Automatic data byte counting is supported in master mode with the I2CNDATregister. When I2CRM = 0, the number of bytes to be received or transmittedis written to I2CNDAT. A STOP condition is automaticall...
Page 327 - Figure 15−11. Slave Transmitter
I 2 C Module Operation 15-13 USART Peripheral Interface, I 2 C Mode Figure 15−11. Slave Transmitter I2CBB Is Cleared Send Data Low Byte To Master 2nd Start Detected? Send Data High Byte To Master Ack Ack 8 x SCL 8 x SCL STTIFG Is Set I2CBUSY Is Set START Detected? I2CBB Is Set Send Acknowledge 1 x S...
Page 328 - Figure 15−12. Slave Receiver
I 2 C Module Operation 15-14 USART Peripheral Interface, I 2 C Mode Figure 15−12. Slave Receiver IDLE I2CBB Is Cleared 4 x I2CPSC Yes Receive Data Low Byte From Master RESTART Detected ? Send Acknowledge Receive Data High Byte From Master Send Acknowledge 1 x SCL 1 x SCL 8 x SCL 8 x SCL No I2CWORD=0...
Page 329 - C Data Register I2CDR; Table 15−2. I2CDR Register Function; I2CWORD; Transmit Underflow; C master still; Receive Overrun
I 2 C Module Operation 15-15 USART Peripheral Interface, I 2 C Mode 15.2.5 The I 2 C Data Register I2CDR The I2CDR register can be accessed as an 8-bit or 16-bit register selected bythe I2CWORD bit. The I2CDR register functions as described in Table 15−2.When I2CWORD = 1, any attempt to modify the r...
Page 330 - C Clock Generation and Synchronization; I2CCLK Maximum Frequency; I2CPSC Value; C Module SCL Generation
I 2 C Module Operation 15-16 USART Peripheral Interface, I 2 C Mode 15.2.6 I 2 C Clock Generation and Synchronization The I 2 C module is operated with the clock source selected by the I2CSSELx bits. The prescaler, I2CPSC, and the I2CSCLH and I2CSCLL registersdetermine the frequency and duty cycle o...
Page 331 - C Module with Low Power Modes
I 2 C Module Operation 15-17 USART Peripheral Interface, I 2 C Mode 15.2.7 Using the I 2 C Module with Low Power Modes The I 2 C module can be used with MSP430 low-power modes. When the internal clock source for the I 2 C module is present, the module operates normally regardless of the MSP430 opera...
Page 332 - C Interrupts; Interrupt
I 2 C Module Operation 15-18 USART Peripheral Interface, I 2 C Mode 15.2.8 I 2 C Interrupts The I 2 C module has one interrupt vector for eight interrupt flags listed in Table 15−3. Each interrupt flag has its own interrupt enable bit. When an interruptis enabled, and the GIE bit is set, the interru...
Page 333 - I2CIV, Interrupt Vector Generator
I 2 C Module Operation 15-19 USART Peripheral Interface, I 2 C Mode I2CIV, Interrupt Vector Generator The I 2 C interrupt flags are prioritized and combined to source a single interrupt vector. The interrupt vector register I2CIV is used to determine which flagrequested an interrupt. The highest pri...
Page 334 - C Module Registers; C Registers
I 2 C Module Registers 15-20 USART Peripheral Interface, I 2 C Mode 15.3 I 2 C Module Registers The I 2 C module registers are listed in Table 15−4. Table 15−4. I 2 C Registers Register Short Form Register Type Address Initial State I 2 C interrupt enable I2CIE Read/write 050h Reset with PUC I 2 C i...
Page 336 - C Transmit Control Register
I 2 C Module Registers 15-22 USART Peripheral Interface, I 2 C Mode I2CTCTL, I 2 C Transmit Control Register 7 6 5 4 3 2 1 0 I2CWORD I2CRM I2CSSELx I2CTRX I2CSTB I2CSTP I2CSTT rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2CWORD Bit 7 I 2 C word mode. Selects byte or word m...
Page 337 - C Data Control Register
I 2 C Module Registers 15-23 USART Peripheral Interface, I 2 C Mode I2CDCTL, I 2 C Data Control Register 7 6 5 4 3 2 1 0 Unused Unused I2CBUSY I2C SCLLOW I2CSBD I2CTXUDF I2CRXOVR I2CBB r0 r0 r−0 r−0 r−0 r−0 r−0 r−0 Unused Bits7−6 Unused. Always read as 0. I2CBUSY Bit 5 I 2 C busy 0 I 2 C module is i...
Page 338 - C Data Register; C Transfer Byte Count Register; I2CNDATx
I 2 C Module Registers 15-24 USART Peripheral Interface, I 2 C Mode I2CDRW, I2CDRB, I 2 C Data Register 15 14 13 12 11 10 9 8 I2CDRW High Byte rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 7 6 5 4 3 2 1 0 I2CDRW Low Byte I2CDRB rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 I2CDRW/I2CDRB Bits15−8 I 2 C Data. Whe...
Page 339 - C Clock Prescaler Register; I2CPSCx; C clock prescaler. The I
I 2 C Module Registers 15-25 USART Peripheral Interface, I 2 C Mode I2CPSC, I 2 C Clock Prescaler Register 7 6 5 4 3 2 1 0 I2CPSCx rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2CPSCx Bits7−0 I 2 C clock prescaler. The I 2 C clock input I2CIN is divided by the I2CPSCx value...
Page 340 - C Shift Clock High Register; I2CSCLHx; C Shift Clock Low Register; C shift clock low. These bits define the low period of SCL when the I
I 2 C Module Registers 15-26 USART Peripheral Interface, I 2 C Mode I2CSCLH, I 2 C Shift Clock High Register 7 6 5 4 3 2 1 0 I2CSCLHx rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2CSCLHx Bits7−0 I 2 C shift clock high. These bits define the high period of SCL when the I 2 ...
Page 341 - C Own Address Register, 7-Bit Addressing Mode; C Own Address Register, 10-Bit Addressing Mode; C own address. The I2COA register contains the local address of the
I 2 C Module Registers 15-27 USART Peripheral Interface, I 2 C Mode I2COA, I 2 C Own Address Register, 7-Bit Addressing Mode 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 I2COAx r0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2COAx Bits15-0 I 2...
Page 342 - C Slave Address Register, 7-Bit Addressing Mode
I 2 C Module Registers 15-28 USART Peripheral Interface, I 2 C Mode I2CSA, I 2 C Slave Address Register, 7-Bit Addressing Mode 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 I2CSAx r0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 I2CSAx Bits15-0 I 2 C slave address. The I2CSA r...
Page 343 - C Interrupt Enable Register
I 2 C Module Registers 15-29 USART Peripheral Interface, I 2 C Mode I2CIE, I 2 C Interrupt Enable Register 7 6 5 4 3 2 1 0 STTIE GCIE TXRDYIE RXRDYIE ARDYIE OAIE NACKIE ALIE rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 STTIE Bit 7 START detect interrupt enable0 Interrupt disabled 1 Interrupt enabled GCIE...
Page 344 - C Interrupt Flag Register
I 2 C Module Registers 15-30 USART Peripheral Interface, I 2 C Mode I2CIFG, I 2 C Interrupt Flag Register 7 6 5 4 3 2 1 0 STTIFG GCIFG TXRDYIFG RXRDYIFG ARDYIFG OAIFG NACKIFG ALIFG rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 STTIFG Bit 7 START detect interrupt flag0 No interrupt pending 1 Interrupt pend...
Page 345 - C Interrupt Vector Register
I 2 C Module Registers 15-31 USART Peripheral Interface, I 2 C Mode I2CIV, I 2 C Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 I2CIVx 0 r0 r0 r0 r−0 r−0 r−0 r−0 r0 I2CIVx Bits15-0 I 2 C interrupt vector value I2CIV Contents Interrupt So...
Page 348 - Comparator_A Introduction
Comparator_A Introduction 16-2 Comparator_A 16.1 Comparator_A Introduction The comparator_A module supports precision slope analog-to-digitalconversions, supply voltage supervision, and monitoring of external analogsignals. Features of Comparator_A include: - Inverting and non-inverting terminal inp...
Page 350 - Comparator_A Operation; Comparator Input Connection
Comparator_A Operation 16-4 Comparator_A 16.2 Comparator_A Operation The comparator_A module is configured with user software. The setup andoperation of comparator_A is discussed in the following sections. 16.2.1 Comparator The comparator compares the analog voltages at the + and – input terminals.I...
Page 351 - Figure 16−2. RC-Filter Response at the Output of the Comparator; The voltage reference generator is used to generate V; which can be; CAREF; is applied. If external signals are applied to both; or a fixed transistor threshold voltage
Comparator_A Operation 16-5 Comparator_A 16.2.3 Output Filter The output of the comparator can be used with or without internal filtering.When control bit CAF is set, the output is filtered with an on-chip RC-filter. Any comparator output oscillates if the voltage difference across the inputterminal...
Page 352 - Figure 16−4. Comparator_A Interrupt System
Comparator_A Operation 16-6 Comparator_A 16.2.5 Comparator_A, Port Disable Register CAPD The comparator input and output functions are multiplexed with the associatedI/O port pins, which are digital CMOS gates. When analog signals are appliedto digital CMOS gates, parasitic current can flow from V C...
Page 353 - Figure 16−5. Temperature Measurement System
Comparator_A Operation 16-7 Comparator_A 16.2.7 Comparator_A Used to Measure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elementsusing single slope analog-to-digital conversion. For example, temperature canbe converted into digital data using a thermistor, by ...
Page 354 - Figure 16−6. Timing for Temperature Measurement Systems; The V; voltage; and the capacitor value should remain constant during the
Comparator_A Operation 16-8 Comparator_A The thermistor measurement is based on a ratiometric conversion principle.The ratio of two capacitor discharge times is calculated as shown inFigure 16−6. Figure 16−6. Timing for Temperature Measurement Systems V C V CC 0.25 × V CC Phase I: Charge Phase II: D...
Page 355 - Comparator_A Registers; The Comparator_A registers are listed in Table 16−1:
Comparator_A Registers 16-9 Comparator_A 16.3 Comparator_A Registers The Comparator_A registers are listed in Table 16−1: Table 16−1. Comparator_A Registers Register Short Form Register Type Address Initial State Comparator_A control register 1 CACTL1 Read/write 059h Reset with POR Comparator_A cont...
Page 361 - ADC12 Introduction
ADC12 Introduction 17-3 ADC12 Figure 17−1. ADC12 Block Diagram Sample and Hold Ve REF+ 12−bit SAR VR− − 16 x 12 Memory Buffer − − 16 x 8 Memory Control − VR+ VREF+ Ve REF− VREF− / ADC12SC TA1 TB1 TB0 Divider /1 .. /8 ADC12DIVx ADC12CLK ENC MSC SHP SHT0x SAMPCON SHI S/H Convert Sync Sample Timer /4 ....
Page 362 - Conversion Clock Selection
ADC12 Operation 17-4 ADC12 17.2 ADC12 Operation The ADC12 module is configured with user software. The setup and operationof the ADC12 is discussed in the following sections. 17.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation andstores the result in con...
Page 363 - ) so that the stray capacitance is grounded to help; Figure 17−2. Analog Multiplexer; Analog Port Selection; to GND. This parasitic current occurs if the
ADC12 Operation 17-5 ADC12 17.2.2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channelfor conversion by the analog input multiplexer. The input multiplexer is abreak-before-make type to reduce input-to-input noise injection resulting fromchanne...
Page 364 - Reference Decoupling; REF−
ADC12 Operation 17-6 ADC12 17.2.3 Voltage Reference Generator The ADC12 module contains a built-in voltage reference with two selectablevoltage levels, 1.5 V and 2.5 V. Either of these reference voltages may be usedinternally and externally on pin V REF+ . Setting REFON=1 enables the internal refere...
Page 365 - ADC12 Operation; The ADC12SC bit; Extended Sample Mode; When; Figure 17−3. Extended Sample Mode
ADC12 Operation 17-7 ADC12 17.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of the sampleinput signal SHI. The source for SHI is selected with the SHSx bits andincludes the following: - The ADC12SC bit - The Timer_A Output Unit 1 - The Timer_B Outpu...
Page 366 - Pulse Sample Mode; AD12CLK for a programmed interval t; . The total sampling time is t; sample; plus t; sync; Figure 17−4. Pulse Sample Mode
ADC12 Operation 17-8 ADC12 Pulse Sample Mode The pulse sample mode is selected when SHP = 1. The SHI signal is used totrigger the sampling timer. The SHT0x and SHT1x bits in ADC12CTL0 controlthe interval of the sampling timer that defines the SAMPCON sample periodt sample. The sampling timer keeps S...
Page 367 - Sample Timing Considerations; Figure 17−5. Analog Input Equivalent Circuit
ADC12 Operation 17-9 ADC12 Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON =1, the selected Ax input can be modeled as an RC low-pass filter during thesampling time t sample , as shown below in Figure 17−5. An internal MUX-on input resistance R I (max. 2 ...
Page 368 - Table 17−1. Conversion Mode Summary; CONSEQx; A single channel is converted once.
ADC12 Operation 17-10 ADC12 17.2.6 Conversion Memory There are 16 ADC12MEMx conversion memory registers to store conversionresults. Each ADC12MEMx is configured with an associated ADC12MCTLxcontrol register. The SREFx bits define the voltage reference and the INCHxbits select the input channel. The ...
Page 373 - Using the Multiple Sample and Convert (MSC) Bit; No EOS Bit Set For Sequence
ADC12 Operation 17-15 ADC12 Using the Multiple Sample and Convert (MSC) Bit To configure the converter to perform successive conversions automaticallyand as quickly as possible, a multiple sample and convert function is available.When MSC = 1, CONSEQx > 0, and the sample timer is used, the first ...
Page 374 - Using the Integrated Temperature Sensor; output or affect the reference selections for the conversion.; Figure 17−10. Typical Temperature Sensor Transfer Function
ADC12 Operation 17-16 ADC12 17.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog inputchannel INCHx = 1010. Any other configuration is done as if an externalchannel was selected, including reference selection, conversion-memoryselection, e...
Page 375 - ADC12 Grounding and Noise Considerations; Figure 17−11. ADC12 Grounding and Noise Considerations
ADC12 Operation 17-17 ADC12 17.2.9 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout andgrounding techniques should be followed to eliminate ground loops, unwantedparasitic effects, and noise. Ground loops are formed when return curren...
Page 376 - ADC12 Interrupts; The ADC12 has 18 interrupt sources:; ADC12IV, Interrupt Vector Generator
ADC12 Operation 17-18 ADC12 17.2.10 ADC12 Interrupts The ADC12 has 18 interrupt sources: - ADC12IFG0-ADC12IFG15 - ADC12OV, ADC12MEMx overflow - ADC12TOV, ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memoryregister is loaded with a conversion result. An...
Page 377 - ADC12 Interrupt Handling Software Example; ADTOV
ADC12 Operation 17-19 ADC12 ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IVand the handling overhead. The ADC12IV value is added to the PC toautomatically jump to the appropriate routine. The numbers at the right margin show the necessary...
Page 378 - ADC12 Registers; The ADC12 registers are listed in Table 17−2:
ADC12 Registers 17-20 ADC12 17.3 ADC12 Registers The ADC12 registers are listed in Table 17−2: Table 17−2. ADC12 Registers Register Short Form Register Type Address Initial State ADC12 control register 0 ADC12CTL0 Read/write 01A0h Reset with POR ADC12 control register 1 ADC12CTL1 Read/write 01A2h Re...
Page 379 - SHTx Bits
ADC12 Registers 17-21 ADC12 ADC12CTL0, ADC12 Control Register 0 15 14 13 12 11 10 9 8 SHT1x SHT0x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 MSC REF2_5V REFON ADC12ON ADC12OVIE ADC12 TOVIE ENC ADC12SC rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Modifiable onl...
Page 381 - SHSx; SAMPCON signal is sourced from the sample-input signal.; ISSH
ADC12 Registers 17-23 ADC12 ADC12CTL1, ADC12 Control Register 1 15 14 13 12 11 10 9 8 CSTARTADDx SHSx SHP ISSH rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 ADC12DIVx ADC12SSELx CONSEQx ADC12 BUSY rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) Modifiable only when E...
Page 382 - No operation is active.; ADC12MEMx, ADC12 Conversion Memory Registers
ADC12 Registers 17-24 ADC12 ADC12SSELx Bits4-3 ADC12 clock source select00 ADC12OSC 01 ACLK 10 MCLK 11 SMCLK CONSEQx Bits2-1 Conversion sequence mode select00 Single-channel, single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels ADC12BUSY Bit 0 ADC12 busy....
Page 383 - ADC12MCTLx, ADC12 Conversion Memory Control Registers; EOS
ADC12 Registers 17-25 ADC12 ADC12MCTLx, ADC12 Conversion Memory Control Registers 7 6 5 4 3 2 1 0 EOS SREFx INCHx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 EOS Bit 7 End of sequence. Indicates the last conversion in a sequence.0 Not end of sequence 1 End of...
Page 384 - ADC12IE, ADC12 Interrupt Enable Register; ADC12IFG, ADC12 Interrupt Flag Register
ADC12 Registers 17-26 ADC12 ADC12IE, ADC12 Interrupt Enable Register 15 14 13 12 11 10 9 8 ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IE9 ADC12IE8 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 ADC12IE7 ADC12IE6 ADC12IE5 ADC12IE4 ADC12IE3 ADC12IE2 ADC12...
Page 385 - ADC12IV, ADC12 Interrupt Vector Register; ADC12 interrupt vector value
ADC12 Registers 17-27 ADC12 ADC12IV, ADC12 Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 ADC12IVx 0 r0 r0 r−(0) r−(0) r−(0) r−(0) r−(0) r0 ADC12IVx Bits15-0 ADC12 interrupt vector value ADC12IV Contents Interrupt Source Interrupt Flag Int...
Page 389 - ADC10 Introduction
ADC10 Introduction 18-3 ADC10 Figure 18−1. ADC10 Block Diagram 1001 1000 0010 0001 00110100010101100111 Sample and Hold 10−bit SAR Divider /1 .. /8 ACLK MCLK SMCLK ADC10SC TA1 TA2 TA0 Data TransferController RAM, Flash, Peripherials VR− VR+ Ve REF+ VREF+ Ve REF− VREF−/ ADC10ON INCHx REFBURST ADC10SS...
Page 391 - Figure 18−2. Analog Multiplexer; share terminals
ADC10 Operation 18-5 ADC10 18.2.2 ADC10 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channelfor conversion by the analog input multiplexer. The input multiplexer is abreak-before-make type to reduce input-to-input noise injection resulting fromchanne...
Page 392 - Internal Reference Low-Power Features
ADC10 Operation 18-6 ADC10 18.2.3 Voltage Reference Generator The ADC10 module contains a built-in voltage reference with two selectablevoltage levels. Setting REFON = 1 enables the internal reference. WhenREF2_5V = 1, the internal reference is 2.5 V. When REF2_5V = 0, thereference is 1.5 V. The int...
Page 393 - Figure 18−3. Sample Timing
ADC10 Operation 18-7 ADC10 18.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of sample inputsignal SHI. The source for SHI is selected with the SHSx bits and includes thefollowing: - The ADC10SC bit - The Timer_A Output Unit 1 - The Timer_A Output Un...
Page 394 - ADC10 Operation; Figure 18−4. Analog Input Equivalent Circuit
ADC10 Operation 18-8 ADC10 Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON =1, the selected Ax input can be modeled as an RC low-pass filter during thesampling time t sample , as shown below in Figure 18−4. An internal MUX-on input resistance R I (max. 2 ...
Page 395 - Table 18−1. Conversion Mode Summary
ADC10 Operation 18-9 ADC10 18.2.6 Conversion Modes The ADC10 has four operating modes selected by the CONSEQx bits asdiscussed in Table 18−1. Table 18−1. Conversion Mode Summary CONSEQx Mode Operation 00 Single channelsingle-conversion A single channel is converted once. 01 Sequence-of-channels A se...
Page 400 - Using the MSC Bit
ADC10 Operation 18-14 ADC10 Using the MSC Bit To configure the converter to perform successive conversions automaticallyand as quickly as possible, a multiple sample and convert function is available.When MSC = 1 and CONSEQx > 0 the first rising edge of the SHI signaltriggers the first conversion...
Page 401 - ADC10 activity test
ADC10 Operation 18-15 ADC10 18.2.7 ADC10 Data Transfer Controller The ADC10 includes a data transfer controller (DTC) to automatically transferconversion results from ADC10MEM to other on-chip memory locations. TheDTC is enabled by setting the ADC10DTC1 register to a nonzero value. When the DTC is e...
Page 402 - One-Block Transfer Mode
ADC10 Operation 18-16 ADC10 One-Block Transfer Mode The one-block mode is selected if the ADC10TB is reset. The value n inADC10DTC1 defines the total number of transfers for a block. The block startaddress is defined anywhere in the MSP430 address range using the 16-bitregister ADC10SA. The block en...
Page 404 - Two-Block Transfer Mode
ADC10 Operation 18-18 ADC10 Two-Block Transfer Mode The two-block mode is selected if the ADC10TB bit is set. The value n inADC10DTC1 defines the number of transfers for one block. The addressrange of the first block is defined anywhere in the MSP430 address range withthe 16-bit register ADC10SA. Th...
Page 406 - Continuous Transfer; Table 18−2. Maximum DTC Cycle Time
ADC10 Operation 18-20 ADC10 Continuous Transfer A continuous transfer is selected if ADC10CT bit is set. The DTC will not stopafter block one in (one-block mode) or block two (two-block mode) has beentransferred. The internal address pointer and transfer counter are set equal toADC10SA and n respect...
Page 407 - Using the Integrated Temperature Sensor; Figure 18−14. Typical Temperature Sensor Transfer Function
ADC10 Operation 18-21 ADC10 18.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog inputchannel INCHx = 1010. Any other configuration is done as if an externalchannel was selected, including reference selection, conversion-memoryselection, e...
Page 408 - ADC10 Grounding and Noise Considerations; Figure 18−16. ADC10 Grounding and Noise Considerations
ADC10 Operation 18-22 ADC10 18.2.9 ADC10 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout andgrounding techniques should be followed to eliminate ground loops, unwantedparasitic effects, and noise. Ground loops are formed when return curren...
Page 409 - ADC10 Interrupts
ADC10 Operation 18-23 ADC10 18.2.10 ADC10 Interrupts One interrupt and one interrupt vector are associated with the ADC10 asshown in Figure 18−17. When the DTC is not used (ADC10DTC1 = 0)ADC10IFG is set when conversion results are loaded into ADC10MEM. WhenDTC is used (ADC10DTC1 > 0) ADC10IFG is ...
Page 410 - ADC10 Registers; The ADC10 registers are listed in Table 18−3.
ADC10 Registers 18-24 ADC10 18.3 ADC10 Registers The ADC10 registers are listed in Table 18−3. Table 18−3. ADC10 Registers Register Short Form Register Type Address Initial State ADC10 Input enable register ADC10AE Read/write 04Ah Reset with POR ADC10 control register 0 ADC10CTL0 Read/write 01B0h Re...
Page 411 - SREFx
ADC10 Registers 18-25 ADC10 ADC10CTL0, ADC10 Control Register 0 15 14 13 12 11 10 9 8 SREFx ADC10SHTx ADC10SR REFOUT REFBURST rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 MSC REF2_5V REFON ADC10ON ADC10IE ADC10IFG ENC ADC10SC rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0...
Page 413 - INCHx; Ve; Straight binary
ADC10 Registers 18-27 ADC10 ADC10CTL1, ADC10 Control Register 1 15 14 13 12 11 10 9 8 INCHx SHSx ADC10DF ISSH rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 ADC10DIVx ADC10SSELx CONSEQx ADC10 BUSY rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−0 Modifiable only when ENC ...
Page 416 - ADC10DTC0, Data Transfer Control Register 0; One-block transfer mode
ADC10 Registers 18-30 ADC10 ADC10DTC0, Data Transfer Control Register 0 7 6 5 4 3 2 1 0 Reserved ADC10TB ADC10CT ADC10B1 ADC10 FETCH r0 r0 r0 r0 rw−(0) rw−(0) rw−(0) rw−(0) Reserved Bits7-4 Reserved. Always read as 0. ADC10TB Bit 3 ADC10 two-block mode.0 One-block transfer mode 1 Two-block transfer ...
Page 417 - ADC10DTC1, Data Transfer Control Register 1; DTC is disabled; ADC10SA, Start Address Register for Data Transfer
ADC10 Registers 18-31 ADC10 ADC10DTC1, Data Transfer Control Register 1 7 6 5 4 3 2 1 0 DTC Transfers rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) DTCTransfers Bits7-0 DTC transfers. These bits define the number of transfers in each block.0 DTC is disabled 01h-0FFh Number of transfers per...
Page 420 - DAC12 Introduction; Note: Multiple DAC12 Modules
DAC12 Introduction 19-2 DAC12 19.1 DAC12 Introduction The DAC12 module is a 12-bit, voltage output DAC. The DAC12 can beconfigured in 8- or 12-bit mode and may be used in conjunction with the DMAcontroller. When multiple DAC12 modules are present, they may be groupedtogether for synchronous update o...
Page 422 - DAC12 Operation; or V; Resolution; DAC12 Port Selection
DAC12 Operation 19-4 DAC12 19.2 DAC12 Operation The DAC12 module is configured with user software. The setup and operationof the DAC12 is discussed in the following sections. 19.2.1 DAC12 Core The DAC12 can be configured to operate in 8- or 12-bit mode using theDAC12RES bit. The full-scale output is...
Page 423 - signal is used as; DAC12 Reference Input and Voltage Output Buffers; See the device-specific data sheet for
DAC12 Operation 19-5 DAC12 19.2.2 DAC12 Reference The reference for the DAC12 is configured to use either an external referencevoltage or the internal 1.5-V/2.5-V reference from the ADC12 module with theDAC12SREFx bits. When DAC12SREFx = {0,1} the V REF+ signal is used as the reference and when DAC1...
Page 425 - DAC12 Output Amplifier Offset Calibration; Figure 19−4. Negative Offset
DAC12 Operation 19-7 DAC12 19.2.5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative.When the offset is negative, the output amplifier attempts to drive the voltagenegative, but cannot do so. The output voltage remains at zero until...
Page 426 - The DAC12LSELx bits for both DACs must be > 0; DAC12 Settling Time
DAC12 Operation 19-8 DAC12 19.2.6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit tosynchronize the update of each DAC12 output. Hardware ensures that allDAC12 modules in a group update simultaneously independent of anyinterrupt or NMI event. On the MSP4...
Page 428 - DAC12 Registers; The DAC12 registers are listed in Table 19−2:; Reset with POR
DAC12 Registers 19-10 DAC12 19.3 DAC12 Registers The DAC12 registers are listed in Table 19−2: Table 19−2. DAC12 Registers Register Short Form Register Type Address Initial State DAC12_0 control DAC12_0CTL Read/write 01C0h Reset with POR DAC12_0 data DAC12_0DAT Read/write 01C8h Reset with POR DAC12_...
Page 430 - Input Buffer
DAC12 Registers 19-12 DAC12 DAC12AMPx Bits7-5 DAC12 amplifier setting. These bits select settling time vs. currentconsumption for the DAC12 input and output amplifiers. DAC12AMPx Input Buffer Output Buffer 000 Off DAC12 off, output high Z 001 Off DAC12 off, output 0 V 010 Low speed/current Low speed...
Page 431 - Unused. These bits are always 0 and do not affect the DAC12 core.; DAC12 Data Format; 2-bit 2’s complement
DAC12 Registers 19-13 DAC12 DAC12_xDAT, DAC12 Data Register 15 14 13 12 11 10 9 8 0 0 0 0 DAC12 Data r(0) r(0) r(0) r(0) rw−(0) rw−(0) rw−(0) rw−(0) 7 6 5 4 3 2 1 0 DAC12 Data rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Unused Bits15-12 Unused. These bits are always 0 and do not affect t...
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