SMC Networks AHB SRAM/NOR - Manuals

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. vii List of Figures PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Key to timing diagram conventions ............................................................................. xii Figure 1-1 AHB MC (PL24...

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. ix Preface This preface introduces the PrimeCell AHB SRAM/NOR Memory Controller (MC) (PL241) Technical Reference Manual . It contains the following sections: • About this manual on page x • Feedback on page xiv.

Preface x Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B About this manual This is the Technical Reference Manual (TRM) for the PrimeCell AHB SRAM/NOR Memory Controller . Product revision status The r n p n identifier indicates the revision status of the product described in this m...

Preface ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. xi Appendix A Signal Descriptions Read this appendix for a description of the AHB MC input and output signals. Glossary Read the Glossary for definitions of terms used in this manual. Conventions Conventions that this manual ca...

Preface xii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Note Angle brackets can also enclose a permitted range of values. The example, <0-3>, shows that in name extensions, only one of the values 0, 1, 2, or 3 is valid. Timing diagrams The figure named Key to timing diagra...

Preface ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. xiii Prefix B Denotes AXI write response channel signals. Prefix C Denotes AXI low-power interface signals. Prefix H Denotes Advanced High-performance Bus (AHB) signals. Prefix P Denotes Advanced Peripheral Bus ( APB) signals. ...

Preface xiv Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Feedback ARM Limited welcomes feedback on the AHB MC and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier giving: • the product name • a concise e...

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-1 Chapter 1 Introduction This chapter introduces the AHB MC. It contains the following sections: • About the AHB MC on page 1-2 • Supported devices on page 1-5.

Introduction 1-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 1.1 About the AHB MC The AHB MC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral. It is developed, tested, and licensed by ARM Limited. The AHB MC takes advantage of the ...

Introduction ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-3 1.1.1 AHB interface The interface converts the incoming AHB transfers to the protocol used internally by the AHB MC. The interface has the following features: • all AHB fixed length burst types are directly translated ...

Introduction 1-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 1.1.3 SMC The SMC is a high-performance, area-optimized SRAM memory controller. The SMC is pre-configured and validated for: • the SRAM memory type • the number of SRAM memory devices • the maximum SRAM memory width. T...

Introduction ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-5 1.2 Supported devices The SMC supports SRAM/NOR, see SMC on page 1-4. The Release Note provides a specific list of memory devices tested with each configuration. Some memory devices or series of memory devices have spe...

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-1 Chapter 2 Functional Overview This chapter describes the major components of the AHB MC and how they operate. It contains the following sections: • Functional description on page 2-2 • SMC on page 2-4 • Functional operation on page...

Functional Overview 2-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 2.1 Functional description Figure 2-1 shows an AHB MC (PL241) configuration. Figure 2-1 AHB MC (PL241) configuration This section is divided into: • AHB interface • AHB to APB bridge • Clock domains on page 2-3 ...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-3 2.1.3 Clock domains The memory controller has two clock domains: AHB clock domain This is clocked by hclk , smc_aclk and reset by hresetn . Static memory clock domain This is clocked by smc_mclk0 , smc_mclk0n an...

Functional Overview 2-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 2.2 SMC Figure 2-3 shows a block diagram of the SMC. Figure 2-3 SMC block diagram The main blocks of the SMC are: • SMC interface on page 2-5 • APB slave interface on page 2-5 • Format on page 2-5 • Memory manag...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-5 2.2.1 SMC interface The SMC interface processes the incoming AHB transfers and sends them to the command format block. 2.2.2 APB slave interface The SMC has 4KB of memory allocated to it. The APB slave interface...

Functional Overview 2-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 2.2.6 Pad interface The pad interface module provides a registered I/O interface for data and control signals. It also contains interrupt generation logic. Figure 2-4 shows the SRAM pad interface external signal...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-7 2.3 Functional operation This section is divided into: • AHB interface operation • AHB to APB bridge operation on page 2-10 • Clock domain operation on page 2-11 • Low-power interface operation on page 2-12 • SM...

Functional Overview 2-8 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Undefined length INCR bursts All undefined length INCR bursts are converted to INCR bursts of length four. Many AHB masters rely on using undefined length INCR bursts to access data. If each INCR transfer is pro...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-9 If transfers are described as non-bufferable then the bridge must wait for the write response to indicate that the transfer has been completed to memory. If numerous bufferable writes are performed, followed by ...

Functional Overview 2-10 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Registered HWDATA The interconnect used within the AHB MC contains combinatorial paths for the write data. To improve the synthesis timing, HWDATA is registered and makes these paths internal to the design. Big...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-11 Figure 2-6 AHBC memory map The other fourteen 4KB regions are read as zero. The lower 16 bits of the AHB address decode the memory controller that is being used. An external AHB decoder determines where in the ...

Functional Overview 2-12 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Static memory clocking options Table 2-1 lists the static memory clocking options. 2.3.4 Low-power interface operation The memory controller has two low-power interfaces. These interfaces indicate whether the c...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-13 an active output <domain>_cactive Where: <domain> is ahb or smc. Figure 2-7 explains the protocol for the interface by showing a request to enter low-power mode. Figure 2-7 Request to enter low-powe...

Functional Overview 2-14 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B The AHB domain accepts or denies requests based on whether it is busy performing any transfers. Figure 2-9 shows that static memory controllers always accept requests after they have performed the required oper...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-15 2.4 SMC functional operation This section describes: • Operating states • Clocking and resets on page 2-16 • Miscellaneous signals on page 2-18 • APB slave interface operation on page 2-19 • Format block on pag...

Functional Overview 2-16 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B The state transitions are: Ready to Reset When reset is asserted to the smc_aclk domain, it enters the Reset state. Reset to Ready When reset is deasserted to the smc_aclk domain, it enters the Ready state. Rea...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-17 These clocks can be grouped into two clock domains: AHB domain smc_aclk is in this domain. You can only stop the smc_aclk domain signals when the SMC is in low-power mode. Memory clock domain The smc_mclk0 and ...

Functional Overview 2-18 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B You can change both reset signals asynchronously to their respective clock domain. Internally to the SMC the deassertion of the hresetn signal is synchronized to smc_aclk . The deassertion of smc_mreset0n is sy...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-19 smc_msync0 When HIGH, indicates smc_mclk0 is synchronous to smc_aclk . Otherwise they are asynchronous. Ensure that smc_msync0 is tied to the same value as smc_async0 . smc_rst_bypass Use this signal for ATPG t...

Functional Overview 2-20 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B The SMC ensures the ordering of read transfers from a single port is maintained RAR, and additionally that the ordering of write transfers from a single master is maintained WAW. SRAM memory accesses This secti...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-21 memory bursts, terminating a memory transfer at the burst boundary. Also ensure the page size is an integer multiple of the burst length, to avoid a memory burst crossing a page boundary. When the burst_align b...

Functional Overview 2-22 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 2.4.6 Memory manager operation The memory manager module is responsible for controlling the state of the SMC and the updating of chip configuration registers. This subsection describes: • Low-power operation • ...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-23 The APB registers smc_set_cycles and smc_set_opmode act as holding registers, the configuration registers within the manager are only updated if either: • the smc_direct_cmd Register indicates only a register u...

Functional Overview 2-24 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Direct commands The SMC enables code to be executed from the memory while simultaneously, from the software perspective, moving the same chip to a different operating mode. This is achieved by synchronizing the...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-25 Figure 2-12 Device pin mechanism :ULWHWLPLQJSDUDPHWHUV DQGRSHUDWLQJPRGHWR WKHPHPRU\FRQWUROOHU KROGLQJUHJLVWHUV 6WDUW :ULWHUHTXLUHGH[WHUQDOFKLS VHOHFWQXPEHUDQGUHTXLUHG PRGHUHJLVWHUYDOXHWRWKH 'LUHFW&RPPDQG5HJ...

Functional Overview 2-26 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Figure 2-13 Software mechanism :ULWHWLPLQJSDUDPHWHUV DQGRSHUDWLQJPRGHWR WKHPHPRU\FRQWUROOHU KROGLQJUHJLVWHUV 6WDUW :ULWHUHTXLUHGH[WHUQDOFKLS VHOHFWQXPEHUDQGUHTXLUHG PRGHUHJLVWHUYDOXHWRWKH 'LUHFW&RPPDQG5HJLV...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-27 2.4.7 Interrupts operation The next read to any chip select on the appropriate memory interface clears the interrupt. The interrupt outputs are generated through a combinational path from the relevant input pin...

Functional Overview 2-28 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Read data output by the memory device is also registered on the rising edge of smc_mclk0n , equivalent to the falling edge of smc_mclk0 , for asynchronous reads. For synchronous reads, read data is registered u...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-29 Figure 2-14 Asynchronous read Asynchronous read in multiplexed-mode Table 2-4 and Table 2-5 list the smc_opmode0_<0-3> and SRAM Register settings. Figure 2-15 shows a single asynchronous read transfer in ...

Functional Overview 2-30 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Note In multiplexed-mode, both address and data are output by the SMC on the smc_data_out_0[31:0] output bus. Read data is accepted on the smc_data_in_0[31:0] bus. Asynchronous write Table 2-6 and Table 2-7 lis...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-31 Asynchronous write in multiplexed-mode Table 2-8 and Table 2-9 list the smc_opmode0_<0-3> and SRAM Register settings. Figure 2-17 shows an asynchronous write in multiplexed-mode. t WC is seven cycles. t W...

Functional Overview 2-32 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Figure 2-18 shows a page read access, with an initial access time, t RC , of three cycles, an output enable assertion delay, t CEOE , of two cycles and a page access time, t PC , of one cycle. Page mode is enab...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-33 Figure 2-19 shows a burst read with the smc_wait_0 output of the memory used to delay the transfer. Note • Synchronous memories have a configuration register enabling smc_wait_0 to be asserted either on the sam...

Functional Overview 2-34 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Synchronous burst read in multiplexed-mode Table 2-14 and Table 2-15 list the smc_opmode0_<0-3> and SRAM Register settings. Figure 2-20 shows the same synchronous read burst transfer as Figure 2-19 on pag...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-35 Synchronous burst write Table 2-16 and Table 2-17 list the smc_opmode0_<0-3> and SRAM Register settings. Figure 2-21 shows a synchronous burst write transfer that is delayed by the smc_wait_0 signal. You ...

Functional Overview 2-36 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Synchronous burst write in multiplexed-mode Table 2-18 and Table 2-19 list the smc_opmode0_<0-3> and SRAM Register settings. Figure 2-22 shows the same synchronous burst write as Figure 2-21 on page 2-35,...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-37 Synchronous read and asynchronous write Table 2-20 and Table 2-21 list the smc_opmode0_<0-3> and SRAM Register settings. Figure 2-23 on page 2-38 shows the turnaround time t TR , enforced between synchron...

Functional Overview 2-38 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Figure 2-23 Synchronous read and asynchronous write Programming t RC and t WC when the controller operates in synchronous mode For t RC : • when using memory devices that are not wait-enabled, you must program ...

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-39 For t WC : • when using memory devices that are not wait-enabled, you must program t WC to be the number of clock cycles required before the first data is written, following the assertion of cs_n • when using m...

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-1 Chapter 3 Programmer’s Model This chapter describes the registers of the SMC and provides information for programming the device. It contains the following sections: • About the programmer’s model on page 3-2 • Register summary on ...

Programmer’s Model 3-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 3.1 About the programmer’s model The SMC has 4KB of memory allocated to it from a base address of 0x1000 to a maximum address of 0x1FFF . Figure 3-1 shows that the register map address range is split into the fol...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-3 3.2 Register summary Figure 3-2 shows the SMC configuration register map. Figure 3-2 SMC configuration register map Figure 3-3 shows the SMC chip< 0-3 > configuration register map: Figure 3-3 SMC chip confi...

Programmer’s Model 3-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Note Figure 3-3 on page 3-3 shows the maximum number of supported chips. If you intend to use fewer, then the highest chip configuration blocks of the correct type are read back as zero. Figure 3-4 shows the SMC ...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-5 smc_set_cycles 0x1014 WO N/A See SMC Set Cycles Register at 0x1014 on page 3-11. smc_set_opmode 0x1018 WO N/A See SMC Set Opmode Register at 0x1018 on page 3-12. smc_refresh_period_0 0x1020 R/W 0x00000000 See SMC...

Programmer’s Model 3-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 3.3 Register descriptions This section describes the SMC registers. 3.3.1 SMC Memory Controller Status Register at 0x1000 The read-only smc_memc_status Register provides information on the configuration of the SM...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-7 3.3.2 SMC Memory Interface Configuration Register at 0x1004 The read-only smc_memif_cfg Register provides information on the configuration of the memory interface. This register cannot be read in the Reset state....

Programmer’s Model 3-8 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 3.3.3 SMC Set Configuration Register at 0x1008 The write-only smc_memc_cfg_set Register enables the memory controller to be changed to Low-power state, and interrupts enabled. This register cannot be written to i...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-9 Table 3-4 lists the register bit assignments. 3.3.4 SMC Clear Configuration Register at 0x100C The write-only smc_memc_cfg_clr Register enables the memory controller to be moved out of the Low-power state, and th...

Programmer’s Model 3-10 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 3.3.5 SMC Direct Command Register at 0x1010 The write-only smc_direct_cmd Register passes commands to the external memory, and controls the updating of the chip configuration registers with values held in the se...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-11 3.3.6 SMC Set Cycles Register at 0x1014 This is the holding register for the smc_set_cycles0_<n>. The write-only smc_set_cycles Register enables the time interval to be set for holding registers before dat...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-13 Table 3-8 lists the register bit assignments. Table 3-8 smc_set_opmode Register bit assignments Bits Name Function [31:16] - Reserved, undefined, write as zero. [15:13] set_burst_align Holding register for value...

Programmer’s Model 3-14 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B [9:7] set_wr_bl Holding register for value to be written to the specific SRAM chip smc_opmode Register bls field. Encodes the memory burst length: b000 = 1 beat b001 = 4 beats b010 = 8 beats b011 = 16 beats b100...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-15 3.3.8 SMC Refresh Period 0 Register at 0x1020 The read/write smc_refresh_period_0 Register enables the AHB MC to perform refresh cycles for PSRAM devices that you connect to memory interface 0. You cannot access...

Programmer’s Model 3-16 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Table 3-10 lists the register bit assignments. 3.3.10 SMC Opmode Registers <0-3> at 0x1104, 0x1124, 0x1144, 0x1164 There is an instance of the smc_opmode Register for each chip supported. This register is ...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-17 Table 3-11 lists the register bit assignments. Table 3-11 smc_opmode Register bit assignments Bits Name Function [31:24] address_match Returns the value of this tie-off. This is the comparison value for address ...

Programmer’s Model 3-18 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 3.3.11 SMC User Status Register at 0x1200 The smc_user_status Register is a general purpose read-only register that returns the state on the smc_user_status[7:0] primary inputs. The smc_user_status Register can ...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-19 3.3.12 SMC User Configuration Register at 0x1204 The smc_user_config Register is a general purpose write-only register. This register sets the value of the smc_user_config[7:0] primary outputs. The smc_user_conf...

Programmer’s Model 3-20 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Figure 3-18 shows the correspondence between bits of the smc_ periph_id registers and the conceptual 32-bit Peripheral ID Register. Figure 3-18 smc_periph_id Register bit assignments The following section descri...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-21 SMC Peripheral Identification Register 1 The smc_periph_id_1 Register is hard-coded and the fields within the register indicate the value. Table 3-16 lists the register bit assignments. SMC Peripheral Identifica...

Programmer’s Model 3-22 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 3.3.14 SMC PrimeCell Identification Registers <0-3> at 0x1FF0-0x1FFC The smc_pcell_id Registers are four 8-bit wide registers, that span address locations 0xFF0-0FFC . The registers can conceptually be tre...

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-23 The following sections describe the smc_pcell_id Registers: • SMC PrimeCell Identification Register 0 • SMC PrimeCell Identification Register 1 • SMC PrimeCell Identification Register 2 on page 3-24 • SMC PrimeC...

Programmer’s Model 3-24 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B SMC PrimeCell Identification Register 2 The smc_pcell_id_2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignments. SMC PrimeCell Identificatio...

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 4-1 Chapter 4 Programmer’s Model for Test This chapter describes the additional logic for functional verification and production testing. It contains the following section: • SMC integration test registers on page 4-2.

Programmer’s Model for Test 4-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 4.1 SMC integration test registers Test registers are provided for integration testing. Figure 4-1 shows the SMC integration test register map. Figure 4-1 SMC integration test register map Table 4-1 list...

Programmer’s Model for Test ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 4-3 Table 4-2 lists the register bit assignments. 4.1.2 Integration Inputs Register at 0x1E04 The read-only smc_int_inputs Register enables an external master to access the inputs of the SMC using the APB in...

Programmer’s Model for Test 4-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 4.1.3 Integration Outputs Register at 0x1E08 The write-only smc_int_outputs Register enables an external master to access the outputs of the SMC using the APB interface. This register cannot be read in t...

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 5-1 Chapter 5 Device Driver Requirements This chapter contains various flow diagrams to aid in the development of a software driver for the SMC. It contains the following section: • Memory initialization on page 5-2.

Device Driver Requirements ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 5-3 Figure 5-1 SMC and memory initialization sheet 1 of 3 6WDUW 3VHXGR&RGHIRU¶VPFBVHWBF\FOHV·6XEURXWLQHLQWVHWBF\FOHVWWWWWWW^ 6KLIWHDFKSDUDPHWHUWRWKHFRUUHFWELWSRVLWLRQIRUH[DPSOH VHWBF\FOHVBYDO W_W_W_W_W_W_...

Device Driver Requirements 5-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Figure 5-2 SMC and memory initialization sheet 2 of 3 6KHHW ,V PHPRU\GHYLFH 0RGH5HJDFFHVVHGE\ DGGUHVVDQGGDWD RUDGGUHVV RQO\" 3VHXGR&RGHIRU¶VPFBGLUHFWBFPG·6XEURXWLQHLQWGLUHFWBFPGPHPBLIFKLSBVHOFPGBW...

Device Driver Requirements ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 5-5 Figure 5-3 SMC and memory initialization sheet 3 of 3 Where: x = denotes the appropriate chip select. 6KHHW 9HULI\ WKHQHZWLPLQJV DQGRSHUDWLQJ PRGH" (QG &KHFNIRUFRUUHFW VPFBVUDPBF\FOHVB[ 5HJLVWHUFR...

Signal Descriptions A-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B A.1 About the signals list This appendix lists the PL241 signals. Figure A-1 shows how the signals are grouped. Figure A-1 AHB MC PL241 grouping of signals where: AHBC = AHB Configuration signals $+%0&3/ $+%...

Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-3 A.2 Clocks and resets Table A-1 lists the clock and reset signals. Table A-1 Clocks and resets Name Type Source/ destination Description hclk Input Clock source AHB clock hresetn Input Reset source AHB clock dom...

Signal Descriptions A-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B A.3 AHB signals Table A-2 lists the AHB signals. where: <x> = 0 or C, where C = Configuration. Table A-2 AHB signals Name Type Source/ destination Description hsel<x> Input AHB Transfer is to this po...

Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-5 A.4 SMC memory interface signals Table A-3 lists the SMC memory interface signals. Table A-3 SMC memory interface signals Name Type Source/ destination Description smc_fbclk_in_0 Input Memory Fed back clock smc_...

Signal Descriptions A-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B A.5 SMC miscellaneous signals Table A-4 lists the SMC miscellaneous signals. Table A-4 SMC miscellaneous signals Name Type Source/ destination Description smc_async0 Input Tie-off AHB clock synchronous to memory...

Signal Descriptions A-8 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B A.7 Configuration signal Table A-6 lists the configuration signal. Table A-6 Configuration signal Name Type Source/ destination Description big_endian Input Tie-off Big-endian mode configuration tie-off

Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-9 A.8 Scan chains Table A-7 lists the scan chain signals. Table A-7 Scan chain signals Name Type Source/ destination Description se Input Scan chains Scan enable for all clock domains ahb_rst_bypass Input Scan cha...

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. Glossary-1 Glossary This glossary describes some of the terms used in technical documents from ARM Limited. Advanced High-performance Bus (AHB) A bus protocol with a fixed pipeline between address/control and data phases. It only suppo...

Glossary Glossary-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Advanced Peripheral Bus (APB) A simpler bus protocol than AHB. It is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Connection to the main...

Glossary ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. Glossary-3 Boundary scan chain A boundary scan chain is made up of serially-connected devices that implement boundary scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller contai...

Glossary Glossary-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B SBO See Should Be One. SBZ See Should Be Zero. SBZP See Should Be Zero or Preserved. Scan chain A scan chain is made up of serially-connected devices that implement boundary scan technology using a standard JTAG TAP...

Glossary ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. Glossary-5 Remapping Changing the address of physical memory or devices after the application has started executing. This is typically done to permit RAM to replace ROM when the initialization has been completed. Reserved A fi...