SMC Networks PL241 - Manual

SMC Networks PL241

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Table of Contents:

  • Page 2 – Technical Reference Manual; Copyright © 2006 ARM Limited. All rights reserved.
  • Page 3 – Contents
  • Page 5 – List of Tables
  • Page 7 – List of Figures
  • Page 9 – Preface; This preface introduces the
  • Page 10 – About this manual; Product revision status; Introduction; Chapter 2; Functional Overview; Chapter 3; Programmer’s Model; Chapter 4; Programmer’s Model for Test
  • Page 11 – Appendix A; Signal Descriptions; Glossary; Typographical; italic; bold
  • Page 12 – Note; Key to timing diagram conventions; Signals; Advanced eXtensible Interface; Prefix AR
  • Page 13 – Advanced High-performance Bus; Numbering; AMBA
  • Page 14 – Feedback; Feedback on this product
  • Page 15 – Chapter 1; About the AHB MC
  • Page 16 – The AHB MC is an
  • Page 17 – AHB interface; Read After Write; HWDATA; AHB to APB bridge
  • Page 18 – SMC; Pseudo Static Random Access Memory; Clock domains
  • Page 19 – Supported devices; WAIT; CRE
  • Page 21 – Functional description
  • Page 22 – This section is divided into:; See
  • Page 23 – Clock domain operation; VPFBPFON
  • Page 24 – Figure 2-3 shows a block diagram of the SMC.
  • Page 25 – SMC interface; Format; Format block; Memory manager; Memory manager operation; Memory interface; Memory interface operation
  • Page 26 – Pad interface; Figure 2-4 SMC SRAM pad interface external connections; Interrupts; input for the SRAM memory interface.
  • Page 27 – Functional operation; AHB interface operation; This section describes:; AHB fixed burst types
  • Page 28 – Undefined length INCR bursts; The bufferable bit of the; HPROT; signal determines whether the bridge must wait for a
  • Page 29 – Read after write hazard detection buffer; Write After; AHB response signals
  • Page 30 – Registered HWDATA; is registered and makes these paths; Removal of AHB error response logic
  • Page 31 – Figure 2-6 AHBC memory map; Low-power interface operation; hresetn
  • Page 32 – Static memory clocking options; Table 2-1 lists the static memory clocking options.; AHB clock domain; a request input; Table 2-1 Static memory clocking options; m x; hclk
  • Page 33 – an active output; Figure 2-7 Request to enter low-power mode
  • Page 34 – Figure 2-9 Accepting requests
  • Page 35 – SMC functional operation; Operating states; Figure 2-10 SMC aclk domain FSM; Reset; Power is applied to the device, and
  • Page 36 – Ready to Reset; Clocking
  • Page 37 – Resets
  • Page 38 – SMC User Configuration Register
  • Page 39 – APB slave interface operation
  • Page 40 – SRAM memory accesses; Standard SRAM access; The programmer’s view is a flat area of memory.; Memory address shifting; Memory burst alignment
  • Page 41 – Memory burst length; port signal
  • Page 42 – This subsection describes:; Chip configuration registers
  • Page 43 – Figure 2-11 Chip configuration registers
  • Page 44 – Direct commands
  • Page 45 – Figure 2-12 Device pin mechanism
  • Page 46 – Figure 2-13 Software mechanism
  • Page 47 – Interrupts operation; SRAM timing tables and diagrams
  • Page 48 – , equivalent to the falling edge of; Asynchronous read; , of three cycles and an output enable assertion delay, t; Table 2-2 Asynchronous read opmode chip register settings; mw; Value
  • Page 49 – Figure 2-14 Asynchronous read; Asynchronous read in multiplexed-mode; Figure 2-15 Asynchronous read in multiplexed-mode
  • Page 50 – Asynchronous write; Figure 2-16 Asynchronous write
  • Page 51 – Asynchronous write in multiplexed-mode; Figure 2-17 shows an asynchronous write in multiplexed-mode. t; Figure 2-17 Asynchronous write in multiplexed-mode; Asynchronous page mode read; Table 2-10 Page read opmode chip register settings
  • Page 52 – Figure 2-18 shows a page read access, with an initial access time, t; an output enable assertion delay, t; , of two cycles and a page access time, t; Multiplexed-mode page accesses are not supported.; Synchronous burst read; Table 2-12 Synchronous burst read opmode chip register settings
  • Page 53 – Figure 2-19 Synchronous burst read
  • Page 54 – Synchronous burst read in multiplexed-mode; Figure 2-20 Synchronous burst read in multiplexed-mode
  • Page 55 – Synchronous burst write; Figure 2-21 Synchronous burst write
  • Page 56 – Synchronous burst write in multiplexed-mode; Figure 2-22 Synchronous burst write in multiplexed-mode
  • Page 57 – Synchronous read and asynchronous write; Figure 2-23 on page 2-38 shows the turnaround time t
  • Page 58 – Figure 2-23 Synchronous read and asynchronous write; Programming t; and t; when the controller operates in synchronous mode
  • Page 59 – wait
  • Page 61 – About the programmer’s model
  • Page 62 – The SMC has 4KB of memory allocated to it from a base address of; SMC configuration registers; Figure 3-1 SMC register map
  • Page 63 – Register summary; Figure 3-2 shows the SMC configuration register map.
  • Page 64 – Figure 3-4 shows the SMC user configuration memory register map.; SMC Memory Controller Status Register at
  • Page 65 – Name
  • Page 66 – Register descriptions; This section describes the SMC registers.; SMC Memory Controller Status Register at 0x1000; Table 3-2 lists the register bit assignments.
  • Page 67 – SMC Memory Interface Configuration Register at 0x1004; Table 3-3 lists the register bit assignments.; Bits; Returns the value of the
  • Page 68 – SMC Set Configuration Register at 0x1008; memory_chips0 Returns
  • Page 69 – Table 3-4 lists the register bit assignments.; SMC Clear Configuration Register at 0x100C; Table 3-5 lists the register bit assignments.
  • Page 70 – SMC Direct Command Register at 0x1010; Table 3-6 lists the register bit assignments.
  • Page 71 – Table 3-7 describes register holding, see
  • Page 73 – Table 3-8 lists the register bit assignments.; byte lane strobe
  • Page 74 – Encodes the memory burst length:
  • Page 75 – Table 3-9 lists the register bit assignments.
  • Page 76 – Table 3-10 lists the register bit assignments.
  • Page 77 – Table 3-11 lists the register bit assignments.
  • Page 78 – SMC User Status Register at 0x1200; read in all states. Figure 3-16 shows the register bit assignments.
  • Page 79 – SMC User Configuration Register at 0x1204; Table 3-13 lists the register bit assignments.; SMC Peripheral Identification Register 3
  • Page 80 – The following section describe the smc_periph_id Registers; SMC Peripheral Identification Register 0; Reserved, read undefined
  • Page 81 – SMC Peripheral Identification Register 1
  • Page 82 – . The register can be accessed with one
  • Page 83 – These registers cannot be read in the Reset state.; SMC PrimeCell Identification Register 0
  • Page 84 – SMC PrimeCell Identification Register 2
  • Page 85 – SMC integration test registers
  • Page 86 – Test registers are provided for integration testing.; Figure 4-2 shows the register bit assignments.; SMC Integration Configuration Register at 0x1E00
  • Page 87 – Table 4-2 lists the register bit assignments.; Integration Inputs Register at 0x1E04; Figure 4-3 shows the register bit assignments.
  • Page 88 – Integration Outputs Register at 0x1E08; Figure 4-4 shows the register bit assignments.
  • Page 89 – Chapter 5; Device Driver Requirements; Memory initialization
  • Page 91 – Figure 5-1 SMC and memory initialization sheet 1 of 3
  • Page 92 – Figure 5-2 SMC and memory initialization sheet 2 of 3
  • Page 93 – Figure 5-3 SMC and memory initialization sheet 3 of 3
  • Page 96 – About the signals list; Figure A-1 AHB MC PL241 grouping of signals
  • Page 97 – Clocks and resets; Table A-1 lists the clock and reset signals.
  • Page 98 – AHB signals; Table A-2 AHB signals
  • Page 99 – SMC memory interface signals; Table A-3 lists the SMC memory interface signals.
  • Page 100 – SMC miscellaneous signals; Table A-4 lists the SMC miscellaneous signals.
  • Page 102 – Configuration signal; Table A-6 lists the configuration signal.; Input
  • Page 103 – Scan chains; Table A-7 Scan chain signals
  • Page 105 – See also
  • Page 106 – AHB
  • Page 107 – Boundary scan chain; TDI; and; TDO; , through which test data is shifted. Processors can contain
  • Page 108 – Should Be Zero or Preserved.; to enable you to access selected parts of the device.
  • Page 109 – Remapping
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Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

PrimeCell

®

AHB SRAM/NOR

Memory Controller (PL241)

Revision: r0p1

Technical Reference Manual

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Summary

Page 2 - Technical Reference Manual; Copyright © 2006 ARM Limited. All rights reserved.

ii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Copyright © 2006 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Proprietary Notice Words and logos...

Page 3 - Contents

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. iii Contents PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Preface About this manual .......................................................................................... xFeedback ......................

Page 5 - List of Tables

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. v List of Tables PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Change History ............................................................................................................. ii Table 2-1 Stat...

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