Page 6 - CONTENTS; DIFFERENCES BETWEEN
- i - CONTENTS CHAPTER 1. GENERAL ............................................................................................................................... 1 1.1 OUTLINE OF FUNCTIONS . ................................................................................................................
Page 7 - Differences Between
- ii - CHAPTER 4. INTERNAL CPU FUNCTIONS ........................................................................................... 31 4.1 PROGRAM COUNTER (PC) ........................................................................................................................... 31 4.2 PROGRAM ...
Page 9 - Change of
- iv - CONTENTS OF FIGURES Fig. No Title Page 3-1 Static RAM Address Updating Method ............................................................................................. 25 4-1 Program Counter Configuration .......................................................................................
Page 11 - CONTENTS OF TABLES; Title
- vi - CONTENTS OF TABLES Table No. Title Page 1-1 Differences Between µ PD75402A and µ PD75402, 75P402 ................................................................. 4 2-1 Port Pin List .................................................................................................................
Page 12 - Remarks
1 CHAPTER 1. GENERAL Name Program Memory Data Memory µ PD75402A 1920 × 8 (mask ROM) 64 × 4 (RAM) µ PD75P402 1920 × 8 (one-time PROM) 64 × 4 (RAM) CHAPTER 1. GENERAL The µ PD75402A, 75P402 is a CMOS 4-bit single-chip microcomputer adopting the 75X architecture. With its built- in NEC standard serial ...
Page 13 - OUTLINE OF FUNCTIONS
2 CHAPTER 1. GENERAL Item Description 1.1 OUTLINE OF FUNCTIONS Number of basicinstructions Instructionexecution time Built-inmemory General register Accumulators I/O line Pull-up resistor Clock output Timer/Counter Serial interface Vectoredinterrupt Test input Standby Instruction set Package 37 • 0....
Page 14 - Standard
3 CHAPTER 1. GENERAL Ordering Code Package Program Memory µ PD75402AC- ××× 28-pin plastic DIP (600 mil) Mask ROM µ PD75402ACT- ××× 28-pin plastic shrink DIP (400 mil) µ PD75402AGB- ××× -3B4 44-pin plastic QFP ( ■ ■ 10mm) µ PD75P402C 28-pin plastic DIP (600 mil) One-time PROM µ PD75P402CT 28-pin plas...
Page 15 - Table 1-1 shows the differences between the; Table 1-1 Differences Between; The
4 CHAPTER 1. GENERAL Instruction execution time Port 5’s pull-up resistor Supply voltage Operating temperature range Package 1.3 DIFFERENCES BETWEEN µ PD75402A AND µ PD75402, 75P402 Table 1-1 shows the differences between the µ PD75402A and the µ PD75402, 75P402. Otherwise the µ PD75402A and the µ P...
Page 16 - BLOCK DIAGRAM; Parentheses for the
5 CHAPTER 1. GENERAL BASICINTERVALTIMER SERIALINTERFACE INTERRUPTCONTROL INTBT INTCSI SI SO/SB0 SCK INT0 INT2 PROGRAMCOUNTER(11) ROM (PROM) PROGRAM MEMORY 1920 × 8 bits ALU CY SP (5) DECODE ANDCONTROL GENERAL REG. RAM DATA MEMORY 64 x 4 bits PORT0 PORT1 PORT2 PORT3 PORT5 PORT6 4 4 2 4 4 4 P00-P03 P1...
Page 17 - RESET
6 CHAPTER 1. GENERAL 1.5 PIN CONFIGURATION 1.5.1 28-Pin Plastic Dip (600 mil), Shrink Dip (400 mil) (1) Normal operating mode P00 to P03 : Port 0 SCK : Serial clock input/output P10, P12 : Port 1 SO/SB0 : Serial output/input/output P20 to P23 : Port 2 SI : Serial input P30 to P33 : Port 3 PCL : Cloc...
Page 18 - PROM mode; CE; : Program power supply
7 CHAPTER 1. GENERAL (2) PROM mode A0 to A14 : Address input O0 to O7 : Data input/output CE : Chip enable input OE : Output enable input V DD : Power supply V PP : Program power supply V SS : Ground V PP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 V SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22...
Page 19 - Normal operating mode; is to be set to the GND potential.
8 CHAPTER 1. GENERAL P30 P31 P32 V SS P33 P60 P61 NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 44 43 42 41 40 39 38 37 36 35 34 P01/SCK P00 RESET NC (V PP ) * NC NC NC V DD X1 X2 NC P62 P63 P20 P21 P23 NC V SS NC P22/PCL P10/INT0 P12/INT2 P53 ...
Page 21 - CHAPTER 2. PIN FUNCTIONS; pin level as shown in the table below.; Operating Mode
CHAPTER 2. PIN FUNCTIONS 10 CHAPTER 2. PIN FUNCTIONS The µ PD75402A operates by the pin functions in the normal operating mode. For the µ PD75P402’s pin functions, the 2 modes of the normal operating mode ( µ PD75402A mode) and the PROM mode are available. The operating mode switches according to th...
Page 22 - In the; For the status of each pin at reset, see CHAPTER 8 “RESET FUNCTION”.
11 CHAPTER 2. PIN FUNCTIONS Functions A 4-bit input port (Port 0). For P01 to P03, it is designatable to build in the pull-up resistor by software in 3-bit units. A 2-bit input port (Port 1). P10 is built in with the noise eliminator by the sampling clock. P12 is built in with the noise eliminator b...
Page 23 - If using the
CHAPTER 2. PIN FUNCTIONS 12 Dual-Function Pin P10 P12 P03 P02/SB0 P01 P02/SO P22 2.1.2 List of Pins Other Than Port Pins Table 2-2 List of Pins Other than Port Pins Pin Name INT0 INT2 SI SO SCK SB0 PCL X1, X2 RESET V DD V SS NC* 8 Functions An edge-detected vectored interrupt request input pin (dete...
Page 24 - Pin Port 1; NORMAL OPERATING MODE; P10 can be built in with the pull-up resistor.
13 CHAPTER 2. PIN FUNCTIONS Port 0 Dual-Function Pin Port 1 Dual-Function Pin P00 P10 INT0 P01 SCK P12 INT2 P02 SO/SB0 P03 SI 2.2 NORMAL OPERATING MODE 2.2.1 P00 to P03 (Port 0) ..... SCK, SO/SB0, SI Dual-Function Input P10, P12 (Port 1) ..... INT0, INT2 Dual-Function Input P00 to P03 are the 4-bit ...
Page 26 - It is also possible to supply the clock from the exterior.; A positive power supply pin.
15 CHAPTER 2. PIN FUNCTIONS V DD V DD X1 X2 PD75402A µ Crystal Resonatoror Ceramic Oscillator X1 X2 PD74HC04 µ ExternalClock (Standard 4.194304 MHz) PD75402A µ 2.2.7 X1, X2 (Crystal) The built-in clock oscillation crystal/ceramic input. It is also possible to supply the clock from the exterior. (a) ...
Page 28 - PIN INPUT/OUTPUT CIRCUITS; Pin; A circle
17 CHAPTER 2. PIN FUNCTIONS Input/Output Type µ PD75402A µ PD75P402 P00 B P01/SCK F - A P02/SO/SB0 F - B P03/SI B - C P10/INT0 B P12/INT2 B - C P20, P21, P23 P22/PCL P30 to P33 E - B P50 to P53 M M - A P60 to P63 E - B RESET B 2.4 PIN INPUT/OUTPUT CIRCUITS The input/output circuit of each pin is sho...
Page 29 - Type B
CHAPTER 2. PIN FUNCTIONS 18 V DD P-ch P.U.R.enable IN P.U.R. V DD P-ch N-ch OUT data outputdisable V DD P-ch N-ch IN Type A (for Types E - B) Type B Type B - C Type D (for Type E - B, F - A, Y - D) Type E - B Type F - A IN P. U. R : Pull-Up Resistor P. U. R : Pull-Up Resistor P. U. R : Pull-Up Resis...
Page 30 - data
19 CHAPTER 2. PIN FUNCTIONS V DD IN/OUT N-ch (+10 V Withstand Voltage) data outputdisable P.U.R(Mask Option) IN/OUT N-ch (+10 V Withstand Voltage) data outputdisable Type F - B Type M Type M - A P. U. R : Pull-Up Resistor Middle-High Voltage Input Buffer (+10 V Withstand Voltage) P. U. R : Pull-Up R...
Page 31 - UNUSED PIN TREATMENT
CHAPTER 2. PIN FUNCTIONS 20 V DD V DD V DD V DD Diode withSmall V F P00, RESET P00, RESET 2.5 UNUSED PIN TREATMENT Pin P00 P01 to P03 P10 and P12 P20 to P23 P30 to P33 P50 to P53 P60 to P63 NC * If using the µ PD75P402 and the printed circuit board commonly, the NC pins should be connected directly ...
Page 32 - CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP; DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES
CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 21 CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP The µ PD75402A’s architecture is a subset of the 75X architecture. Its features are outlined below. 3.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES 3.1.1 Data Memory Bank Configuration Th...
Page 40 - IE
CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 29 W W Bit 2 is fixed to 0. W W R/W R/W R/W R/W R/W R/W R/W R/W FB2H FB3H FB4H FB8H FBDH FBEH FBFH Bit 0 is fixed to 0. F80H F85H F86H W b3 b2 b1 b0 Stack pointer (SP) Basic interval timer mode register (BTM) Basic interval timer (BT) Table 3-4 µ PD...
Page 42 - The program counter operates as follows.; CHAPTER 4. INTERNAL CPU FUNCTIONS
CHAPTER 4. INTERNAL CPU FUNCTIONS 31 The program counter operates as follows. • Normal operation The content is incremented automatically according to the number of bytes of the instruction every time one is executed. • Branch instruction (BR, BRCB) execution The immediate data indicating the addres...
Page 44 - Data Memory
CHAPTER 4. INTERNAL CPU FUNCTIONS 33 4.3 DATA MEMORY (RAM) The data memory consists of the data and peripheral hardware areas as shown in Fig. 4-3. Fig. 4-3 Data Memory Map (1) Data area The µ PD75402A’s data area consists of the static RAM (64 words × 4 bits). The data area is used to store process...
Page 46 - as a register or not.
CHAPTER 4. INTERNAL CPU FUNCTIONS 35 4.4 GENERAL REGISTER ..... 4 × 4 BITS The general register is assigned to a specific address of the data memory. There are four 4-bit registers (H, L, X, A). While each general register is operated per 4 bits, HL and XA make up register pairs, each of which is op...
Page 47 - CY
36 CHAPTER 4. INTERNAL CPU FUNCTIONS 4.5 ACCUMULATOR In the µ PD75402A, the A register and the XA register pair function as accumulators. The 4-bit data process instruction is executed mainly by the A register and the 8-bit data process instruction is executed mainly by the XA register pair. In the ...
Page 48 - Address
CHAPTER 4. INTERNAL CPU FUNCTIONS 37 4.6 STACK POINTER (SP) ..... 8 BITS The µ PD75402A uses a static RAM as the stack memory (LIFO format). The 8-bit register holding the top address information of such a stack memory area is the stack pointer (SP). Fig. 4-7 shows its format. As the SP’s high-order...
Page 50 - shows its configuration.; Fig. 4-10 Program Status Word Configuration; IST0 turns 0 and SK0 to SK2 and CY turn indeterminate at RESET input.; Table 4-1 Carry Flag Manipulation Instructions; Skip Flag
CHAPTER 4. INTERNAL CPU FUNCTIONS 39 4.7 PROGRAM STATUS WORD (PSW) ..... 8 BITS The program status word (PSW) consists of various flags concerning closely the processor operation. Fig. 4-10 shows its configuration. Saved to the stack memory per 8 bits at the interrupt acceptance and restored from th...
Page 52 - CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS; DIGITAL INPUT/OUTPUT PORTS; Note
41 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 DIGITAL INPUT/OUTPUT PORTS The µ PD75402A has the following digital input/output ports on chip: Ports 0 through 3, 5 and 6. The µ PD75402A uses memory mapped I/O, and all input/output ports are mapped onto data ...
Page 53 - Port; LED direct drive capability
42 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.1 Digital Input/Output Port Types, Characteristics and Configuration The different types of digital input/output ports are shown in Table 5-1, and the configuration of each port is shown in Figs. 5-2, 5-3, 5-4 and 5-5. Table 5-1 Digital Input/Output Po...
Page 55 - Input Buffer
44 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-3 Configuration of Port 3 Remarks n = 0 to 3 Input Buffer PM 3 n=0 PM 3 n=1 M PX Output Latch PM 3 n PMGA Bit n OutputBuffer POGABit 3 PO3 P-ch Pull-UpResistor V DD P 3 n Internal Bus
Page 57 - units by PMGB for ports 2 and 5, and by PMGA for port 6.
46 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-5 Configuration of Port 5 Pull-Up Resistors( M a s k O p t i o n ; µ P D 7 5 4 0 2 A Only) 5.1.2 Input/Output Mode Setting The input/output mode for each input/output port is set by a port mode register as shown in Fig. 5-6. For port 3, input/output...
Page 58 - As all the input/output ports in the
47 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-6 Format of Port Mode Registers Port Mode Register Group A Port Mode Register Group B Specification 0 Input mode (output buffer off) 1 Output mode (output buffer on) Address 7 6 5 4 3 2 1 0 Symbol FE8H PM63 PM62 PM61 PM60 PM33 PM32 PM31 PM30 PMGA P3...
Page 62 - Table 5-4 Internal Pull-Up Resistor Specification for Each Port; PD75P402, pull-up resistors cannot be incorporated into port 5.
51 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.5 Internal Pull-up Resistors The µ PD75402A can incorporate internal pull-up resistors for all port pins except P00 and P10. The µ PD75P402 can incorporate internal pull-up resistors for all port pins except P00, P10, and P50 through P53. As shown in T...
Page 65 - Selector
54 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.2 CLOCK GENERATION CIRCUIT The clock generation circuit supplies various clocks to the CPU and peripheral hardware, and controls the operating mode of the CPU. 5.2.1 Clock Generation Circuit Configuration The configuration of the clock generation circuit...
Page 66 - Example
55 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.2.2 Clock Generation Circuit Function and Operaion The clock generation circuit generates the CPU clock ( Φ ) and various clocks for supply to peripheral hardware, and controls the CPU operating mode, such as standby mode etc. Clock generation circuit op...
Page 68 - Long connection circuit wiring; PORTn
57 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) System clock oscillation circuit The system clock oscillation circuit oscillates by means of a crystal resonator or ceramic resonator connected to the X1 and X2 pins (standard: 4.194304 MHz). An external clock can also be input. Fig. 5-12 System Clock ...
Page 69 - Signal line close to varyin high current; Signal is picked up.
58 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-13 Example of Poor Resonator Connection Circuit (2/2) (c) Signal line close to varyin high current (d) Current flows an oscillator power supply line. (potentials at A, B and C fluctuate.) Highcurrent X1 X2 V DD V DD µ PD75402A X1 X2 A V DD V DD PORT...
Page 71 - As the PCC is set in 0 by RESET input,; Table 5-5 Maximum Time Required for Change of CPU Clock; PCC Before Change; When standby mode is not set until; after Power-On Reset; RESET Input Signal
60 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS As the PCC is set in 0 by RESET input, Φ is reset-started at the slowest speed (state in which the operating voltage range is wide). For this reason, in a system with a slow supply voltage rise (such as a system with a high- capacitance capacitor connected...
Page 73 - PD75402 is shown below. Setting of bit 1 of the PCC is; PD75402 Processor Clock Control Register Format
62 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Next, the processor clock control register (PCC) of the µ PD75402 is shown below. Setting of bit 1 of the PCC is performed by a 4-bit memory handling instruction. At this time, ensure that bits 3, 2 and 0 are reset to “0” so that the pattern “00 × 0” is wr...
Page 74 - The configuration of the clock output circuit is shown in Fig. 5-18.; Fig. 5-18 Clock Output Circuit Configuration; that a short pulse is not output.
63 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to supply clock pulses to peripheral LSIs, etc. 5.3.1 Clock Output Circuit Configuration The configuration of the clock output circuit is shown in Fig....
Page 75 - CLOM is a 4-bit register used to control clock output.; Fig. 5-19 Clock Output Mode Register Format
64 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.3.2 Clock Output Mode Register (CLOM) CLOM is a 4-bit register used to control clock output. CLOM is set by a 4-bit memory handling instruction. Bit handling instructions cannot be used. Also, this register cannot be read. RESET input clears CLOM to zero...
Page 77 - Basic Interval Timer Configuration; The configuration of the basic interval timer is shown in Fig. 5-21.; Fig. 5-21 Basic Interval Timer Configuration; Instruction execution
66 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4 BASIC INTERVAL TIMER The µ PD75402A is equipped with an 8-bit basic interval timer which has the following functions: (a) Standard time generation (2 different time intervals) (b) Reading counter contents This basic interval timer can also be used as a...
Page 78 - MOV; Fig. 5-22 Basic Interval Timer Mode Register Format
67 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.2 Basic Intercal Timer Mode Register (BTM) BTM is a 4-bit register which controls the operation of the basic interval timer. BTM is set by a 4-bit memory handling instruction. Bit operations are not possible. Example To set the interrupt generation int...
Page 80 - Module 1
69 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.4 Examples of Basic Interval Timer Applications Example 1. In this example the basic interval timer is enabled, and the interrupt generation interval is set to 1.95 ms (at 4.19 MHz operation). SEL MB15 MOV A, #1111B MOV BTM,A ; Setting and start EI ; E...
Page 81 - Operation-halted mode; Serial data transfer is performed MSB-first.
70 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.5 SERIAL INTERFACE 5.5.1 Serial Interface Functions The µ PD75402A incorporates a clocked 8-bit serial interface, with the following three modes available. (1) Operation-halted mode This mode is used when no serial transfer is to be performed, and allows...
Page 82 - This mode conforms to the NEC serial bus format.; Fig. 5-23 Example of SBI System Configuration
71 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) SBI mode (serial bus interface mode) In the SBI mode, communication is performed with multiple devices by means of two lines: The serial clock (SCK) and the serial data bus (SB0). This mode conforms to the NEC serial bus format. In the SBI mode, the se...
Page 84 - Selects the serial clock to be used.; Serial clock counter; transmission/reception has been performed.
73 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (1) Serial operating mode register (CSIM) CSIM is an 8-bit register which specifies the serial interface operating mode, serial clock, wake-up function, etc. (See 5.5.3 (1) “Serial operating mode register” for details.) (2) Serial bus interface control reg...
Page 85 - • In SBI mode; Serial clock control circuit; the internal system clock is used.; Register Functions; by bit using the individual bit names.
74 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (8) INTCSI control circuit Controls the generation of interrupt requests. In the following case, the interrupt requests (INTCSI) are generated and interrupt request flags (IRQCSI) are set (see Fig. 6-1 “Interrupt Control Circuit Block Diagram”). • In 3-wir...
Page 86 - Serial interface operating mode selection bit (W)
75 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-25 Serial Operating Mode Register (CSIM) Format (1/2) Address 7 6 5 4 3 2 1 0 Symbol FE0H CSIE COI WUP 0 CSIM3 0 CSIM1 0 CSIM Serial Clock Selection Bit (W) Serial Interface Operating Mode Selection Bit (W) Wake-up Function Specification Bit (W) Sig...
Page 92 - A serial transfer is started by writing data to SIO.; Fig. 5-27 Configuration Around Shift Register; been written into the shift register.
81 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) Shift register (SIO) The configuration around the shift register is shown in Fig. 5-27. SIO is an 8-bit register which carries out parallel- to-serial conversion and performs serial transmission/reception (shift operations) in synchronization with the ...
Page 95 - The P01/SCK pin status depends on the CSIM1 setting as shown below.; Register setting; • Serial bus interface control register (SBIC)
84 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Serial clock selection bit (W) The P01/SCK pin status depends on the CSIM1 setting as shown below. CSIM1 P01/SCK Pin Status 0 High impedance 1 High level The following procedure should be used to clear CSIE during a serial transfer. ➀ Clear the interrupt e...
Page 96 - Reset input clears the CSIM register to 00H.; Read only
85 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (a) Serial operating mode register (CSIM) When the 3-wire serial I/O mode is used, CSIM is set as shown below (see 5.5.3 (1) “Serial operating mode register” for full details of CSIM). CSIM is manipulated by 8-bit memory manipulation instructions. Bit mani...
Page 98 - SBIC is manipulated by bit manipulation instructions.; Command trigger bit; Write only
87 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (b) Serial bus interface control register (SBIC) When the 3-wire serial I/O mode is used, SBIC is set as shown below (see 5.5.3 (2) “Serial bus interface control register” for full details of SBIC). SBIC is manipulated by bit manipulation instructions. Res...
Page 99 - bit by bit in synchronization with the serial clock.
88 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) Communication operation In the 3-wire serial I/O mode, data transmission/ reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Shift register shift operations are performed in synchron...
Page 100 - following clocks can be selected.; Signals
89 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) Serial clock selection Serial clock selection is performed by setting bit 1 of the serial operating mode register (CSIM). Either of the following clocks can be selected. Table 5-6 Serial Clock Selection and Use (in 3-Wire Serial I/O Mode) Serial Clock ...
Page 101 - Start of transfer
90 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (5) Data transfer order The µ PD75402A 3-wire serial I/O mode differs from that of other 75X series products in that it is not possible to switch between MSB and LSB as the first bit. Serial transfer is performed MSB-first. Fig. 5-31 Shift Register (SIO) a...
Page 104 - OR state. The serial data bus line requires a pull-up resistor.; Fig. 5-32 Example of SBI Serial Bus System Configuration
93 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.5.6 SBI Mode Operation The SBI (serial bus interface) is a high-speed serial interface which conforms to the the NEC serial bus format. The SBI is a single-master high-speed serial bus. Its format includes the addition of bus configuration functions to t...
Page 105 - software is very large.; Address/command/data differentiation function; Identifies serial data as an address, command or actual data.
94 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (1) SBI functions Since conventional serial I/O methods have only data transfer functions, when a serial bus is configured with multiple devices connected a large number of ports and wires are required for Chip Select signal and command/ data differentiati...
Page 106 - the configuration shown below.; Address Transfer
95 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) SBI definition The SBI serial data format and the meaning of the signals used are explained in the following section. Serial data transmitted via the SBI is classified into three types: Commands, addresses and data. Serial data forms a frame with the c...
Page 107 - hardware to detect the bus release signal.; Slave incorporate hardware to detect the command signal.
96 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS SCK SB0 “H” The bus release signal indicates that the master is about to send an address to a slave. Slaves incorporate hardware to detect the bus release signal. (b) Command signal (CMD) The command signal indicates that the SB0 line has changed from high...
Page 108 - disconnect directive is received from the master.
97 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (c) Address An address is 8-bit data output by the master to slaves connected to the bus line in order to select a particular slave. Fig. 5-36 Address SCK SB0 Bus Release Signal Command Signal Address 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 The 8-bit data ...
Page 109 - by address transmission.; communication specifications.
98 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (d) Command & data The master performs command transmission to or data transmission/reception to/from the slave selected by address transmission. Fig. 5-38 Command SCK SB0 Command Signal Command 1 2 3 4 5 6 7 8 C7 C6 C5 C4 C3 C2 C1 C0 Fig. 5-39 Data SC...
Page 110 - not to have been performed correctly.
99 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (e) Acknowledge signal (ACK) The acknowledge signal is used to confirm serial data reception between the sender and receiver. Fig. 5-40 Acknowledge Signal The acknowledge signal is a one-shot pulse synchronized with the fall of SCK after an 8-bit data tran...
Page 111 - master automatically terminates output of the SCK serial clock.
100 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (f) Busy signal (BUSY), ready signal (READY) The busy signal notifies the master that a slave is preparing for data transmission/reception. The ready signal notifies the master that a slave is ready for data transmission/reception. Fig. 5-41 Busy Signal &...
Page 116 - Disablin of automatic busy signal output; Serial clock selection
105 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Busy enable bit (R/W) 0 ➀ Disablin of automatic busy signal output ➁ Busy signal output is stopped in synchronization with the fall of SCK immediatelyafter execution ofthe clearing instruction. The busy signal is output in synchronization with the fall or...
Page 129 - XCH
118 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (10) Start of transfer When the following two conditions are met a serial transfer is started by setting transfer data in the shift register (SIO). • The serial interface operatio enable/disable bit (CSIE) = 1. • After an 8-bit serial transfer, the intern...
Page 130 - Serial bus configuration; Slave CPU
119 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS V DD SB0 (SB1) SCK SB0 (SB1) SCK SB0 SCK SB0 (SB1) SCK (12) SBI mode application This section presents examples of applications in which serial data communication is performed in SBI mode. In these application examples, the µ PD75402A is operated as a sla...
Page 132 - READ command; is interpreted as a 256-byte data transfer specification.
121 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Remarks M : Output by master S : Output by slave After the slave receives the data length, if the transmissible data is equal to or greater than that data length, the slave returns ACK. If the data is insufficient, ACK is not returned and an error is gene...
Page 133 - the slave that all the data has been correctly transferred.
122 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS After the slave receives the data length, if the area for storing the receive data is at least as large as that data length, the slave returns ACK. If the data storage area is too small, ACK is not returned and an error is generated. When all the data has...
Page 134 - The format of the status byte returned by the slave is shown below.
123 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS ➂ STATUS command This command is used to read the status of the currently selected slave. Fig. 5-57 STATUS Command Transfer Format M S STATUS ACK Command S S Status ACK Data Remarks M : Output by master S : Output by slave The format of the status byte re...
Page 136 - Error Data
125 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (iv) Error occurrence Operation in the event of an error in communication is described below. A slave indicates the occurrence of an error by failing to return ACK to the master. When an error occurs, the status bit indicating the occurrence of an error i...
Page 137 - CHAPTER 6. INTERRUPT FUNCTIONS; On the; INTERRUPT CONTROL CIRCUIT CONFIGURATION
126 CHAPTER 6. INTERRUPT FUNCTIONS CHAPTER 6. INTERRUPT FUNCTIONS On the µ PD75402A there are 3 vectored interrupt sources and one testable input, enabling a wide variety of applications to be handled. Moreover, the µ PD75402A’s interrupt control circuit has the following special features, making po...
Page 140 - INTERRUPT CONTROL CIRCUIT HARDWARE; Interrupt request flag & interrupt enable flag
129 CHAPTER 6. INTERRUPT FUNCTIONS Interrupt Request Flag IRQBT IRQ0 IRQCSI IRQ2 6.3 INTERRUPT CONTROL CIRCUIT HARDWARE (1) Interrupt request flag & interrupt enable flag There are four interrupt request flags (IRQ ××× ) corresponding to the interrupt sources (interrupt: 3, test: 1) as follows. ...
Page 141 - Therefore, pulses narrower than the width of the 2 cycles (2t; ) of sampling clock are eliminated as noise,
130 CHAPTER 6. INTERRUPT FUNCTIONS (2) External interrupt input pin hardware The configuration of INT0 and INT2 is shown in Fig. 6-3. Fig. 6-3 Configuration of INT0 and INT2 4 IM0 InputBuffer Input Buffer with Hysteresis Characteristics Internal Bus INT2/P12 INT0/P10 Sampling ClockNoise Elimina-tion...
Page 142 - must be of sufficient width to avoid being eliminated as noise.
131 CHAPTER 6. INTERRUPT FUNCTIONS Fig. 6-4 INT0 Noise Elimination Circuit Input/Output Timing Remarks t SMP = t CY or 64/f XX Specification of the detected edge of the INT0 input and selection of the sampling clock is performed by the edge detection mode register (IM0). As signals are also input vi...
Page 143 - IME is manipulated by the EI/DI instructions.
132 CHAPTER 6. INTERRUPT FUNCTIONS The format of the edge detection mode register (IM0) which is used to select the detected edge is shown in Fig. 6-6. IM0 is set by 4-bit memory handling instructions. On an RESET input, all bits of IM0 are cleared to 0 and the rising edge is specified for INT0. Fig...
Page 144 - in multiple interrupt.; Table 6-3 IST0 Interrupt Servicing Status
133 CHAPTER 6. INTERRUPT FUNCTIONS (4) Interrupt status flag The interrupt status flag (IST0) is the flag which shows the status of the processing currently being executed by the CPU, and is contained in the PSW. The interrupt priority control circuit performs interrupt control according to the cont...
Page 146 - routine program are as shown below.
135 CHAPTER 6. INTERRUPT FUNCTIONS 6.5 MACHINE CYCLES BEFORE INTERRUPT SERVICING On the 75X, the machine cycles from the setting of the interrupt request flag (IRQn) until execution of the interrupt routine program are as shown below. (1) When IRQn is set during execution of an interrupt control ins...
Page 147 - D: Execution of interrupt routine; performed following the instruction being executed.
136 CHAPTER 6. INTERRUPT FUNCTIONS (2) When IRQn is set during execution of an instruction other than an interrupt control instruction (a) When IRQn is set in the last machine cycle of the instruction being executed In this case, the interrupt routine program is executed after 3 machine cycles of in...
Page 149 - All interrupts disabled and status 0 set by RESET input.
138 CHAPTER 6. INTERRUPT FUNCTIONS (2) Example using INTBT, INT0 (falling edge active), and INTCSI ➀ Reset ➁ MOV MOVCLR1 ➂ EI EIEIEI ➄ RETI <INT0 Service Program> ➃ INT0 A, #1IM0, AIRQ0IEBTIE0IECSI ; MBE = 0 Status 0 Status 1 Status 0 <Main Program> ➀ All interrupts disabled and status 0...
Page 150 - Same as
139 CHAPTER 6. INTERRUPT FUNCTIONS (3) Pending interrupt execution - interrupt input in interrupt disabled state Reset ➂ INTCSI <INT0 Service Program> RETI RETI <INTCSI Service Program> EI IE0 ➀ INT0 <Main program> ➁ EI ➃ EI IECSI ➀ Although INT0 is set in the interrupt disabled st...
Page 152 - CHAPTER 7. STANDBY FUNCTION; STOP mode; HALT mode
141 CHAPTER 7. STANDBY FUNCTION CHAPTER 7. STANDBY FUNCTION The µ PD75402A has a standby function which can reduce the system power consumption. The standby function has the following two modes: • STOP mode • HALT mode (1) STOP mode In this mode, the main system clock oscillator is stopped and the w...
Page 153 - Operation state; and HALT instruction set bits 3 and 2 of the PCC respectively.)
142 CHAPTER 7. STANDBY FUNCTION 7.1 STANDBY MODE SETTING AND OPERATION STATES Table 7-1 Standby Mode Operation States STOP Mode HALT Mode Setting instruction HALT instruction CPU clock Φ only stopped oscillator (oscillation continues) Operation(IRQBT set at basic time interval) Operation possible Ou...
Page 154 - instruction execution begins.
143 CHAPTER 7. STANDBY FUNCTION 7.2 STANDBY MODE RESET The STOP mode is reset only by RESET input. The HALT mode is reset by standby release signal by setting of an interrupt request flag enabled by the interrupt enable flag and by RESET input. The standby mode reset operation is shown in Fig. 7-1. ...
Page 155 - HALT mode reset by interrupt generation
144 CHAPTER 7. STANDBY FUNCTION Fig. 7-1 Standby Mode Reset Operation (a) STOP mode reset by RESET input (b) HALT mode reset by RESET input HALTInstruction RESETInput OperatingMode Clock Oscillation HALT Mode Operating Mode STOPInstruction RESETInput OperatingMode Clock Oscillation STOP Mode Oscilla...
Page 156 - The interrupt request flag is held.; STANDBY MODE APPLICATION; When using the standby mode, proceed as follows:
145 CHAPTER 7. STANDBY FUNCTION 7.3 OPERATION AFTER STANDBY MODE RESET (1) When the standby mode was reset by RESET input, normal reset operation is executed. (STOP and HALT modes) (2) When the standby mode was reset by interrupt request generation, whether or not a vector interrupt is executed when...
Page 157 - CHAPTER 8. RESET FUNCTION
146 CHAPTER 8. RESET FUNCTION CHAPTER 8. RESET FUNCTION When low level is input to the RESET pin, system reset is applied and the hardware enters the state shown in Table 8-1. When the RESET input goes from low level to high level, the reset state is released. Then, the contents of the lower-order t...
Page 159 - CHAPTER 9. INSTRUCTION SET; ARCHITECTURE AND MEMORY MAP”.
148 CHAPTER 9. INSTRUCTION SET CHAPTER 9. INSTRUCTION SET The 75X series instruction set is an improved and expanded version of old µ PD7500 series instruction set. It is a revolutionary new instruction set which retains succession from the µ PD7500 series. The µ PD75402A instruction set is a 75X in...
Page 163 - FF0H to FFFH; MB is the accessible memory bank.; Description of machine cycle field; The value of S changes as follows:; Data memory
152 CHAPTER 9. INSTRUCTION SET (3) Description of addressing area field symbols * 1 MB = 0 * 2 MB = 0 (00H to 3FH) MB = 15 (80H to FFH) * 3 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH * 4 addr = 000H to 77FH * 5 addr = (Current PC) – 15 to (Current PC) – 1, (Current PC) + 16 to (Current PC) + 2 * 6 c...
Page 164 - Move instructions
153 CHAPTER 9. INSTRUCTION SET A, #n 4 1 1 A ← n 4 Stack A XA, #n 8 2 2 XA ← n 8 Stack A HL, #n 8 2 2 HL ← n 8 Stack B A, @HL 1 1 A ← (HL) *1 MOV @HL, A 1 1 (HL) ← A *1 A, mem 2 2 A ← (mem) *2 XA, mem 2 2 XA ← (mem) *2 mem, A 2 2 (mem) ← A *2 mem, XA 2 2 (mem) ← XA *2 A, @HL 1 1 A ↔ (HL) *1 A, mem 2...
Page 165 - Branch
154 CHAPTER 9. INSTRUCTION SET mem. bit 2 2 (mem. bit) ← 1 *2 f mem. bit 2 2 (f mem.bit) ← 1 *3 mem. bit 2 2 (mem. bit) ← 0 *2 f mem. bit 2 2 (f mem. bit) ← 0 *3 mem. bit 2 2 + S Skip if (mem. bit) = 1 *2 (mem. bit) = 1 f mem. bit 2 2 + S Skip if (f mem. bit) = 1 *3 (f mem. bit) = 1 mem. bit 2 2 + S...
Page 167 - Dn : Immediate data for mem; Bit manipulation addressing operation code; Bn : Immediate data for bit address (0 to 3) described at bit
156 CHAPTER 9. INSTRUCTION SET R 1 R 0 reg 0 0 A 0 1 X 1 0 L 1 1 H 9.3 OPERATION CODE OF EACH INSTRUCTION (1) Description of operation code symbols P 1 reg-pair 0 XA 1 HL N 2 N 1 N 0 IE ××× 0 0 0 IEBT 1 0 1 IECSI 1 1 0 IE0 1 1 1 IE2 In : Immediate data for n4, n8 Dn : Immediate data for mem Bn : Imm...
Page 168 - Arithmetic and
157 CHAPTER 9. INSTRUCTION SET Operation Code B 1 B 2 XCH MOV Note 1. Instruction Group 2. Accumulator operation instructions 3. Increment/decrement instructions 4. Compare instruction 0 1 1 1 I 3 I 2 I 1 I 0 1 0 0 0 1 0 P 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0...
Page 169 - Memory bit manipulation instructions
158 CHAPTER 9. INSTRUCTION SET mem. bit f mem. bit mem. bit f mem. bit mem. bit f mem. bit mem. bit f mem. bit SKTCLR f mem. bit AND 1 CY, f mem. bit OR 1 CY, f mem. bit XOR 1 CY, f mem. bit BRCB ! caddr CALLF ! faddr RET RETS RETI PUSH rp POP rp IE ××× IE ××× IN A, PORTn OUT PORTn, A HALT STOP NOP ...
Page 173 - Program Memory; For instance, when there is a MOVT XA, @PCXA instruction at position
162 CHAPTER 9. INSTRUCTION SET 9.4.2 Table Reference Instructions MOVT XA, @PCXA Function: XA ← ROM (PC 10 to PC 8 + XA) Moves the high-order three bits (PC 10 to PC 8 ) of the program counter (PC) and the low-order four bits of the table data in the program memory addressed by the contents of regis...
Page 174 - to I
163 CHAPTER 9. INSTRUCTION SET 9.4.3 Arithmetic and Logic Instructions ADDS A, #n4 Function: A ← A + n4; Skip if carry; n4 = I 3 to I 0 : 0 to FH Binary adds 4-bit immediate data n4 to the contents of the A register and skips the next instruction if a carry is generated. The carry flag is not affect...
Page 175 - the result into the A register.
164 CHAPTER 9. INSTRUCTION SET OR A, @HL Function: A ← A ∨ (HL) ORs the contents of the A register and the data memory contents addressed by register pair HL and sets the result into the A register. XOR A, @HL Function: A ← A ∨ (HL) Exclusive-ORs the contents of the A register and the data memory co...
Page 176 - RORC A; An to A; NOT A
165 CHAPTER 9. INSTRUCTION SET 9.4.4 Accumulator Operation Instructions RORC A Function: CY ← A 0 An to A 1 ← An , A 3 ← CY (n = 1 to 3) Rotates the contents of the A register (4-bit accumulator), including the carry flag, to the right one bit at a time. 0 0 1 0 1 1 0 0 1 0 CY 3 2 1 0 A RORC A Befor...
Page 177 - INCS reg; of incrementing, skips the next instruction.; INCS mem; to D; DECS reg; of decrementing, skips the next instruction.
166 CHAPTER 9. INSTRUCTION SET 9.4.5 Increment/Decrement Instructions INCS reg Function: reg ← reg + 1; Skip if reg = 0 Increments the contents of register reg (X, A, H, L). When the contents of register reg become 0 as the result of incrementing, skips the next instruction. INCS mem Functions: (mem...
Page 179 - SET1 CY; Clears the carry flag.; SKT CY; When the carry flag is 1, skips the next instruction.; NOT1 CY
168 CHAPTER 9. INSTRUCTION SET 9.4.7 Carry Flag Operation Instructions SET1 CY Function: CY ← 1 Sets the carry flag. CLR1 CY Function: CY ← 0 Clears the carry flag. SKT CY Function: Skip if CY = 1 When the carry flag is 1, skips the next instruction. NOT1 CY Function: CY ← CY Inverts the carry flag....
Page 182 - BR addr
171 CHAPTER 9. INSTRUCTION SET 9.4.9 Branch Instructions BR addr Function: PC 10 to PC 0 ← addr; addr = 000H to 77FH Branches to the address addressed by 11-bit immediate data addr. This instruction is an assembler pseudo instruction. During assembly, the assembler automatically replaces this instru...
Page 183 - RET
172 CHAPTER 9. INSTRUCTION SET 9.4.10 Subroutine Stack Control Instructions CALLF !faddr Function: (SP-1) ← PC 7 to PC 4 , (SP-2) ← PC 3 to PC 0 , (SP-3) ← 0, 0, 0, 0 (SP-4) ← 0, PC 10 to PC 8 , SP ← SP-4, PC ← A 10 to A 0 faddr = A 10 to A 0 : 000H to 77FH Saves the contents of the program counter ...
Page 184 - PUSH rp; rp; POP rp
173 CHAPTER 9. INSTRUCTION SET PUSH rp Function: (SP-1) ← rp H , (SP-2) ← rp L , SP ← SP-2 Saves the contents of register pair rp (XA, HL) to the data memory (stack) addressed by the stack pointer (SP), then decrements the SP. The high-order side (rp H : X, H) of the register pair is saved to the st...
Page 185 - EI; determined by each interrupt enable flag.; EI IEXXX; DI; to N
174 CHAPTER 9. INSTRUCTION SET 9.4.11 Interrupt Control Instructions EI Function: IME ← 1 Sets the interrupt master enable flag (1), and enables interrupts. Whether or not interrupts are accepted is determined by each interrupt enable flag. EI IEXXX Function: IE ××× ← 1; ××× = N 2 to N 0 Sets the in...
Page 187 - STOP; NOP
176 CHAPTER 9. INSTRUCTION SET 9.4.13 CPU Control Instructions HALT Function: PCC. 2 ← 1 Sets the HALT mode (This instruction sets bit 2 of the processor clock control register.). Note The instruction following the HALT instruction is made an NOP instruction. STOP Function: PCC. 3 ← 1 Sets the STOP ...
Page 188 - following instructions not available with the
177 APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY Since EVAKIT-75X (75X series common evaluation board) supports the 75X series functions, it can execute the following instructions not available with the µ PD75402A. Since th...
Page 189 - APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY
178 APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY Mnemonic Operands DECS mem @HL SKE A, reg XA, rp’ XA, @HL @HL, #n4 A, mem SET1, CLR1, pmem. @L SKF, SKT,SKTCLR @H + mem. bit AND1, OR1 CY, pmem. @L CY, @H + mem. bit CY,/fmem. bit CY,/pmem. @L CY,/@H + mem. bit XOR1 CY, pmem. @L CY, @H...
Page 190 - Language Processor; PROM Writing Tools; Hardware; and operating systems quoted above.
179 APPENDIX B. DEVELOPMENT TOOLS APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the µ PD75402A: Language Processor Host Machine Ordering Code (Product Name) Supply Medium OS PC DOS TM (Ver. 3.1) ~ PC-9800 series MS-DOS TM 3.5-inch 2HD µ S5A1...
Page 191 - APPENDIX B. DEVELOPMENT TOOLS; Debugging Tools; Their respective system configurations are as follows.; Maintenance product
180 APPENDIX B. DEVELOPMENT TOOLS Debugging Tools The following in-circuit emulators (IE-75000-R and IE-75001-R) are available as the µ PD75402A program debugging tools. Their respective system configurations are as follows. IE-75000-R*1 The IE-75000-R is an in-circuit emulator for hardware/software...
Page 192 - Development Tool Configuration; PROM Programmer
181 APPENDIX B. DEVELOPMENT TOOLS Development Tool Configuration * 1. The IE-75001-R does not incorporate the IE-75000-R-EM (Sold separately) 2. EV-9200G-44 Host MachinePC-9800 SeriesIBM PC/AT(SymbolicDebuggingCapability) Centronics I/F IEControlProgram PG-1500Controller RS-232-C RelocatableAssemble...
NEC nec
Manual
NEC LCD172VXM
Manual
NEC PSIII
Manual
NEC XV17+
Manual
NEC LCD1860NX
Manual
NEC PA322UHD
Manual
NEC Versa M540
Manual
NEC LCD224WMX
Manual
NEC SP4620
Manual
NEC 0612-20
Manual
NEC PX-50XM5A
Manual
NEC 46 V462
Manual
NEC MT1055
Manual
NEC NP-V311X
Manual
NEC LT240K, LT260K
Manual
NEC DTR-IR-2
Manual
NEC j
Manual
NEC PD78052(A)
Manual
NEC 0724-20
Manual