Intel IXP12xx - Manuals - manualsarea.com

Page 3 - OVERVIEW; For use with the IXP1240/1250 with hardware CRC capability; external; MEASUREMENT ENVIRONMENT; Alternate DRAM Timing

Version 1.0, 4/10/02 Page 3 of 17 IXP12xx ATM OC12/Ethernet IP Router Example Design Performance and Headroom Analysis OVERVIEW This documents details the performance and headroom analysis done on the IXP12xx ATM OC12 / Ethernet IP Router Example Design. It covers the general performance aspects of ...

Page 4 - KEY WORKLOADS & APPROACHES TO TESTING THE EXAMPLE DESIGN; Protocol Performance of IP over ATM vs. Ethernet; Figure 1 – Protocol Processing

Version 1.0, 4/10/02 Page 4 of 17 KEY WORKLOADS & APPROACHES TO TESTING THE EXAMPLE DESIGN Protocol Performance of IP over ATM vs. Ethernet Figure 1 details the protocol processing required to carry an IP packet over ATM and Ethernet. . Figure 1 – Protocol Processing Figures 2 and 3 show that as...

Page 5 - Figure 2 – Frame and PDU Length versus IP Packet Length; Figure 3 – Expected Ethernet Transmit Bandwidth

Version 1.0, 4/10/02 Page 5 of 17 The result is that ATM is significantly more efficient that Ethernet in terms of Mbps for carrying very small PDUs. Every Mbps of single-cell-PDUs on the ATM link requires (84/55) Mbps on the matching Ethernet link(s). 0 16 32 48 64 80 96 112 128 144 160 176 0 20 40...

Page 6 - Multiple Cells/PDU Workload; CYCLE AND INSTRUCTION BUDGETS; Cycle Budgets to support Line Rates

Version 1.0, 4/10/02 Page 6 of 17 As shown graphically in Figure 3, 622Mbps of single-cell-PDU input requires 622*(84/55) = 949 Mbps of Ethernet output. This example design supplies 800Mbps of Ethernet bandwidth (IXP1240 configurations), so under a single cell/PDU workload the design can be expected...

Page 7 - Virtual Circuits; interleaved; next pipeline stage falls behind.

Version 1.0, 4/10/02 Page 7 of 17 bytes/minimum frame}. 84 bytes/frame * 8 bits/byte / 100Mb/sec = 6.72 usec/frame. 232MHz * 6.72 usec/frame = 1559 cycles/frame These cycle budgets specify how frequently a cell or frame goes over the wire. If multiple threads handle multiple frames on the same wire,...

Page 8 - SIMULATION MEASUREMENT PROCEDURE AND RESULTS; Simulated 29-byte packet performance

Version 1.0, 4/10/02 Page 8 of 17 One issue with running simulations unbounded to wire-rate is that it can hide errors because there is no concept of device overflows or underflows. Further the design can become un-balanced, say for example if an efficient receiver races ahead of the rest of the des...

Page 9 - Simulated 40-byte and 1500-byte packet performance; HARDWARE MEASUREMENT PROCEDURE AND RESULTS; Hardware Measurement Results

Version 1.0, 4/10/02 Page 9 of 17 Both the OC-12 and 4xOC-3 configurations experience an ATM overflow after 1M cycles. This indicates that under this system workload, the receiver is not keeping up with the wire, but has dropped a cell in the first 6,000 cells. Simulated 40-byte and 1500-byte packet...

Page 10 - Hardware 29-byte packet performance; Figure 5 – Single-cell/PDU Performance using 133MHZ DRAM

Version 1.0, 4/10/02 Page 10 of 17 the number of times the PHY was not fed a cell in time to keep the wire busy, and thus had to manufacture an idle cell. The number reported here is from the 2 nd counters query when 2 “_VolgaGetChanCounters” are issued on the same line at the VxWorks prompt (this i...

Page 11 - Figure 6 – Single-cell/PDU Performance using 143MHz DRAM; Hardware 40-byte packet performance; Figure 7 – Two-cell PDU Performance on 133MHZ DRAM

Version 1.0, 4/10/02 Page 11 of 17 degrade in these scenarios, and the design becomes subject to ATM overflows from running “_VolgaGetChanCounters”. Ethernet Input Ports ATM Transmit Rate [%] IXF6012 Transmit Idle ATM Receive Ports IXF6012 Overflows Ethernet Transmit KFrame/s Ethernet Transmit [MB/s...

Page 12 - Figure 8 – Two-cell/PDU Performance on 143MHZ DRAM; Hardware 1500-byte packet performance; Figure 9 – 32-cell/PDU Performance on 133MHz DRAM; StrongARM CORE PERFORMANCE

Version 1.0, 4/10/02 Page 12 of 17 Ethernet Input Ports ATM Transmit Rate [%] IXF6012 Transmit Idle ATM Receive Ports IXF6012 Overflows Ethernet Transmit KFrame/s Ethernet Transmit [MB/s] 8 100 0 1 0 88,300 5.6 Figure 8 – Two-cell/PDU Performance on 143MHZ DRAM Using 143 MHz DRAM, the 40-byte (2-cel...

Page 14 - RESOURCE UTILIZATION AND HEADROOM ANALYSIS; Microengine Register and Microstore Headroom; Figure 12 – Microengine register and microstore headroom

Version 1.0, 4/10/02 Page 14 of 17 RESOURCE UTILIZATION AND HEADROOM ANALYSIS This section details system resource utilization, including per-microengine resources such as registers and microstore instructions; as well as shared resources such as Scratchpad RAM, SRAM, and DRAM. The memory utilizatio...

Page 16 - Configuration; Figure 13 – SRAM and SDRAM bandwidth headroom

Version 1.0, 4/10/02 Page 16 of 17 SDRAM Capacity The IXM1240 Network Processor Base Card comes with 128MB of SDRAM. The project is configured to use less than 64MB: 32MB of Packet Data Buffers, 16MB for VxWorks, and the balance for IP Route Table Entries. This leaves over 50% available. The IP Rout...

Page 17 - APPENDIX; Buffer Allocation in DRAM; ordered

Version 1.0, 4/10/02 Page 17 of 17 APPENDIX Buffer Allocation in DRAM The microengines in this example design uses two DRAM command queues. The ordered queue is used by all sdram_crc[] commands to transfer packet data between DRAM and the receive and transmit FIFOs. The priority queue is used for al...