Page 2 - Application Note
Application Note Information in this document is provided in connection with Intel ® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Inte...
Page 3 - iii; Contents
Application Note iii IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Contents 1.0 Introduction ................................................................................................................................. 7 1.1 Purpose of ATM Example Design ...........
Page 4 - iv; IP Route Table Entry37
iv Application Note IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 3.7.2 CRC-32 Checker and Generator High Level Algorithm.......................... 29 3.7.3 CRC-32 Computation ............................................................................. 29 4.0 Softwa...
Page 6 - Figures
vi Application Note IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Figures 1 IP over ATM Encapsulation Format ...................................................................... 9 2 Frame and PDU Length vs. IP Packet Length ............................................
Page 7 - Introduction; Core and microengine; Purpose of ATM Example Design
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 7 Modified on: 3/20/02, 1.0 Introduction Intel develops example software to demonstrate the capabilities of the IXP1200 Network Processor Family. This document describes the implementation of example soft...
Page 8 - Supported / Not Implemented Functions; Background; Ethernet, IP and AAL5 Protocol Processing; Figure 1
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 8 Application Note Modified on: 3/20/02, 1.2.1 Supported / Not Implemented Functions The following identifies the ATM, Ethernet, and StrongARM supported functions, as well as those functions that are not supported. The ma...
Page 9 - Frame and PDU Length vs. IP Packet Length; Figure 2; Figure 1. IP over ATM Encapsulation Format
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 9 Modified on: 3/20/02, 1.3.2 Frame and PDU Length vs. IP Packet Length Figure 2 shows the relationship between IP Packet Length (X axis), Ethernet Frame Length, and AAL5 PDU length (Y axis). Packet lengt...
Page 10 - Expected Ethernet Transmit Bandwidth; Figure 3; Figure 2. Frame and PDU Length vs. IP Packet Length
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 10 Application Note Modified on: 3/20/02, PDUs because 8-bytes of LLC/SNAP plus 8 bytes of AAL5 trailer push them over the 48 byte payload capacity of a single ATM cell. • Fully populated 64-byte minimum-sized Ethernet fr...
Page 11 - Execution Environment; Software; for; Figure 3. Expected Ethernet Transmit Bandwidth
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 11 Modified on: 3/20/02, A 33-byte IP packet overflows into 2 cells, requiring 53 more bytes on the input wire. This effectively slows down the input rate, and the theoretical best-case Ethernet Transmit ...
Page 12 - Figure 4. Developer’s Workbench - ATM Data Stream Dialog Box
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 12 Application Note Modified on: 3/20/02, Figure 4 shows how data stream PDUs can be created in the Workbench for ATM, Ethernet, IP, and other protocol data streams. These data streams can then be assigned to feed differe...
Page 13 - Hardware; . While the project runs in; System Overview; System Programming Model; Figure 6; Figure 5. Developer’s Workbench - IX Bus Device Status Window
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 13 Modified on: 3/20/02, . 1.4.2 Hardware The README.txt file contained in the vxworks subdirectory of the project source code describes how to build and run the project on hardware using VxWorks ® . Whil...
Page 14 - StrongARM Core Software; Figure 6. System Programming Model
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 14 Application Note Modified on: 3/20/02, The StrongARM core shares access to SRAM and DRAM with the microengines, and thus can manage the VC and IP tables. The StrongARM core runs a Developer’s Workbench debug library to...
Page 15 - Software Partitioning; Figure 9
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 15 Modified on: 3/20/02, 2.3 Software Partitioning The following figures show how the microcode functional blocks are partitioned on IXP12xx hardware for the three system configurations. All three figures...
Page 16 - Lookup Tables
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 16 Application Note Modified on: 3/20/02, In the OC-12 configuration, there are two message queues (MSGQs) in scratchpad RAM, one for PDUs from each Ethernet Receive microengine. The pool of threads in the ATM transmit mi...
Page 17 - Data Flow; ATM to Ethernet Data Flow; Partitioning
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 17 Modified on: 3/20/02, 2.4 Data Flow 2.4.1 ATM to Ethernet Data Flow Figure 10 outlines the processing to receive ATM cells and forward them to Ethernet ports. For a given VC, three different types of c...
Page 18 - IP Lookup Table; Figure 10. ATM to Ethernet Processing Steps
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 18 Application Note Modified on: 3/20/02, syndrome is updated appropriately. The VC Table Entry also contains an AAL type field. Currently, this example design supports only classical IP over ATM, where the AAL type can b...
Page 19 - Ethernet to ATM Data Flow; Figure 11. Ethernet to ATM Processing Steps; StrongARM Core Initialization; Control the baseboard 82559 PCI Ethernet NIC.
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 19 Modified on: 3/20/02, 2.4.2 Ethernet to ATM Data Flow Figure 11 outlines the sequence of events that takes place when processing incoming Ethernet packets. Incoming Ethernet packets can either fit with...
Page 20 - Microengine Initialization; Microengine Functional Blocks; ATM Receive Microengine; Structure
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 20 Application Note Modified on: 3/20/02, 3. Run the IXP1200 Developer’s Workbench debug library, and connects it to a remote system host via the PCI Ethernet NIC to download and debug IXP1240 microcode. Then, atm_init() ...
Page 21 - High Level Algorithm; Figure 12. ATM Receive High Level Algorithm
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 21 Modified on: 3/20/02, 3.1.2 High Level Algorithm In all configurations, each Receive thread gets its own RFIFO element, as assigned by port_rx_init(). "Fast-port" speculative receive requests. ...
Page 22 - ATM Transmit Microengine; Figure 13. ATM Transmit High Level Algorithm
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 22 Application Note Modified on: 3/20/02, 3.2 ATM Transmit Microengine The ATM Transmit microengine is an AAL5 Unspecified Bit Rate (UBR) Transmitter that uses a single microengine to move cells at wire-rate in either sin...
Page 23 - IP-Router Microengine; Ethernet Receive Microengine; For ATM destinations, append the AAL5 trailer.; Figure 14. IP Router High Level Algorithm
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 23 Modified on: 3/20/02, 3.3 IP-Router Microengine The IP Router microengine consumes packets from the ATM receive microengine via a message queue, and routes them to the appropriate Ethernet transmit pac...
Page 24 - Ethernet Receive Structure; Ethernet Transmit Microengine; Figure 15. Ethernet Receive High Level Algorithm
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 24 Application Note Modified on: 3/20/02, • For ATM destinations, enqueue to the ATM Transmit microengine, or for software CRC, to the appropriate AAL5 CRC-32 generation queues. The ETHERNET_LOOPBACK build option enables ...
Page 25 - Ethernet Transmit Structure; As mentioned in; CRC-32 Hardware Checking on Receive; , but not to the ATM header. The ATM header is not
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 25 Modified on: 3/20/02, 3.5.1 Ethernet Transmit Structure The Ethernet Transmit microengine contains three fill threads and one transmit scheduler thread. The Ethernet transmitter uses the eight even TIF...
Page 26 - Figure 16. First Cell of a PDU in RFIFO and in DRAM
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 26 Application Note Modified on: 3/20/02, Quadwords 1-5 are transferred by an sdram_crc[r_fifo_rd, 5] instruction. Quadword 6 contains "Data 11" -- the eleventh 32-bit longword of the cell. Data 11 is stored in th...
Page 27 - CRC-32 Hardware Generation on Transmit; and; Transmit Alignment; Figure 18. Transmit cell as seen in DRAM
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 27 Modified on: 3/20/02, • Upon reception of the first cell, data11 is saved in the VC cache/table entry. Upon reception of the 2nd cell, data11 is retrieved from the VC cache/table entry, combined with d...
Page 28 - Functional Differences between Checker and Generator; Queues to be consumed.
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 28 Application Note Modified on: 3/20/02, The hardware byte aligner operates on the data before the CRC computation hardware. This can be seen in the transfer to quadword 0 of the TFIFO element with sdram_crc[t_fifo_wr], ...
Page 29 - CRC-32 Checker and Generator High Level Algorithm; Software Subsystems & Data Structures; VC Table Function
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 29 Modified on: 3/20/02, 3.7.2 CRC-32 Checker and Generator High Level Algorithm The PDUs within each VC on each port are enqueued on the output in the same order that they were dequeued from the input. 3...
Page 31 - Figure 21. Hashed VC Table Structure
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 31 Modified on: 3/20/02, When atm_vc_table_entry_create() attempts to add an entry to the table and determines that the entry in the primary table is already occupied, it needs to come up with an availabl...
Page 32 - VC Table Entry; Figure 22. VC Table Index
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 32 Application Note Modified on: 3/20/02, The project defaults to support a 64K-entry VC table - independent of the number of ports. It does this with eight significant VCI bits, and eight more bits split between VPI and ...
Page 34 - Virtual Circuit Lookup Table Cache; VC Cache Function
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 34 Application Note Modified on: 3/20/02, 4.2 Virtual Circuit Lookup Table Cache 4.2.1 VC Cache Function 4.2.1.1 OC-12 Configuration The intent of the VC cache is not to reduce average latency but to account for back to b...
Page 35 - VC Cache API; IP Table Function
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 35 Modified on: 3/20/02, 4.2.3 VC Cache API There is no interaction between the StrongARM core and the VC Cache. In particular, there is no method for the StrongARM core to force the ATM Receive microengi...
Page 36 - IP Table Management API; Initializes route table memory and data structures.
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 36 Application Note Modified on: 3/20/02, 4.3.3 IP Table Management API The route table is managed by the Route Table Manager (RTM), which may be used from both Transactor Scripts and VxWorks. It may be compiled and loade...
Page 37 - IP Route Table Entry
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 37 Modified on: 3/20/02, 4.3.3.4 enet_route_add() Adds a route with Ethernet destination to the route table. enet_route_add( char *dest, char *netmask, char *gateway, int itf, int gateway_da_hi32, int gat...
Page 38 - SRAM Buffer Descriptors and DRAM Data Buffers; Figure 25. IP Route Table Entry - ATM Destination; Figure 26. IP Route Table Entry - Ethernet Destination
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 38 Application Note Modified on: 3/20/02, 4.4 SRAM Buffer Descriptors and DRAM Data Buffers SRAM Buffer Descriptors and DRAM Data Buffers are a fundamental component of this design. Each descriptor occupies 16 bytes of SR...
Page 39 - SRAM Buffer Descriptor Format; Figure 27. SRAM Descriptor to DRAM Buffer Mapping; SRAM
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 39 Modified on: 3/20/02, Both descriptors and buffers are stored in arrays. The array index is used to associate a unique DRAM Data Buffer with each SRAM Descriptor: 4.4.1 SRAM Buffer Descriptor Format Th...
Page 40 - DRAM Data Buffer Format; Figure 33. DRAM Data Buffer Received by Ethernet
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 40 Application Note Modified on: 3/20/02, 4.4.2 DRAM Data Buffer Format Packet payloads are stored in DRAM data buffers. Depending on if the data was received on an ATM or Ethernet port, the payload will land in a differe...
Page 41 - System Limit on Packet Buffers; sequence.uc contains the following API calls:; SEQUENCE_HANDLE Usage
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 41 Modified on: 3/20/02, 4.4.3 System Limit on Packet Buffers Several factors are involved in the number of packet buffers the system can support: • The Ethernet transmitter uses packetqs (packetq.uc), an...
Page 42 - Usage Model
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 42 Application Note Modified on: 3/20/02, 4.5.2 Usage Model The following model is described by an analogy to waiting in line at a bakery:. 4.5.2.1 Example #define MY_SEQUENCE_HANDLE my_seq_number, @enter, @one, @exit, @o...
Page 43 - MSGQ_HANDLE Parameters; Sends a message to the queue.
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 43 Modified on: 3/20/02, 4.6.1 MSGQ_HANDLE Parameters The following parameters make up MSGQ_HANDLE and are common to all macros in msgq.uc: 4.6.2 msgq_init_queue() Initializes the global queue in RAM_TYPE...
Page 44 - Example
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 44 Application Note Modified on: 3/20/02, msgq_send(io_message, MSGQ_HANDLE , RAM_OPTION ) 4.6.5 msgq_receive() Receives a message from the queue. msgq_receive(i o_xfer, MSGQ_HANDLE ) 4.6.6 Example In the following exampl...
Page 45 - BDQ Management Macros
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 45 Modified on: 3/20/02, 4.7 Buffer Descriptor Queues - bdq.uc This design uses a generic buffer descriptor queuing subsystem to pass data between microengines. This section describes the facility so that...
Page 46 - Counters; counters.uc provides the following microcode API:; Figure 34. Buffer Descriptor Queue API
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 46 Application Note Modified on: 3/20/02, For the synchronous empty->non-empty queue notification feature to be used, only one microengine can be assigned to dequeue from each queue. Further, it is optimal when threads...
Page 47 - Global Parameters; The counter handle has three members:; Counter Base Address
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 47 Modified on: 3/20/02, • On hardware, counters.c is compiled into the atm_utils.o VxWorks-loadable module to provide counters at the VxWorks console. 4.8.1 Global Parameters 4.8.2 Use of the Counter Sub...
Page 48 - Global Counter Enable and Flags; To enable a counter for a command:; Counter Flags
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 48 Application Note Modified on: 3/20/02, 4.8.2.3 Global Counter Enable and Flags Global Counter Enable and Flags COUNTERS_ENABLE_MASK is the global counter enable and is set via a #define statement in system_config.h: To...
Page 53 - Mutex Vectors; Enters the specified microengine critical section.
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 53 Modified on: 3/20/02, // sram[read, $foo], ordered, ctx_swap 4.10 Mutex Vectors Mutex vectors are an extension to critical sections that allows multiple critical sections to be contained within a singl...
Page 54 - Inter-Thread Signalling; Inter-thread signals are used in four ways:
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 54 Application Note Modified on: 3/20/02, 4.11 Inter-Thread Signalling Inter-thread signals are used in four ways: • Initialization, as detailed in the “Microengine Initialization” section. • Notification to a BDQ (Buffer...
Page 55 - Switching Between Hardware Configurations; Testing Environments
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 55 Modified on: 3/20/02, // Define DEBUG to enable all the counters and run-time checking.// Disable for maximum performance.// #define DEBUG // Define COUNTERS_ENABLE_MASK to all 1’s to enable every syst...
Page 56 - Limitations
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 56 Application Note Modified on: 3/20/02, 7.0 Simulation Support (Scripts, etc.) Simulation support for this example design is provided by using a combination of the Foreign Model DLLs (libraries linked to the Transactor ...
Page 57 - Document Conventions; Bytes are numbered from left to right as shown in the array in; Acronyms & Definitions; Figure 37. Illustration of Array of 32-bit Words; Figure 38. Illustration of Byte Sequence; Figure 39. Definitions
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note 57 Modified on: 3/20/02, 10.0 Document Conventions In illustrations of 32-bit registers, or data structures in memory; smaller addresses appear toward the top of the figure, - as they would appear in a me...
Page 58 - Related Documents
IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 58 Application Note Modified on: 3/20/02, 12.0 Related Documents PDU Protocol Data Unit Rosetta Intel IXB8055 IX Bus to Utopia Bridge RTM Route Table Manager Slow Port A port that does not have dedicated status lines, and...
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