Intel IXP1200 - Manual

Intel IXP1200

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Table of Contents:

  • Page 2 – Application Note
  • Page 3 – iii; Contents
  • Page 4 – iv; IP Route Table Entry37
  • Page 6 – Figures
  • Page 7 – Introduction; Core and microengine; Purpose of ATM Example Design
  • Page 8 – Supported / Not Implemented Functions; Background; Ethernet, IP and AAL5 Protocol Processing; Figure 1
  • Page 9 – Frame and PDU Length vs. IP Packet Length; Figure 2; Figure 1. IP over ATM Encapsulation Format
  • Page 10 – Expected Ethernet Transmit Bandwidth; Figure 3; Figure 2. Frame and PDU Length vs. IP Packet Length
  • Page 11 – Execution Environment; Software; for; Figure 3. Expected Ethernet Transmit Bandwidth
  • Page 12 – Figure 4. Developer’s Workbench - ATM Data Stream Dialog Box
  • Page 13 – Hardware; . While the project runs in; System Overview; System Programming Model; Figure 6; Figure 5. Developer’s Workbench - IX Bus Device Status Window
  • Page 14 – StrongARM Core Software; Figure 6. System Programming Model
  • Page 15 – Software Partitioning; Figure 9
  • Page 16 – Lookup Tables
  • Page 17 – Data Flow; ATM to Ethernet Data Flow; Partitioning
  • Page 18 – IP Lookup Table; Figure 10. ATM to Ethernet Processing Steps
  • Page 19 – Ethernet to ATM Data Flow; Figure 11. Ethernet to ATM Processing Steps; StrongARM Core Initialization; Control the baseboard 82559 PCI Ethernet NIC.
  • Page 20 – Microengine Initialization; Microengine Functional Blocks; ATM Receive Microengine; Structure
  • Page 21 – High Level Algorithm; Figure 12. ATM Receive High Level Algorithm
  • Page 22 – ATM Transmit Microengine; Figure 13. ATM Transmit High Level Algorithm
  • Page 23 – IP-Router Microengine; Ethernet Receive Microengine; For ATM destinations, append the AAL5 trailer.; Figure 14. IP Router High Level Algorithm
  • Page 24 – Ethernet Receive Structure; Ethernet Transmit Microengine; Figure 15. Ethernet Receive High Level Algorithm
  • Page 25 – Ethernet Transmit Structure; As mentioned in; CRC-32 Hardware Checking on Receive; , but not to the ATM header. The ATM header is not
  • Page 26 – Figure 16. First Cell of a PDU in RFIFO and in DRAM
  • Page 27 – CRC-32 Hardware Generation on Transmit; and; Transmit Alignment; Figure 18. Transmit cell as seen in DRAM
  • Page 28 – Functional Differences between Checker and Generator; Queues to be consumed.
  • Page 29 – CRC-32 Checker and Generator High Level Algorithm; Software Subsystems & Data Structures; VC Table Function
  • Page 31 – Figure 21. Hashed VC Table Structure
  • Page 32 – VC Table Entry; Figure 22. VC Table Index
  • Page 34 – Virtual Circuit Lookup Table Cache; VC Cache Function
  • Page 35 – VC Cache API; IP Table Function
  • Page 36 – IP Table Management API; Initializes route table memory and data structures.
  • Page 37 – IP Route Table Entry
  • Page 38 – SRAM Buffer Descriptors and DRAM Data Buffers; Figure 25. IP Route Table Entry - ATM Destination; Figure 26. IP Route Table Entry - Ethernet Destination
  • Page 39 – SRAM Buffer Descriptor Format; Figure 27. SRAM Descriptor to DRAM Buffer Mapping; SRAM
  • Page 40 – DRAM Data Buffer Format; Figure 33. DRAM Data Buffer Received by Ethernet
  • Page 41 – System Limit on Packet Buffers; sequence.uc contains the following API calls:; SEQUENCE_HANDLE Usage
  • Page 42 – Usage Model
  • Page 43 – MSGQ_HANDLE Parameters; Sends a message to the queue.
  • Page 44 – Example
  • Page 45 – BDQ Management Macros
  • Page 46 – Counters; counters.uc provides the following microcode API:; Figure 34. Buffer Descriptor Queue API
  • Page 47 – Global Parameters; The counter handle has three members:; Counter Base Address
  • Page 48 – Global Counter Enable and Flags; To enable a counter for a command:; Counter Flags
  • Page 53 – Mutex Vectors; Enters the specified microengine critical section.
  • Page 54 – Inter-Thread Signalling; Inter-thread signals are used in four ways:
  • Page 55 – Switching Between Hardware Configurations; Testing Environments
  • Page 56 – Limitations
  • Page 57 – Document Conventions; Bytes are numbered from left to right as shown in the array in; Acronyms & Definitions; Figure 37. Illustration of Array of 32-bit Words; Figure 38. Illustration of Byte Sequence; Figure 39. Definitions
  • Page 58 – Related Documents
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IXP1200 Network Processor
Family

ATM OC-3/12/Ethernet IP Router Example Design

Application Note - Rev 1.0, 3/20/2002

Order Number:

278393-001

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Summary

Page 2 - Application Note

Application Note Information in this document is provided in connection with Intel ® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Inte...

Page 3 - iii; Contents

Application Note iii IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Contents 1.0 Introduction ................................................................................................................................. 7 1.1 Purpose of ATM Example Design ...........

Page 4 - iv; IP Route Table Entry37

iv Application Note IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design 3.7.2 CRC-32 Checker and Generator High Level Algorithm.......................... 29 3.7.3 CRC-32 Computation ............................................................................. 29 4.0 Softwa...

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