Intel GD82559ER - Manuals

Datasheet 1 Networking Silicon — GD82559ER 1. Introduction 1.1 GD82559ER Overview The 82559ER is part of Intel's second generation family of fully integrated 10BASE-T/100BASE-TX LAN solutions. The 82559ER consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a...

Datasheet 3 Networking Silicon — GD82559ER 2. GD82559ER Architectural Overview Figure 1 is a high level block diagram of the 82559ER. It is divided into four main subsystems: a parallel subsystem, a FIFO subsystem, the 10/100 Mbps Carrier-Sense Multiple Access with Collision Detect (CSMA/CD) unit, a...

GD82559ER — Networking Silicon 4 Datasheet operate independently. Control is switched between the two units according to the microcode instruction flow. The independence of the Receive and Command units in the micromachine allows the 82559ER to interleave commands and receive incoming frames, with n...

Datasheet 7 Networking Silicon —GD82559ER 3. Signal Descriptions 3.1 Signal Type Definitions 3.2 PCI Bus Interface Signals 3.2.1 Address and Data Signals Type Name Description IN Input The input pin is a standard input only signal. OUT Output The output pin is a Totem Pole Output pin and is a standa...

GD82559ER — Networking Silicon 8 Datasheet 3.2.2 Interface Control Signals Symbol Type Name and Function FRAME# S/T/S Cycle Frame. The cycle frame signal is driven by the current master to indicate the beginning and duration of a transaction. FRAME# is asserted to indicate the start of a transaction...

Datasheet 9 Networking Silicon —GD82559ER 3.2.3 System and Power Management Signals 3.3 Local Memory Interface Signals Symbol Type Name and Function CLK IN Clock. The Clock signal provides the timing for all PCI transactions and is an input signal to every PCI device. The 82559ER requires a PCI Cloc...

GD82559ER — Networking Silicon 10 Datasheet 3.4 Testability Port Signals FLA[13]/EEDI OUT Flash Address[13]/EEPROM Data Input. During Flash accesses, this multiplexed pin acts as the Flash Address [13] output signal. During EEPROM accesses, it acts as serial output data to the EEPROM Data Input sign...

Datasheet 11 Networking Silicon —GD82559ER 3.5 PHY Signals NOTE: 619 Ω and 549 Ω for the RBIAS100 and RBIAS10, respectively, are only a recommended values and should be fine tuned for various designs. Symbol Type Name and Function X1 A/I Crystal Input One. X1 and X2 can be driven by an external 3.3 ...

Datasheet 13 Networking Silicon — GD82559ER 4. GD82559ER Media Access Control Functional Description 4.1 82559ER Initialization The 82559ER has four sources for initialization. They are listed according to their precedence: 1. ALTRST# Signal 2. PCI RST# Signal 3. Software Reset (Software Command) 4....

GD82559ER — Networking Silicon 14 Datasheet 4.2 PCI Interface 4.2.1 82559ER Bus Operations After configuration, the 82559ER is ready for normal operation. As a Fast Ethernet controller, the role of the 82559ER is to access transmitted data or deposit received data. In both cases the 82559ER, as a bu...

Datasheet 15 Networking Silicon — GD82559ER The figures below show CSR zero wait-state I/O read and write cycles. In the case of accessing the Control/Status Registers, the CPU is the initiator and the 82559ER is the target of the transaction. Read Accesses: The CPU, as the initiator, drives address...

GD82559ER — Networking Silicon 16 Datasheet controls the TRDY# signal and asserts it from the data access. The 82559ER allows the CPU to issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP# signal. This is true for both memory mapped and I/O ...

Datasheet 17 Networking Silicon — GD82559ER Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME# . It also provides the 82559ER with valid data immediately after asserting IRDY# . The 82559ER...

GD82559ER — Networking Silicon 18 Datasheet Note: The 82559ER is considered the target in the above diagram; thus, TRDY# is not asserted. 4.2.1.1.4 Error Handling Data Parity Errors: The 82559ER checks for data parity errors while it is the target of the transaction. If an error was detected, the 82...

GD82559ER — Networking Silicon 20 Datasheet Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be completed after an 82559ER internal arbitration. (Details on the Configure command are described in the Software Developer ’s Manual.) The 82559ER, as the initiator, driv...

Datasheet 21 Networking Silicon — GD82559ER 1. Minimum transfer of one cache line 2. Active byte enable bits (or BE#[3:0] are all low) during MWI access 3. The 82559ER may cross the cache line boundary only if it intends to transfer the next cache line too. To ensure the above conditions, the 82559E...

GD82559ER — Networking Silicon 22 Datasheet • This feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. • This feature should be used only when the CLS register in PCI Configuration space is set to 8 or 16 Dwords. • The 82559E...

Datasheet 23 Networking Silicon — GD82559ER 4.2.4 Power States The 82559ER’s power management register implements all four power states as defined in the Power Management Network Device Class Reference Specification, Revision 1.0. The four states, D0 through D3, vary from maximum power consumption a...

GD82559ER — Networking Silicon 24 Datasheet 4.2.4.4 D3 Power State In the D3 power state, the 82559ER has the same capabilities and consumes the same amount of power as it does in the D2 state. However, it enables the PCI system to be in the B3 state. If the PCI system is in the B3 state (in other w...

Datasheet 25 Networking Silicon — GD82559ER . 4.2.4.6 Auxiliary Power Signal The 82559ER senses whether it is connected to the PCI power supply or to an auxiliary power supply (V AUX ) via the FLA1/AUXPWR pin. The auxiliary power detection pin (multiplexed with FLA1) is sampled when the PCI RST# or ...

GD82559ER — Networking Silicon 26 Datasheet In a LAN on Motherboard solution, the PCI power good signal is supplied by the system. In network adapter implementations, the PCI power good signal can be either generated locally using an external analog device, or connected directly to the PCI reset sig...

Datasheet 27 Networking Silicon — GD82559ER • ISOLATE# trailing edge The internal initialization signal resets the PCI Configuration Space, MAC configuration, and memory structure. The behavior of the PCI RST# signal and the internal 82559ER initialization signal are shown in the figure below. 4.2.5...

GD82559ER — Networking Silicon 28 Datasheet 4.2.5.2 Link Status Change Event The 82559ER link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82559ER reports a PME link status event in all power states. T...

Datasheet 29 Networking Silicon — GD82559ER All accesses, either read or write, are preceded by a command instruction to the device. The address field is six bits for a 64 register EEPROM or eight bits for a 256 register EEPROM. The end of the address field is indicated by a dummy zero bit from the ...

GD82559ER — Networking Silicon 30 Datasheet Note that word 0Ah contains several configuration bits. Bits from word 0Ah, FBh through FEh, and certain bits from word 0Dh are described as follows: Note: The IA read from the EEPROM is used by the 82559ER until an IA Setup command is issued by software. ...

Datasheet 31 Networking Silicon — GD82559ER 4.5.1 Full Duplex When operating in full duplex mode the 82559ER can transmit and receive frames simultaneously. Transmission starts regardless of the state of the internal receive path. Reception starts when the internal PHY detects a valid frame on the r...

GD82559ER — Networking Silicon 32 Datasheet 4.6 Media Independent Interface (MII) Management Interface The MII management interface allows the CPU to control the PHY unit via a control register in the 82559ER. This allows the software driver to place the PHY in specific modes such as full duplex, lo...

Datasheet 33 Networking Silicon — GD82559ER 5. GD82559ER Test Port Functionality 5.1 Introduction The 82559ER’s NAND-Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. The port pro-vides two f...

GD82559ER — Networking Silicon 34 Datasheet 5.5 TriState This command set all 82559ER Input and Output pins into a TRI-state (HIGH-Z) mode, all internal pull-ups and pull-downs are disabled. This mode is entered by setting the following Test Pin Com- binations: TEST = ‘1, TCK = ‘0, TEXEC = ‘0, TI = ...

Datasheet 37 Networking Silicon — GD82559ER 6. GD82559ER Physical Layer Functional Description 6.1 100BASE-TX PHY Unit 6.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal or a 25 MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its internal transmit digital...

Datasheet 39 Networking Silicon — GD82559ER 6.1.2.3 100BASE-TX Transmit Framing The PHY unit does not differentiate between the fields of the MAC frame containing preamble, Start of Frame Delimiter, data and Cyclic Redundancy Check (CRC). The PHY unit encodes the first byte of the preamble as the “J...

GD82559ER — Networking Silicon 40 Datasheet 6.1.3 100BASE-TX Receive Blocks The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the PHY unit will accurately receive valid data...

Datasheet 41 Networking Silicon — GD82559ER 6.1.4 100BASE-TX Collision Detection 100BASE-TX collisions in half duplex mode only are detected similarly to 10BASE-T collision detection, via simultaneous transmission and reception. 6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution The 82559...

GD82559ER — Networking Silicon 42 Datasheet 6.2.2 10BASE-T Transmit Blocks 6.2.2.1 10BASE-T Manchester Encoder After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs the Manchester encoding. The Manchester code always has a mid-bit transition. If the value...

Datasheet 43 Networking Silicon — GD82559ER All other activity is determined to be either data, link test pulses, Auto-Negotiation fast link pulses, or the idle condition. When activity is detected, the carrier sense signal is asserted to the MAC. 6.2.3.3 10BASE-T Error Detection and Reporting In 10...

GD82559ER — Networking Silicon 44 Datasheet 6.3.1 Description Auto-Negotiation selects the fastest operating mode (in other words, the highest common denominator) available to hardware at both ends of the cable. A PHY’s capability is encoded by bursts of link pulses called Fast Link Pulses (FLPs). C...

Datasheet 45 Networking Silicon — GD82559ER will perform Auto-Negotiation or Parallel Detection with no data packets being transmitted. Connection is then established either by FLP exchange or Parallel Detection. The PHY unit will look for both FLPs and link integrity pulses. The following diagram i...

Datasheet 47 Networking Silicon — GD82559ER 7. PCI Configuration Registers The 82559ER acts as both a master and a slave on the PCI bus. As a master, the 82559ER interacts with the system main memory to access data for transmission or deposit received data. As a slave, some 82559ER control structure...

GD82559ER — Networking Silicon 48 Datasheet 7.1.2 PCI Command Register The 82559ER Command register at word address 04h in the PCI configuration space provides control over the 82559ER’s ability to generate and respond to PCI cycles . If a 0His written to this register, the 82559ER is logically disc...

Datasheet 49 Networking Silicon — GD82559ER 7.1.3 PCI Status Register The 82559ER Status register is used to record status information for PCI bus related events. The format of this register is shown in the figure below. Note that bits 21, 22, 26, and 27 are set to 0b and bits 20, 23, and 25 are set...

GD82559ER — Networking Silicon 50 Datasheet 7.1.4 PCI Revision ID Register The Revision ID is an 8-bit read only register with a default value of 08h for the 82559ER. The three least significant bits of the Revision ID can be overridden by the ID and Revision ID fields in the EEPROM ( Section 4.4, “...

Datasheet 51 Networking Silicon — GD82559ER Note: Bit 3 is set to 1b only if the value 00001000b (8H) is written to this register, and bit 4 is set to 1b only if the value of 00010000b (16H) is written to this register. All other bits are read only and will return a value of 0b on read. This registe...

GD82559ER — Networking Silicon 52 Datasheet Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory or I/O space. Base registers that map to memory space must return a 0b in bit 0. Base registers that map to I/O space must return 1b in bit 0. Base r...

Datasheet 53 Networking Silicon — GD82559ER 7.1.10 PCI Subsystem Vendor ID and Subsystem ID Registers The Subsystem Vendor ID field identifies the vendor of an 82559ER-based solution. The Subsystem Vendor ID values are based upon the vendor’s PCI Vendor ID and is controlled by the PCI Special Intere...

GD82559ER — Networking Silicon 54 Datasheet 7.1.13 Interrupt Pin Register The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins, INTA# through INTD#, a PCI device is connected to. The 82559ER is connected the INTA# pin. 7.1.14 Minimum Grant Register The Min...

GD82559ER — Networking Silicon 56 Datasheet 7.1.20 Data Register The data register is an 8-bit read only register that provides a mechanism for the 82559ER to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written to th...

Datasheet 57 Networking Silicon — GD82559ER 8. Control/Status Registers 8.1 LAN (Ethernet) Control/Status Registers The 82559ER’s Control/Status Register (CSR) is illustrated in the figure below. NOTE: In Figure 23 above, SCB is defined as the System Control Block of the 82559ER, and PMDR is defined...

GD82559ER — Networking Silicon 58 Datasheet MDI Control Register: The MDI Control register allows the CPU to read and write information from the PHY unit (or an external PHY component) through the Management Data Interface. Receive DMA Byte Count: The Receive DMA Byte Count register keeps track of h...

GD82559ER — Networking Silicon 60 Datasheet 8.1.8 Receive Direct Memory Access Byte Count The Receive DMA Byte Count register keeps track of how many bytes of receive data have been passed into host memory via DMA. 8.1.9 Early Receive Interrupt The Early Receive Interrupt register allows the 82559ER...

Datasheet 61 Networking Silicon — GD82559ER Note: The PMDR is initialized at ALTRST# reset only. 8.1.12 General Control Register The General Control register is a byte register and is described below. 8.1.13 General Status Register The General Status register is a byte register which indicates the l...

GD82559ER — Networking Silicon 62 Datasheet 8.2 Statistical Counters The 82559ER provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the 82559ER when it ...

Datasheet 65 Networking Silicon — GD82559ER 9. PHY Unit Registers The 82559ER provides status and accepts management information via the Management Data Interface (MDI) within the CSR space. Acronyms mentioned in the registers are defined as follows: 9.1 MDI Registers 0 - 7 9.1.1 Register 0: Control...

GD82559ER — Networking Silicon 66 Datasheet 9.1.2 Register 1: Status Register Bit Definitions 9 Restart Auto-Negotiation This bit restarts the Auto-Negotiation process and is self-clearing. 1 = Restart Auto-Negotiation process 0 RW SC 8 Duplex Mode This bit controls the duplex mode when Auto-Negotia...

Datasheet 67 Networking Silicon — GD82559ER 9.1.3 Register 2: PHY Identifier Register Bit Definitions 9.1.4 Register 3: PHY Identifier Register Bit Definitions 9.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions 9.1.6 Register 5: Auto-Negotiation Link Partner Ability Register B...

GD82559ER — Networking Silicon 68 Datasheet 9.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions 9.2 MDI Registers 8 - 15 Registers eight through fifteen are reserved for IEEE. 9.3 MDI Register 16 - 31 9.3.1 Register 16: PHY Unit Status and Control Register Bit Definitions Bit(s) Na...

Datasheet 69 Networking Silicon — GD82559ER 9.3.2 Register 17: PHY Unit Special Control Bit Definitions 8 Polarity This bit indicates 10BASE-T polarity. 1 = Reverse polarity 0 = Normal polarity -- RO 7:2 Reserved These bits are reserved and should be set to 0B. 000000 RO 1 Speed This bit indicates t...

GD82559ER — Networking Silicon 70 Datasheet 9.3.3 Register 18: PHY Address Register 9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions 9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions 9.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit Defin...

Datasheet 71 Networking Silicon — GD82559ER 9.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions 9.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions 9.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions 9.3.11 Reg...

Datasheet 73 Networking Silicon — GD82559ER 10. Electrical and Timing Specifications 10.1 Absolute Maximum Ratings Maximum ratings are listed below: Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 85 C Storage Temperature . . . ....

Datasheet 75 Networking Silicon — GD82559ER NOTES: Current is measured on all V CC pins (V CC = 3.3 V). 1. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by the load resistance value. NOTES: Current is measured on all V CC pins (V CC = 3.3 V). ...

GD82559ER — Networking Silicon 76 Datasheet 10.3 AC Specifications NOTES: 1. Switching Current High specifications are not relevant to PME#, SERR#, or INTA#, which are open drain outputs. 2. Maximum current requirements will be met as drivers pull beyond the first step voltage (AC drive point). Equa...

Datasheet 77 Networking Silicon — GD82559ER 10.4 Timing Specifications 10.4.1 Clocks Specifications 10.4.1.1 PCI Clock Specifications The 82559ER uses the PCI Clock signal directly. Figure 26 shows the clock waveform and required measurement points for the PCI Clock signal. Table 22 summarizes the P...

GD82559ER — Networking Silicon 78 Datasheet 10.4.2 Timing Parameters 10.4.2.1 Measurement and Test Conditions Figure 27 , Figure 28 , and Table 24 define the conditions under which timing measurements are done. The component test guarantees that all timings are met with minimum clock slew rate (slow...

Datasheet 79 Networking Silicon — GD82559ER NOTE: Input test is done with 0.1V CC overdrive. V max specifies the maximum peak-to-peak waveform allowed for testing input timing. 10.4.2.2 PCI Timings NOTES: 1. Timing measurement conditions are illustrated in Figure 27 . 2. PCI minimum times are specif...

Datasheet 81 Networking Silicon — GD82559ER 10.4.2.4 EEPROM Interface Timings The 82559ER is designed to support a standard 64x16, or 256x16 serial EEPROM. Table 27 provides the timing parameters for the EEPROM interface signals. The timing parameters are illustrated in Figure 30 . Figure 29. Flash ...

GD82559ER — Networking Silicon 82 Datasheet 10.4.2.5 PHY Timings Figure 30. EEPROM Timings E E C S F L A 1 5 E E S K F L A 1 3 E E D I T 5 1 T 5 2 T 5 4 T 5 3 Table 28. 10BASE-T NLP Timing Parameters Symbol Parameter Condition Min Typ Max Units T56 T nlp_wid NLP Width 10 Mbps 100 ns T57 T nlp_per NL...

Datasheet 83 Networking Silicon — GD82559ER Figure 32. Auto-Negotiation FLP Timings F a s t L i n k P u l s e T 6 0 T 5 8 T 5 9 C l o c k P u l s e D a t a P u l s e C l o c k P u l s e F L P B u r s t s T 6 2 T 6 3 Table 30. 100Base-TX Transmitter AC Specification Symbol Parameter Condition Min Typ...

Datasheet 85 Networking Silicon — GD82559ER 12. Package and Pinout Information 12.1 Package Information The GD82559ER is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in Figure 24 . More information on Intel device packaging is available in the Intel Packaging Handbook, which...

GD82559ER — Networking Silicon 86 Datasheet 12.2 Pinout Information 12.2.1 GD82559ER Pin Assignments Table 15. GD82559ER Pin Assignments Pin Name Pin Name Pin Name A1 NC A2 SERR# A3 VCC A4 IDSEL A5 AD25 A6 PME# A7 VCC A8 AD30 A9 ALTRST# A10 NC A11 VCC A12 LILED A13 TEST A14 NC B1 AD22 B2 AD23 B3 VSS...

GD82559ER — Networking Silicon 88 Datasheet 12.2.2 GD82559ER Ball Grid Array Diagram Figure 25. GD82559ER Ball Grid Array Diagram N C F L A 9 V C C P L X 2 F L A 1 3 / E E D I F L A 1 6 V S S P L E E C S A D 2 A D 3 A D 6 A D 8 V C C P P N C F L A 8 F L A 1 0 V S S P L X 1 F L A 1 4 / E E D O F L C ...