Intel GD82559ER - Manual

Intel GD82559ER

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Table of Contents:

  • Page 2 – ii; Datasheet; Revision History
  • Page 3 – iii; Contents
  • Page 4 – iv
  • Page 7 – Introduction; Suggested Reading; PCI Specification, PCI Special Interest Group.
  • Page 9 – Figure 1; Parallel Subsystem Overview
  • Page 10 – Section 4.3, “Parallel Flash Interface” on page 28; FIFO Subsystem Overview
  • Page 13 – Signal Descriptions; Signal Type Definitions; Address and Data Signals
  • Page 14 – Interface Control Signals
  • Page 15 – System and Power Management Signals; Local Memory Interface Signals
  • Page 16 – Testability Port Signals
  • Page 17 – PHY Signals
  • Page 19 – Initialization Effects on 82559ER Units
  • Page 20 – PCI Interface
  • Page 21 – CLK
  • Page 22 – Flash Buffer Accesses; Figure 4. Flash Buffer Read Cycle
  • Page 23 – Retry Premature Accesses; Figure 6; Figure 5. Flash Buffer Write Cycle
  • Page 24 – Error Handling; After accesses to the Flash buffer; Figure 6. PCI Retry Cycle
  • Page 26 – Memory Write and Invalidate
  • Page 27 – Minimum transfer of one cache line; Read Align; If this bit is set, the 82559ER operates as follows:
  • Page 28 – Clockrun Signal; s. If the system latency is longer than 0.5; Power Management Event Signal
  • Page 29 – Power States; D0 Power State; configuration bit in the Power Management Driver Register (PMDR).
  • Page 30 – D3 Power State; state. The 82559ER can be connected to an auxiliary power source (V; Understanding Power Requirements
  • Page 31 – Auxiliary Power Signal; Register” on page 54; Alternate Reset Signal; When the 82559ER is connected to V; , it may be powered on while the PCI bus is powered off.
  • Page 32 – PCI Reset Signal; Figure 9. Isolate Signal Behavior to PCI Power Good Signal
  • Page 33 – ISOLATE# trailing edge; “Interesting” Packet Events; Direct Packets (with or without type qualification); D3 power state
  • Page 34 – Link Status Change Event; Parallel Flash Interface
  • Page 35 – The 82559ER EEPROM format is shown below in; Figure 11. 64 Word EEPROM Read Instruction Waveform
  • Page 36 – Wo
  • Page 37 – Full Duplex
  • Page 38 – Media Independent Interface (MII) Management Interface; Section 9., “PHY Unit Registers” on page 65
  • Page 39 – mode during the 85
  • Page 40 – TriState
  • Page 43 – GD82559ER Physical Layer Functional Description; 00BASE-TX Transmit Clock Generation
  • Page 45 – 00BASE-TX Transmit Framing; The magnetics module that is external to the PHY unit converts I; and I; Clock; Figure 14. Conceptual Transmit Differential Waveform; Table 4. Magnetics Modules
  • Page 46 – 00BASE-TX Receive Blocks; Adaptive Equalizer; Link integrity fails in the middle of frame reception.
  • Page 47 – 00BASE-TX Collision Detection; Link Integrity; 0BASE-T Functionality; 0BASE-T Transmit Clock Generation
  • Page 48 – 0BASE-T Transmit Blocks; 0BASE-T Manchester Encoder; 0BASE-T Receive Blocks; 0BASE-T Manchester Decoder; Differential pulses of peak magnitude less than 300 mV; and frequency less than 2; and a frequency of at least 2 MHz and not more than 16 MHz.
  • Page 49 – 0BASE-T Error Detection and Reporting; 0BASE-T Collision Detection; Auto-Negotiation Functionality
  • Page 50 – Description
  • Page 51 – LED Description; MDI register 27 in; Figure 15. Auto-Negotiation and Parallel Detect
  • Page 53 – PCI Configuration Registers; PCI Vendor ID and Device ID Registers; Figure 17. PCI Configuration Registers
  • Page 54 – PCI Command Register; If a 0His written to this; Figure 18. PCI Command Register; Reserved; Table 5. PCI Command Register Bits
  • Page 55 – PCI Status Register; Figure 19. PCI Status Register
  • Page 56 – PCI Revision ID Register; Section 4.4, “Serial EEPROM Interface” on page 28; PCI Class Code Register; Table 6. PCI Status Register Bits; Figure 20. Cache Line Size Register
  • Page 57 – PCI Latency Timer; Figure 21. Base Address Register for Memory Mapping; Base Address
  • Page 58 – CSR Memory Mapped Base Address Register; Figure 22. Base Address Register for I/O Mapping
  • Page 59 – PCI Subsystem Vendor ID and Subsystem ID Registers; Table 7; Capability Pointer
  • Page 60 – or V; Table 8. Power Management Capability Register
  • Page 62 – Data Register; Table 10. Ethernet Data Register
  • Page 63 – Control/Status Registers; SCB General Pointer:
  • Page 64 – Management Driver Register” on page 60; System Control Block Status Word
  • Page 66 – Receive Direct Memory Access Byte Count; The Flow Control Register contains the following fields:; Power Management Driver Register; Table 11. Power Management Driver Register
  • Page 67 – The PMDR is initialized at ALTRST# reset only.; General Control Register; Table 13. General Status Register
  • Page 68 – Statistical Counters
  • Page 71 – PHY Unit Registers; Register 0: Control Register Bit Definitions
  • Page 72 – Register 1: Status Register Bit Definitions
  • Page 73 – Register 2: PHY Identifier Register Bit Definitions
  • Page 74 – Register 6: Auto-Negotiation Expansion Register Bit Definitions; Registers eight through fifteen are reserved for IEEE.; Register 16: PHY Unit Status and Control Register Bit Definitions
  • Page 75 – Register 17: PHY Unit Special Control Bit Definitions
  • Page 76 – Register 18: PHY Address Register
  • Page 77 – Register 26: Equalizer Control and Status Bit Definitions
  • Page 79 – Electrical and Timing Specifications; Absolute Maximum Ratings; Maximum ratings are listed below:; DC Specifications; Table 15. General DC Specifications
  • Page 81 – Figure 24. RBIAS100 Resistance Versus Transmitter Current
  • Page 82 – AC Specifications; Figure 25. RBIAS10 Resistance Versus Transmitter Current
  • Page 83 – Timing Specifications; Clocks Specifications; PCI Clock Specifications; Figure 26. PCI Clock Waveform; Table 23. X1 Clock Specifications
  • Page 84 – Timing Parameters; Measurement and Test Conditions; define the conditions under which timing measurements are; Figure 27. Output Timing Measurement Conditions
  • Page 85 – PCI Timings; signal in; Table 24. Measure and Test Condition Parameters
  • Page 87 – EEPROM Interface Timings; Figure 29. Flash Timings for a Read Cycle; F L A D D R; Table 27. EEPROM Timing Parameters
  • Page 88 – PHY Timings; Figure 30. EEPROM Timings; Table 29. Auto-Negotiation FLP Timing Parameters
  • Page 89 – Table 30. 100Base-TX Transmitter AC Specification
  • Page 91 – Package and Pinout Information; Package Information
  • Page 92 – Pinout Information
  • Page 94 – GD82559ER Ball Grid Array Diagram
Loading the manual

GD82559ER Fast Ethernet**
PCI Controller

Networking Silicon

Datasheet

Product Features

■

Optimum Integration for Lowest Cost
Solution

— Integrated IEEE 802.3 10BASE-T and

100BASE-TX compatible PHY

— Glueless 32-bit PCI master interface

— 128 Kbyte Flash interface

— Thin BGA 15mm

2

package

— ACPI and PCI Power Management

— Power management event on

“interesting” packets and link status
change support

— Test Access Port

■

High Performance Networking Functions

— Chained memory structure similar to the

82559,82558, 82557, and 82596

— Improved dynamic transmit chaining

with multiple priorities transmit queues

— Full Duplex support at both 10 and 100

Mbps

— IEEE 802.3u Auto-Negotiation support

— 3 Kbyte transmit and 3 Kbyte receive

FIFOs

— Fast back-to-back transmission support

with minimum interframe spacing

— IEEE 802.3x 100BASE-TX Flow

Control support

— Low Power Features

— Low power 3.3 V device

— Efficient dynamic standby mode

— Deep power down support

— Clockrun protocol support

Document Number: 714682-001

Revision 1.0

March 1999

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Summary

Page 2 - ii; Datasheet; Revision History

GD82559ER - Networking Silicon ii Datasheet Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sal...

Page 3 - iii; Contents

Datasheet iii Networking Silicon — GD82559ER Contents 1. INTRODUCTION ................................................................................................................. ............ 1 1.1 GD82559ER Overview .................................................................................

Page 4 - iv

GD82559ER — Networking Silicon iv Datasheet 6.1.2 100BASE-TX Transmit Blocks ......................................................................... 37 6.1.3 100BASE-TX Receive Blocks .......................................................................... 40 6.1.4 100BASE-TX Collision Detection...

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