Page 3 - Contents; Introduction
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual iii Contents Contents 1 Introduction .................................................................................................................................... 1 1.1 Scope.................................
Page 4 - EEPROM Interface
iv Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents 5 EEPROM Interface ....................................................................................................................... 25 6 Host Software Interface ..................................
Page 5 - Programming Recommendations; Appendices; Wake-up Functionality; Figures
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual v Contents 7.3.6 100BASE-TX Receive Error Frame Counter: Register 21 ................................... 127 7.3.7 Receive Symbol Error Counter: Register 22 .........................................................
Page 6 - Tables
vi Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents 20 Transmit Buffer Descriptor.......................................................................................................... 8521 Load Microcode Command Format ...............................
Page 8 - Revision History
viii Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents Revision History Date Revision Description January 2006 1.3 • Added Section 2.2.3.2., “82551ER Features.” • Modified the title of Appendix B. September 2005 1.2 • Corrected minor typing errors. Sep...
Page 9 - EtherExpress; Scope
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 1 Introduction 1 This document is intended for use as a software technical reference manual for the Intel ® 10/100 Mbps Fast Ethernet controller family, which includes the 82557, 82558, 82559, 82550, and 82551, ...
Page 10 - Document Conventions; Device References; specific differences and exceptions will be documented.; Numbering; Decimal numbers will not be followed by a suffix.; Signal Name Representation; used for this purpose:
2 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Introduction 1.2 Document Conventions 1.2.1 Device References This document encompasses information for all members of the Intel Fast Ethernet controllers: 82551, 82550, 82559, 82558, 82557 and the 82562. Note...
Page 13 - Adapter and Controller Overview; Adapters based on an Intel; Adapter Block Diagram; The main components of Intel Fast Ethernet adapters are:; Figure 1. 82557 Network Interface Card Block Diagram
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 5 Adapter and Controller Overview 2 Adapters based on an Intel ® 8255x device support the ANSI/IEEE 802.3u standard for 100BASE- TX (100 Mbps operation) and 10BASE-T (10 Mbps operation). 2.1 Adapter Block Diagra...
Page 14 - Intel Fast Ethernet MAC Features; Early transmit complete indication.
6 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Adapter and Controller Overview 2.2 Intel Fast Ethernet MAC Features 2.2.1 82557 Features • Glueless 32-bit, zero wait state PCI bus master interface compliant with PCI Specification, Revision 2.1. • 10 and 10...
Page 15 - Working with the Physical Layer; Mbps only connections, the 82557 can be interfaced to the Intel
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 7 Adapter and Controller Overview • Optional Flash support up to 64 Kbytes. (The 82557 is capable of larger Flash size support.) 2.2.3 82559, 82550, 82551, and 82562 Features The 82559, 82550, and 82551 devices ...
Page 17 - Power Management Interface; Low Power Mode Requirements; PCI Bus Power Management Interface Specification, Revision 1.0.; Device Power States
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 9 Power Management Interface 3 The 82557 has no power management support. The 82558 added support for the Advanced Configuration and Power Interface (ACPI) Specification and limited support for Wake on LAN (WOL)...
Page 18 - Link Operation; and Revision ID” on page 13
10 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Power Management Interface 3.4 Link Operation In the D0 state, the device maintains an active link. The 82558 B-step (refer to Table 2, “Device and Revision ID” on page 13 ) and later devices also maintain an...
Page 19 - PCI Interface; PCI Configuration Space; PCI configuration space of each individual PCI device.; Table 1. PCI Configuration Space
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 11 PCI Interface 4 4.1 PCI Configuration Space One of the most important functions for enabling superior configurability and ease of use is the ability to relocate PCI devices in the address spaces. By default P...
Page 20 - Figure 2. Command Register
12 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual PCI Interface 4.1.1 Vendor ID (Offset 0) This field identifies the device manufacturer. For the 82557 B-step this field equals 8086h. For the 82557 C-Step, 82558, and 82559, this field is automatically loaded...
Page 21 - Figure 3. Command Register; Table 2. Device and Revision ID
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 13 PCI Interface 4.1.5 Revision (Offset 8) This register specifies a device specific revision identifier. For the 82557 C-Step, 82558, and 82559, this field may be automatically loaded from the EEPROM at power o...
Page 23 - Figure 5. Base Address Register for Memory Mapping; Figure 6. Base Address Register for I/O Mapping
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 15 PCI Interface 4.1.10 Built in Self Test (Offset F) This optional register is used for control and status of Built in Self Test (BIST). This register is hard-wired to 0 indicating that the devices do not suppo...
Page 24 - Expansion ROM Base Address Register (Offset 30); Table 3. Base Address Register Summary
16 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual PCI Interface The 8255x requires one BAR for I/O mapping and one BAR for memory mapping of these registers anywhere within the 32-bit memory address space. The driver determines which BAR (I/ O or Memory) is ...
Page 25 - Figure 7. Expansion ROM Base Address Register
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 17 PCI Interface the Flash. The 82557 implements this register regardless of the presence or absence of a Flash component on the adapter. For the 82558 and later Fast Ethernet controllers, this register is only ...
Page 26 - Power Management PCI Configuration Registers; Power Management Capabilities (Offset DE); Table 4. Power Management Capabilities
18 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual PCI Interface 4.1.17 Max_Lat / Min_Gnt (Offset 3E) These registers specify the device settings for Latency Timer values. For both registers, the value specifies a period of time in units of ¼ microsecond. Min...
Page 28 - Table 5. Power Management Control/Status Register
20 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual PCI Interface While wake-up events are not allowed in the D0 power state, hardware does not automatically preclude this functionality. To ensure that wake-up events are not generated when in D0, software must...
Page 29 - Ethernet Power Consumption Registers (Offset E2h); PCI Command Usage; Table 6. Power Consumption / Dissipation Reporting
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 21 PCI Interface 4.1.18.5 Ethernet Power Consumption Registers (Offset E2h) The Data Register is an 8-bit read-only register providing a mechanism for the device to report state dependent maximum power consumpti...
Page 30 - Table 7. Generated PCI Commands; Memory Write and Invalidate; Configuration Space”
22 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual PCI Interface Table 7. Generated PCI Commands The controllers do not generate I/O commands, Interrupt Acknowledge cycles, or Configuration cycles. The controllers also do not support Dual Address Cycle (DAC)....
Page 31 - Read Align; If this bit is set, the device operates as follows:; Odd Byte Alignment Support
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 23 PCI Interface device may start the next cycle using either MW or MWI according to the conditions listed above. If the PCI latency timer or the 82558 (or later generation device) arbitration counter expires du...
Page 33 - EEPROM and then read Flash memory or vice versa.
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 25 EEPROM Interface 5 The 8255x has a local memory interface that provides access to a serial EEPROM and optional Flash device. All controllers implement these interfaces using multiplexed pins. Since the interf...
Page 35 - Host Software Interface; configurations only refer to the simplified memory mode.; The Shared Memory Architecture
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 27 Host Software Interface 6 The 8255x LAN controllers establish a shared memory communication system with the host CPU. Software controls the device by writing and reading data to and from this shared memory sp...
Page 36 - Figure 8. 8255x Memory Architecture
28 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface The CBL consists of a linked list of individual action commands in structures called Command Blocks (CBs). The CBs contain command parameters and status of the action commands. Action ...
Page 37 - Initializing the LAN Controller; LAN Controller Addressing Format; Table 8. Reset Commands
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 29 Host Software Interface 6.2 Initializing the LAN Controller A hardware or software reset prepares the 8255x for normal operation. Since the PCI Specification already provides automatic configuration of many c...
Page 38 - Table 9. Device Addressing Formats
30 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface To support linear addressing, the device should be programmed as follows: • Load a value of 00000000h into the CU base using the Load CU Base Address SCB command. • Load a value of 000...
Page 39 - Controlling the Device; Table 10. Alignment Requirements for 8255x Data Structures
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 31 Host Software Interface As the table above indicates, the 8255x have the same alignment restrictions with one exception: The 82558, and 82559 have a limited capability to support odd byte aligned buffers. 6.3...
Page 42 - SCB Status Word; Table 12. System Control Block; Figure 9. SCB Status Word
34 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface — A flow control pause frame was received (FCP Interrupt). This does not apply to the 82557. Note: TNO interrupts should be avoided. Protocol stacks automatically retry failed transmit...
Page 43 - Table 13. SCB Status Word Bits Descriptions
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 35 Host Software Interface malfunctions. It is simply ignored by the device. Also, any 0 bits in the interrupt acknowledge command have no effect, whether the interrupt is pending or not. Table 13. SCB Status Wo...
Page 44 - Figure 10. SCB Command Word
36 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface Note: The SCB Status word is not updated immediately in response to SCB commands. For example, the CU status will remain in the idle state for a period of time after the CU start comma...
Page 45 - Table 14. SCB Command Word Bits Descriptions
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 37 Host Software Interface When software wants to issue an action command, it should write to the Command byte. The CUC and RUC fields of the Command byte specify the actions to be performed by the 8255x. The co...
Page 47 - SCB General Pointer; for the different commands.
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 39 Host Software Interface 6.3.2.3 SCB General Pointer The SCB General Pointer is a 32-bit entity, which points to various data structures depending on the command in the CUC or RUC field. The two tables below i...
Page 48 - Statistical Counters; Table 16. SCB General Pointer for the RU Command; Table 17. Statistical Counters
40 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.3.2.4 Statistical Counters The 8255x provides information for network management by providing on-chip statistical counters that track a variety of events associated with both transmi...
Page 51 - PORT Interface; Port function selection code on AD3:AD0; Table 18. Port Register Location; Table 19. Port Selection Function
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 43 Host Software Interface 3. Write zeros to the last Dword in this area. This can be done before or after step 2. 4. Write the Dump Statistical Counters or Dump and Reset Statistical Counters command into the C...
Page 52 - PORT Software Reset; command checks the following blocks:
44 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.3.3.1 PORT Software Reset The Port Software Reset is synonymous with the software reset and is used to issue a complete reset to the device. Software must wait for ten system clocks ...
Page 53 - Port Selective Reset; in; EEPROM Control Register; read from and enable writes to an external EEPROM component.
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 45 Host Software Interface Note: The self-test does not generate an interrupt or similar indicator to the host CPU upon completion. 6.3.3.3 Port Selective Reset The Port Selective Reset is useful when only the d...
Page 54 - CPU Accesses to the EEPROM; EEPROM. There should be no other local bus activity at this time.; Table 21. EEPROM Control Register Locations; Figure 12. EEPROM Control Register
46 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface The serial EEPROM or equivalent integrated circuit (IC) stores configuration data for the controller and the adapter. The EEPROM is a serial in and serial out device. Serial EEPROMs ra...
Page 55 - Software Determination of EEPROM Size
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 47 Host Software Interface 6.3.4.2 Software Determination of EEPROM Size To determine the size of the EEPROM, software may use the following steps. Note: This algorithm will only work if the EEPROM drives a dumm...
Page 56 - Software Read Access from the EEPROM; Figure 13. EEPROM Read Timing Diagram
48 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.3.4.3 Software Read Access from the EEPROM To read from the EEPROM, software is required to perform the following steps. The example is a read from address 02h (0000 0010b). Note: Si...
Page 57 - Software Write Access to the EEPROM; Management Data Interface Control Register; Table 24. MDI Control Register Location
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 49 Host Software Interface 6.3.4.4 Software Write Access to the EEPROM Write access to the EEPROM is similar to the read access outlined above, with the differences of a write opcode and step 4: 1. Activate the ...
Page 58 - MDI Control Register; The sequence of events for a MDI write cycle is:; Table 25. Management Data Pins; Table 26. MDI Control Register Bits
50 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface The MII Management Interface allows software to have direct control over a MII compatible PHY through a control register in the device. This allows the driver software to place the PHY...
Page 59 - MDI Read cycle; Receive Byte Count Register
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 51 Host Software Interface b. Interrupt Enable (bit 29) = 1 or 0 c. Opcode (bits 27:26) = 01b (write) d. PHYAdd = the PHY address from the MDI register e. RegAdd = the register address of the specific register t...
Page 60 - Early Receive Interrupt; Table 27. Receive Byte Count Register Location; Table 28. Early Receive Interrupt Register Location
52 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface to increase performance by decreasing NOS receive latencies. However, most software early interrupt schemes would increase CPU utilization and software complexity. Thus, use of this re...
Page 61 - Flow Control Register; Table 29. Flow Control Registers Location
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 53 Host Software Interface words before the end of the frame. If the Type/Length field contains a Type value, the device does not generate an early interrupt, except in the case where the Type value is 8137h (IP...
Page 62 - Power Management Driver Register; Table 30. Flow Control Threshold Values
54 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface • Bits 23:21 - Reserved. These bits are reserved. • Bit 20 - FC Paused Low. This read only bit is an indication of the device flow control state. It is set by the device when it receiv...
Page 63 - Table 31. Power Management Driver Register Location; Table 32. Power Management Driver Register
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 55 Host Software Interface The PMDR has evolved over time in the various Intel Fast Ethernet controllers. The PMDR bits for the 82558 and 82559 are described below. Note: Not all bits are meaningful in the diffe...
Page 64 - General Control Register; Table 33. General Control Register Location; Table 34. General Control Register; Table 35. General Status Register Location
56 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.3.10 General Control Register The General Control register provides control over some general purpose features in the 82559. It is an 8-bit field at offset 1Ch of the CSR. This regis...
Page 65 - Shared Memory Structures; device while the CBL and RFA reside in main system memory.; Action Commands and Operating Modes; Table 10, “Alignment; Table 36. General Status Register
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 57 Host Software Interface 6.4 Shared Memory Structures The 8255x shared memory structures consist of the Command Block List (CBL) and the Receive Frame Area (RFA) and are controlled by the SCB portion of the CS...
Page 66 - General Action Command Format; execution (also common to all action commands) is described below.; Beginning Execution; delayed by RU activity.; Completing Execution; Table 37. Operation Codes; Figure 14. General Action Command Format
58 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.4.1.1 General Action Command Format The format common to all action commands and the algorithms for beginning and completing the execution (also common to all action commands) is des...
Page 67 - Specific Action Commands; Figure 15. NOP Command Format
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 59 Host Software Interface The following sequence is performed by the CU at the completion of execution of an action command: 1. The devices writes command specific status to the status word of the current CB (u...
Page 68 - Figure 16. Individual Address Setup Command Format
60 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface After reading the command and determining it is a NOP, the device CU performs the following sequence: 1. Begins execution of the NOP action command. 2. Prepares the status word with C ...
Page 70 - Figure 17. Configure Command Format
62 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface The individual bit fields of the configure command is another area where there are numerous differences between the controllers (82557, 82558, 82559, etc.). Therefore, a complete confi...
Page 73 - Configuration Parameters
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 65 Host Software Interface 6.4.2.3.1 Configuration Parameters The interpretation of the fields from the configuration byte maps are: • BYTE 0. Table 40. 82559 Configuration Byte Map Byte D7 D6 D5 D4 D3 D2 D1 D0 ...
Page 80 - Table 45. Extended Statistics Functionality
72 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface Default - 0.Recommended - 0. — Bit 0 - Late SCB = Late SCB Update. This bit is reserved on the 82558 and 82559 and should be set to 0 on those devices.This bit only has meaning on the ...
Page 84 - Table 47. 82558 B-step Configuration Block ARP Frame IP Address
76 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface Default - 1.Recommended - Depends on the NOS and driver environment. • BYTE 11. — Bits 2:0 - Linear Priority. These bits are reserved on the 82558 and 82559 and should be set to 000b o...
Page 85 - Table 48. 82558 B-step ARP Frame IP Address Mapping
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 77 Host Software Interface Similarly, the value at offset 14 of the configuration block is compared to the byte at offset 40 in ARP frames without a VLAN header and to byte 44 in ARP frames with a VLAN header.Th...
Page 87 - Table 49. Full Duplex Functionality
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 79 Host Software Interface byte (7Eh) will be transmitted to pad (in other words, fill) the minimum frame length. The CRC will include the padded bytes. If padding is disabled, no padding bytes will be added eve...
Page 90 - Figure 18. Multicast Setup Command Format
82 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface In the case of a port selective reset, the execution machine maintains configuration registers for the device. In the case of a port software reset or a hardware reset, the device reve...
Page 91 - Figure 19. Transmit Command Format
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 83 Host Software Interface The transmit DMA transfers the list of multicast addresses from memory to the execution machine through the transmit FIFO. The CU performs the following sequence: 1. Begins execution o...
Page 93 - Figure 20. Transmit Buffer Descriptor
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 85 Host Software Interface The 82558 and 82559 also offer a more advance transmit command block. When they are configured to use extended TCBs, the device reads an 8-Dword TCB from host memory into its internal ...
Page 94 - Dynamic TBD Mode; two features defined.
86 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.4.2.5.1 Dynamic TBD Mode Note: Dynamic TBD mode only exists in the 82558 and 82559 devices. It is not a valid mode for the 82557. The 82557 requires all TBDs to be setup by the drive...
Page 95 - Transmit Command Operation
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 87 Host Software Interface 5. Fetch data if the transmit buffer pointer is zero (invalid) in the second TBD or poll the TBD. 6. Finish the transmission if the EL bit is set. 6.4.2.5.2 Transmit Command Operation ...
Page 96 - WILL NOT
88 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface While the CU pre-fetches the address and byte count of one buffer, the transmit DMA is transferring the previous buffer to the transmit byte machine. Completion of a buffer transfer by...
Page 97 - Delayed CNA Interrupts; be beneficial for other systems as well.)
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 89 Host Software Interface 2. The SFD field is transferred. 3. Start CRC calculation. 4. Read and transfer the 6 destination address bytes from the transmit FIFO. 5. If the no source address insertion configurat...
Page 98 - Figure 21. Load Microcode Command Format
90 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface • The device received a frame and generated a receive interrupt. If neither of these events occurred, the controller generates a CNA interrupt when the CID time interval has elapsed. T...
Page 99 - Figure 22. Dump Command Format
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 91 Host Software Interface The load microcode command instructs the device to download microcode data from host memory into its internal microcode RAM. The microcode data is organized as a 64-Dword memory block ...
Page 105 - Figure 23. Diagnose Command Format
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 97 Host Software Interface 6.4.2.8 Diagnose (111b) The diagnose command triggers an internal self-test procedure that checks the internal device hardware. Its format is illustrated below. 126 Micromachine Input ...
Page 107 - Receive Operation; Receive Frame Area; Simplified RFA Structure
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 99 Host Software Interface During Phase 1, the linear feedback shift register (LFSR), exponential backoff time-out, slot time, and collision counters are checked. The test is performed in the following manner: 1...
Page 108 - Receive Frame Descriptor Format; RECEIVE FRAME AREA
100 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.4.3.1.2 Receive Frame Descriptor Format Figure 24. Simplified Memory Structure Figure 25. Receive Frame Descriptor Format Offset Command Word Bits 31:16 Status Word Bits 15:0 00h EL...
Page 109 - Table 52. RFD Status Bit Descriptions
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 101 Host Software Interface Link Address The link address is a 32-bit offset to the next RFD. It is added to the RU base. The link address of the last frame can be used to form a cyclical link to the first RFD. ...
Page 110 - Initial Receive Frame Area Structure; The link offset of each RFD in the list should point to the next RFD.; Operation of Frame Reception; discarded, they are still counted in the short frame counter.; Table 53. Actual Count in Header RFD
102 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.4.3.2 Initial Receive Frame Area Structure To enable the device to receive frames, software must setup the following structure: 1. The SCB general pointer in the SCB should point to...
Page 111 - Configuring the Next RFD
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 103 Host Software Interface For every frame, the RU configures a RFD in memory. The loading of each buffer is done by the receive DMA in parallel with pre-fetching the next buffer by the RU. After completing fra...
Page 113 - Example 2. Numerical Calculation; Command Unit and Receive Unit Operation; Starting and Completing Control Commands; control command is accepted:; Generating and Acknowledging Interrupts
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 105 Host Software Interface Example 2. Numerical Calculation Assume the following incoming packet: SA DA Type F1 F5 54 79 E7 9E F5 CRC S 0 = F5F1+7954 = 6F45, C 0 = 1 S 1 = 6F45 + 9EE7 + 1 = 0E2D, C 1 = 1 S 2 = ...
Page 114 - Command Unit Control; Completion of Execution.; CU Start Command
106 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.5.3 Command Unit Control The CU is the 8255x logical unit that executes action commands from the command block list (CBL). This section describes how software controls the execution...
Page 115 - CU Resume Command; goes back to the suspended state.; CU Control Commands Response; and; Table 54. CU Control Commands: Actions at Acceptance Time
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 107 Host Software Interface 6.5.3.2 CU Resume Command The CU Resume (CU_RESUME) command resumes CU operation. The 8255x completes the following sequence: 1. If the CU is in the suspended state it goes to the act...
Page 116 - Receive Unit Control; initial RU state after reset.; Table 56. RU Control Commands: Actions at Acceptance Time
108 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.5.4 Receive Unit Control The receive unit (RU) is the logical unit that receives frames and stores them in memory. It uses free buffers and descriptors prepared by the CPU. This sec...
Page 117 - Completion of Reception.; RU Start Command; NOT
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 109 Host Software Interface Frames arrive at the device independent of the state of the RU. When a frame is arriving, the 8255x is referred to as actively receiving, even when the RU is not in the ready state an...
Page 118 - RU Resume Command; Updating SCB Status; Flow Control
110 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 6.5.4.2 RU Resume Command The RU Resume (RU_RESUME) command resumes frame reception. The RU performs the following tasks: 1. The RU goes to the ready state and configures a new RFD if...
Page 119 - PHY Based Flow Control; should not be used at the same time as frame based flow control.; Frame Based Flow Control; of frame based flow control and is described later in; Protocol Description; includes the following fields:
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 111 Host Software Interface 6.6.1 PHY Based Flow Control The 82558 supports the PHY based flow control scheme known as the “Bay Flow Control” scheme. This scheme is supported only when the 82558 is operating usi...
Page 120 - Pause Operation; The 82557 does not support flow control functionality.; Table 57. Flow Control Frame Format
112 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface A flow control frame is identified by a special type field (bytes transmitted left to right): 88 to 80. The reception of a FC frame can be done either through the regular individual a...
Page 121 - Transmit Flow Control; defined in
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 113 Host Software Interface Flow control is set by three configuration bits: one for transmit and two for receive flow control. The default setting is off ( Section 6.4.2.3, “Configure (010b)” ). Software can in...
Page 123 - Priority Aware Frame Based Flow Control; Priority Flow Control Operation; illustrates a flow control frame.; Table 58. Flow Control Configuration Bits
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 115 Host Software Interface 6.6.3 Priority Aware Frame Based Flow Control The 82558 and later generation controllers have the ability to respond to priority aware frame based flow control frames. Their operation...
Page 124 - Half Duplex Flow Control; Modification in Switched Environments”; Collision Backoff Modification in Switched
116 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface The priority field is the field that differentiates between pause and pause low frames. Only the three least significant bits in this byte are considered. These three bits are compare...
Page 125 - Physical Layer Interface; different PHYs, including the 82555, are included in
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 117 Physical Layer Interface 7 Intel Fast Ethernet adapters all have a physical layer (PHY) component that interfaces the network adapter to the wire. The MAC component of the adapter interfaces to the PHY component via the...
Page 126 - MDI Register Set; The generic MDI register set is defined as follows:; Figure 26. Management Frame Structure
118 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Physical Layer Interface This structure allows a controller, or other management hardware, to query the PHY for the status of the link or configure the PHY to one of many modes. The next section discusses the MDI regist...
Page 127 - Control Register: Register 0; The Control register provides control over the PHY functions.
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 119 Physical Layer Interface The individual registers are defined in the following subsections using the following conventions: R: ReadW: WriteRO: Read onlySC: Self clearing Note: The default values listed for the 82555 reg...
Page 128 - Status Register: Register 1
120 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Physical Layer Interface 7.2.2 Status Register: Register 1 For maximum accuracy of link status, the Auto-Negatiation Complete bit (bit 5), should be polled at a continuous interval of at least 300 milliseconds. After th...
Page 129 - Identification Registers: Registers 2 and 3; Table 61. 24-bit OUI Identification Number
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 121 Physical Layer Interface 7.2.3 Identification Registers: Registers 2 and 3 The 32-bit ID register provides a mechanism for software to determine which PHY is present. The contents of these registers differ depending on ...
Page 130 - Auto-Negotiation Advertisement Register: Register 4
122 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Physical Layer Interface 7.2.4 Auto-Negotiation Advertisement Register: Register 4 This register contains the advertisement ability of the PHY. It is used by software to determine the highest common denominator technolo...
Page 131 - Auto-Negotiation Expansion Register: Register 6
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 123 Physical Layer Interface NOTE: The Auto-Negotiation Link Partner Ability Register is read only. 7.2.6 Auto-Negotiation Expansion Register: Register 6 Register 6 contains supplemental information used by the auto-negotia...
Page 132 - Status and Control Register: Register 16
124 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Physical Layer Interface 7.3 Intel 82555 Specific Registers Note: The Intel MAC/PHY silicon devices (82558, 82559, 82550, and 82551) use the 82555 as the base for their integrated PHY units. Therefore, the information c...
Page 133 - Special Control Register: Register 17
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 125 Physical Layer Interface 7.3.2 Special Control Register: Register 17 Bit Name R / W Description Default 15 Scrambler Bypass RW 1 = Bypass Scrambler0 = Normal operation 0 14 4/5 Bypass RW 1 = Bypass 4-bit to 5-bit0 = Nor...
Page 134 - Clock Synthesis Test and Control Register: Register 18
126 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Physical Layer Interface 7.3.3 Clock Synthesis Test and Control Register: Register 18 7.3.4 100BASE-TX Receive False Carrier Counter: Register 19 7.3.5 100Base-TX Receive Disconnect Counter: Register 20 Bit Name R / W D...
Page 135 - 00BASE-TX Receive Error Frame Counter: Register 21
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 127 Physical Layer Interface 7.3.6 100BASE-TX Receive Error Frame Counter: Register 21 7.3.7 Receive Symbol Error Counter: Register 22 7.3.8 100BASE-TX Receive EOF Error Counter: Register 23 7.3.9 10BASE-T Receive EOF Error...
Page 136 - Equalizer Control and Status Register: Register 26; command, and bits 12:0 contain the data field for the command.
128 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Physical Layer Interface 7.3.11 Equalizer Control and Status Register: Register 26 This register is used to control and monitor the operation of the 8255x PHY module equalizer (excluding the 82557 since it does not have...
Page 137 - Special Control Register: Register 27
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 129 Physical Layer Interface 7.3.12 Special Control Register: Register 27 011 Write to ASD configuration register 2 [9] Breakdown ASD counters.[8] Selects signal detections or transitions.[7:6] Slow mode adaptation time con...
Page 138 - Auto-Negotiation Functionality; lists the priority of each of the technologies.; Table 63. LED Switch Control
130 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Physical Layer Interface 7.4 Auto-Negotiation Functionality The PHY units of the 8255x devices (excluding the 82557) all support auto-negotiation (N-Way). Auto-negotiation is an automatic configuration scheme designed t...
Page 139 - Parallel Detection; Table 64. Technology Ability Field Bit Assignments; Table 65. Technology Priority
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 131 Physical Layer Interface To detect the correct technology, the two register fields are ANDed together to obtain the highest common denominator. This value is used to map into a priority resolution table used by the MAC ...
Page 140 - Vendor-Specific PHY Programming
132 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Physical Layer Interface 7.5 Vendor-Specific PHY Programming The Intel ® PRO/100B adapters are designed to support Intel and third-party PHYs using TX and T4 PHYs. The PHYs will be capable of auto-negotiation, but certa...
Page 143 - Adapter Initialization; PHY Detection and Initialization
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 135 Programming Recommendations 8 8.1 Adapter Initialization The initialization code can be broadly split in the following code modules: • 8255x initialization • PHY detection and initialization • NOS specific initializatio...
Page 144 - NOS Specific Initialization; Transmit Processing; For dynamic chaining:; Frame Reception; memory. Software cannot selectively disable these interrupts.
136 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Programming Recommendations 8.1.3 NOS Specific Initialization Software should be written so that NOS specific interface routines call lower level driver routines. This will enable code re-use. 8.2 Transmit Processing Fr...
Page 145 - Interrupt Processing
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 137 Programming Recommendations 8.4 Interrupt Processing The 8255x supports latched level triggered interrupts. Interrupts can be shared in the system if the software and NOS support this mechanism. The SCB Command and Stat...
Page 147 - This appendix applies only to the 82558 and subsequent devices.
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 139 Wake-up Functionality A Note: This appendix applies only to the 82558 and subsequent devices. Wake-up functionality was first introduced with the 82558 A-step. This component is capable of being brought out of a power m...
Page 148 - Low Power Modes; D1, the PHY and CSMA units are always active.; Power Management Context After Reset; source. It is connected to the system auxiliary power good signal.; power source is used and wake up from D3
140 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Wake-up Functionality A.2 Low Power Modes The device wake-up capabilities require internal PHY and CSMA blocks to be fully active. When the controller is set into the D2 or D3 power state and wake up is disabled, the in...
Page 149 - Auxiliary Power Support; reset. In this case wake up from D3; is not supported. Both the PME enable and status bits; Fixed Packet Filtering; without an active clock on the PCI bus.
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 141 Wake-up Functionality A.3.1 Auxiliary Power Support The LISTAT signal should be 0 after a hardware reset. For WOL mode, the default value after power up reset (ALTRST# is asserted) of the PME enable and status bits are:...
Page 150 - Address Matching
142 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Wake-up Functionality A.4.1 Magic Packet* The 82558 and later generation controllers (except the 82559ER) are capable of generating a wake- up event upon reception of a Magic Packet. This feature is enabled by setting a...
Page 151 - Configuration Bits for Fixed Wake-up filters; Table 66. Fixed Wake-up Configuration Bits
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 143 Wake-up Functionality The controller only filters the shaded fields in the frame format above. Only the two low bytes of the IP address are compared. The controller does not check for VLAN type (any frame with type diff...
Page 152 - Link Status Event
144 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Wake-up Functionality A.5 Link Status Event The controller may be configured to wake up the system on link disconnect and connect events. The link status wake-up enable bit was added to the configuration command for the...
Page 153 - Flexible Filtering Terminology
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 145 Wake-up Functionality • Multiple IP address recognition A.6.1 Flexible Filtering Terminology Filter. A filter is a set of a signature and segments generated for a specific frame format. Each filter defines one frame tha...
Page 154 - Wake-up Packet Storage; controller may wake up the system without storing the packet.; 2559 and Later Generation Device Implementation; support Magic Packet.; Load Programmable Filter Command Structures; Programmable Filters Data Structure.; Programmable filters may have one of two types:; Figure 27. Command Block Structure
146 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Wake-up Functionality A.6.3 Wake-up Packet Storage The device uses its internal registers for packet storage during power down mode. Only the first 124 bytes of a frame may be filtered and stored by the device. The resi...
Page 158 - CRC Word calculation of a Flexible Filter; The 82559 Port commands are summarized in
150 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Wake-up Functionality A.7.2 CRC Word calculation of a Flexible Filter A.7.3 Port Dump Wake Up Packet The 82559 Port commands are summarized in Table 67 , which also includes the new Dump Wake- up Packet command: Followi...
Page 159 - Power Management Software Flow; the power down states.; Power Down without Wake-up Capabilities; Clear the PME enable bit in the PMCSR to the PME disable state.; Table 68. Dump Data Structure
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 151 Wake-up Functionality The sequence of events after a Dump Wake-up command that the 82559 performs are: 1. Write the byte count field at Dword 1. This field contains the actual number of bytes posted in the host memory. ...
Page 160 - Power Down with Wake-up Capabilities; required for the power down state, then this step is redundant.
152 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Wake-up Functionality CLK is inactive and 10 mA if it is active. The deep power down state due to PME disable is enabled in the EEPROM. A.7.4.2 Power Down with Wake-up Capabilities The 82559 provides wake-up capabilitie...
Page 161 - Dummy Wake-up Sequence
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 153 Wake-up Functionality 6. The device statistic counters are corrupted during power down state. Therefore, the driver should clear the statistic counters by first issuing load dump counters address and then a dump and res...
Page 163 - This appendix applies to the Intel; IPCB; useful combinations of the IPCB fields.; Table 69. IPCB Structure
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 155 82550 and 82551QM Specific Information B This appendix applies to the Intel ® 82550 and 82551QM devices. B.1 IPCB The IP command block (IPCB) is new and used to activate the new offloading features of the 82550 and 8255...
Page 164 - Table 72. IPCB Fields
156 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 82550 and 82551QM Specific Information The location and definition of the IPCB fields are summarized in the following table. Table 72. IPCB Fields Field Name Byte Bit(s) Function Description Total TCP/UDP Payload 1Fh:1E...
Page 166 - Driver Interface; checksum operation are shaded.; Table 73. IPCB Structure Checksum Offload
158 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 82550 and 82551QM Specific Information modes of operation. For instance, the driver must guarantee proper values for the Maximum TCP Payload in Large Send mode and VLAN length inclusion. Note: IP fragmentation is not su...
Page 167 - IPCB Field Assignment; Hardware Parsing, or Scheduling modes are used.; Parameters; location of the checksum field.
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 159 82550 and 82551QM Specific Information B.2.2 IPCB Field Assignment The mode bits in the IP Activation field control the checksum operation of the transmit command. • IPv4 Checksum (1bit). When this bit is set to 1, the ...
Page 168 - IPCB usage is enabled only if the 82550 is in the Extended TxCB mode.; Data Flow; checksum is stored in the appropriate location.
160 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 82550 and 82551QM Specific Information first byte of the TCP or UDP header. The controller reads this parameter when Hardware Parsing is clear and TCP/UDP checksum is set. Note: If TCP/UDP headset offset is specified, t...
Page 169 - Tunneling Support; Large Send; Rationale; Stack computes only one header per block.; Driver interface
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 161 82550 and 82551QM Specific Information Note: The partial checksum required by the 82550 is not the partial checksum passed by the Microsoft* IP stack per Microsoft offloading specification, v0.106. For TCP/UDP checksum ...
Page 170 - IPCB Large Send; it will be less than or equal to the maximum TCP payload bytes).; Table 74. IPCB Structure Large Send
162 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 82550 and 82551QM Specific Information Note: To use Large Send, the 82550 should be configured to use dynamic Transmit Buffer Descriptors (TBDs). The driver should ensure transmit buffers associated with the Large Send ...
Page 171 - Headers Parsing
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 163 82550 and 82551QM Specific Information Note: If the IPv4 checksum and TCP/UDP checksum are clear (checksum offload is not requested), frames will be transmitted without computing and replacing the checksum fields conten...
Page 172 - Intermediate Frames Processing
164 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 82550 and 82551QM Specific Information — Fragment offset equals 0. This is expected but not checked by hardware. — IP options are not altered by hardware if they are present. — IP header checksum is calculated by the ch...
Page 173 - Handling the Last Frame
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 165 82550 and 82551QM Specific Information When the headers are finished, they are subject to checksum for processing. The rest of the transmission process is similar to transmission of a small send. This process repeats it...
Page 174 - read access from the PCI will not affect anything.; Performance Considerations; to use the largest possible value for this parameter.; Features Co-existence; Large Send and Checksum; Large Send and checksum are orthogonal.; Large Send and Software Parsing; Large Send cannot be used with software parsing.; Large Send and Scheduling Assist; RCV Checksum Processing
166 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 82550 and 82551QM Specific Information way, it may read an extra TBD (or 8 bytes) after the last valid TBD. The driver is responsible for allocating enough memory for the TBD array. Otherwise, it needs to ensure that an...
Page 175 - Frame Types; right after the optional VLAN field.; Verification Types; Other protocols will not have a checksum.; VLAN Tagging
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 167 82550 and 82551QM Specific Information B.4.1.1 Frame Types • Ethernet v2 . If the Ethernet v2 type field equals 0800h, the first byte of IP header is expected right after the optional VLAN field. • SNAP . The 82550 and ...
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